CN110854106A - Fan-out type antenna packaging structure and packaging method - Google Patents
Fan-out type antenna packaging structure and packaging method Download PDFInfo
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- CN110854106A CN110854106A CN201810947668.5A CN201810947668A CN110854106A CN 110854106 A CN110854106 A CN 110854106A CN 201810947668 A CN201810947668 A CN 201810947668A CN 110854106 A CN110854106 A CN 110854106A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
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- Ceramic Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a fan-out type antenna packaging structure and a packaging method, wherein the packaging structure comprises: rewiring layers; a first metal connection stud on the rewiring layer; a semiconductor chip located on the rewiring layer and electrically connected to the rewiring layer; a first packaging layer covering the rewiring layer, the first metal connecting column and the semiconductor chip and exposing the first metal connecting column; the first antenna metal layer is positioned on the top surface of the first packaging layer and electrically connected with the first metal connecting column; a second metal connection post on the first antenna metal layer; a second packaging layer covering the first antenna metal layer and the second metal connecting column and exposing the second metal connecting column; the second antenna metal layer is positioned on the top surface of the second packaging layer and is electrically connected with the second metal connecting column; and a metal bump on the re-wiring layer. The invention realizes the integration of the multi-layer antenna metal layer, effectively reduces the packaging volume and has higher integration level and electrical stability.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a fan-out type antenna packaging structure and a packaging method.
Background
Lower cost, more reliable, faster, and higher density circuits are sought after goals for integrated circuit packaging. In the future, integrated circuit packages will increase the integration density of various electronic components by continually reducing the minimum feature size. Currently, common packaging methods include: wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Packaging (Fan-Out Wafer Level Package, FOWLP), Flip Chip (Flip Chip), stack on Packaging (POP), and the like. Among them, the fan-out wafer level package has become one of the more advanced packaging methods due to its more input/output ports (I/O) and better integration flexibility.
With the popularization of high-tech electronic products and the increase of the demands of people, especially in order to match the demands of people for movement, most high-tech electronic products have increased wireless communication functions at present.
Generally, the conventional antenna structure usually has the antenna directly fabricated on the surface of the circuit board, which causes the antenna to occupy additional area of the circuit board and has poor integration. For various high-tech electronic products, the use of a larger circuit board means that the high-tech electronic products occupy a larger volume, which is contrary to the demand of people for miniaturization and convenience of the high-tech electronic products, and therefore, how to reduce the area of the circuit board occupied by the antenna and reduce the volume of the antenna packaging structure to improve the integration performance of the antenna packaging structure is a problem to be overcome by these electronic devices.
Therefore, a new fan-out antenna package structure and a new package method are needed to solve the above-mentioned problems caused by the area of the circuit board occupied by the antenna.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a fan-out antenna package structure and a package method thereof, for solving the problems of the prior art that an antenna occupies an area of a circuit board, resulting in a bulky antenna package structure and poor integration.
In view of the above, the present invention provides a fan-out antenna package structure, including:
a rewiring layer including opposing first and second faces;
a first metal connecting column located on the second surface of the rewiring layer and electrically connected with the rewiring layer;
a semiconductor chip located on the second surface of the rewiring layer and electrically connected to the rewiring layer;
the first packaging layer covers the rewiring layer, the first metal connecting column and the semiconductor chip, and the first metal connecting column is exposed on the top surface of the first packaging layer;
the first antenna metal layer is positioned on the top surface of the first packaging layer and is electrically connected with the first metal connecting column;
a second metal connection post on the first antenna metal layer;
the second packaging layer covers the first antenna metal layer and the second metal connecting column, and the top surface of the second packaging layer exposes the second metal connecting column;
the second antenna metal layer is positioned on the top surface of the second packaging layer and is electrically connected with the second metal connecting column; and
a metal bump on a first side of the re-wiring layer.
Optionally, the semiconductor chip further includes one or a combination of a metal pillar and a metal ball connected to a contact pad of the semiconductor chip.
Optionally, the metal pillar is covered by the redistribution layer, and the metal pillar is electrically connected to the redistribution layer through the metal ball.
Optionally, the height of the first metal connection column is greater than the height of the semiconductor chip.
Optionally, a first metal connection block is further included between the first metal connection pillar and the redistribution layer, and a cross-sectional area of the first metal connection block is larger than that of the first metal connection pillar; and a second metal connecting block is further arranged between the second metal connecting column and the first antenna metal layer, and the cross sectional area of the second metal connecting block is larger than that of the second metal connecting column.
Optionally, the height of the second metal connection pillar is smaller than the height of the first metal connection pillar.
Optionally, the first encapsulation layer includes one of an epoxy resin layer, a polyimide layer, and a silicone layer; the second packaging layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer.
Optionally, the redistribution layer includes a patterned dielectric layer and a patterned metal routing layer stacked in sequence.
Optionally, the dielectric layer includes an epoxy resin layer, a silica gel layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer, and one or more combinations of fluorine-containing glass layers, and the metal wiring layer includes one or more combinations of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer, and a titanium layer.
Optionally, the metal bump includes one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump.
The invention also provides a fan-out type antenna packaging method, which comprises the following steps:
s1: providing a supporting substrate, and forming a separation layer on the supporting substrate;
s2: forming a rewiring layer on the separation layer, wherein the rewiring layer comprises a first surface and an opposite second surface, and the first surface is in contact with the separation layer;
s3: forming a first metal connecting column on the second surface of the rewiring layer and electrically connecting the rewiring layer;
s4: providing a semiconductor chip, bonding the semiconductor chip on the second surface of the rewiring layer, and electrically connecting the semiconductor chip with the rewiring layer;
s5: packaging the rewiring layer, the first metal connecting column and the semiconductor chip by adopting a first packaging layer, and exposing the first metal connecting column on the top surface of the first packaging layer;
s6: forming a first antenna metal layer on the top surface of the first packaging layer, wherein the first antenna metal layer is electrically connected with the first metal connecting column;
s7: forming a second metal connecting column on the first antenna metal layer;
s8: packaging the first antenna metal layer and the second metal connecting column by adopting a second packaging layer, and exposing the second metal connecting column on the top surface of the second packaging layer;
s9: forming a second antenna metal layer on the top surface of the second packaging layer;
s10: stripping the support substrate based on the separation layer to expose the first side of the re-routing layer; and
s11: and forming a metal bump on the first surface of the rewiring layer.
Optionally, the support base includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate; the separation layer comprises one of an adhesive tape and a polymer layer, and the curing method of the polymer layer comprises one of an ultraviolet curing method and a thermal curing method.
Optionally, the forming the redistribution layer in step S2 includes the following steps:
s2-1: forming a dielectric layer on the surface of the separation layer by adopting a physical vapor deposition process or a chemical vapor deposition process, and etching the dielectric layer to form a patterned dielectric layer;
s2-2: and forming a metal wiring layer on the surface of the patterned dielectric layer by adopting a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and etching the metal wiring layer to form the patterned metal wiring layer.
Optionally, step S2 further includes a loop step of N times formed by the combination of step S2-1 and step S2-2, wherein N ≧ 1.
Optionally, the method for forming the first encapsulation layer in step S5 includes one of compression molding, transfer molding, liquid seal molding, vacuum lamination, and spin coating; the method for forming the second encapsulation layer in step S8 includes one of compression molding, transfer molding, liquid seal molding, vacuum lamination, and spin coating.
Optionally, the step of forming the first metal connection pillar in step S3 includes the following steps:
s3-1: forming a first metal connecting block on the upper surface of the rewiring layer, wherein the first metal connecting block is electrically connected with the rewiring layer;
s3-2: and forming the first metal connecting column on the upper surface of the first metal connecting block by adopting a wire welding process, wherein the cross-sectional area of the first metal connecting block is larger than that of the first metal connecting column.
Optionally, the step of forming the second metal connection pillar in step S7 includes the following steps:
s7-1: forming a second metal connecting block on the upper surface of the first antenna metal layer, wherein the second metal connecting block is electrically connected with the first antenna metal layer;
s7-2: and forming the second metal connecting column on the upper surface of the second metal connecting block by adopting a wire welding process, wherein the cross-sectional area of the second metal connecting block is larger than that of the second metal connecting column.
The fan-out type antenna packaging structure and the packaging method have the following beneficial effects:
1) the invention adopts the rewiring layer and the metal connecting column penetrating through the packaging layer to realize the integration of the metal layers of the multi-layer antenna, thereby greatly improving the efficiency and the performance of the antenna and improving the integration of the antenna packaging structure;
2) according to the invention, the semiconductor chip is arranged in the packaging layer, so that on one hand, the space volume is saved, and the volume of the packaging structure is smaller; on the other hand, the packaging layer realizes the packaging of the semiconductor chip while packaging the metal connecting column, thereby improving the stability of the semiconductor chip and saving the cost;
3) before the semiconductor chip is jointed, the metal connecting column is formed firstly, so that the cleanliness of the joint surface of the metal connecting column and the rewiring layer is improved, and the stability of the metal connecting column is improved;
4) the fan-out type packaging method is adopted to package the antenna structure, so that the packaging volume can be effectively reduced, the antenna packaging structure has higher integration level and better packaging performance, and the fan-out type packaging method has wide application prospect in the field of semiconductor packaging.
Drawings
Fig. 1 is a flow chart illustrating a packaging method of a fan-out antenna according to the present invention.
Fig. 2 to 15 are schematic structural diagrams of steps of the antenna packaging method of the present invention, wherein fig. 15 is a schematic structural diagram of a fan-out antenna packaging structure of the present invention.
Description of the element reference numerals
101 supporting substrate
102 separating layers
103 rewiring layer
113 dielectric layer
123 metal wiring layer
104 first metal connecting column
114 first metal connecting block
105 semiconductor chip
115 metal column
125 metal ball
106 first encapsulation layer
107 first antenna metal layer
108 second metal connecting column
118 second metal connecting block
109 second encapsulation layer
110 second antenna metal layer
111 metal bump
S1-S11
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 15. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 15, the present invention provides a fan-out antenna package structure, which includes: the redistribution layer 103, the first metal connection pillar 104, the semiconductor chip 105, the first package layer 106, the first antenna metal layer 107, the second metal connection pillar 108, the second package layer 109, the second antenna metal layer 110, and the metal bump 111.
Specifically, the redistribution layer 103 includes a first surface and a second surface opposite to the first surface, and the first metal connection stud 104 is located on the second surface of the redistribution layer 103 and electrically connected to the redistribution layer 103; the semiconductor chip 105 is located on a second side of the redistribution layer 103 and electrically connected to the redistribution layer 103; the first packaging layer 106 covers the redistribution layer 103, the first metal connection pillar 104 and the semiconductor chip 105, and the first metal connection pillar 104 is exposed from the top surface of the first packaging layer 106; the first antenna metal layer 107 is located on the top surface of the first package layer 106, and the first antenna metal layer 107 is electrically connected to the first metal connection pillar 104; the second metal connection stud 108 is located on the first antenna metal layer 107; the second packaging layer 109 covers the first antenna metal layer 107 and the second metal connection post 108, and the second metal connection post 108 is exposed from the top surface of the second packaging layer 109; the second antenna metal layer 110 is located on the top surface of the second package layer 109, and the second antenna metal layer 110 is electrically connected to the second metal connection pillar 108; the metal bump 111 is located on a first surface of the redistribution layer 103. In this embodiment, the redistribution layer 103, the first metal connection column 104 and the second metal connection column 108 are adopted to realize the integration of the first antenna metal layer 107 and the second antenna metal layer 110, so that the efficiency and performance of the antenna and the integration of the antenna packaging structure can be improved; the semiconductor chip 105 is disposed in the first package layer 106, so that the space and volume are saved, the volume of the package structure is further reduced, and the integration level and the package performance of the antenna package structure are improved.
As a further embodiment of this embodiment, the redistribution layer 103 includes a patterned dielectric layer 113 and a patterned metal wiring layer 123 stacked in sequence. Further, the dielectric layer 113 includes one or a combination of two or more of an epoxy resin layer, a silica gel layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer, and a phosphosilicate glass layer, and the metal wiring layer 123 includes one or a combination of two or more of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer, and a titanium layer. The specific number and type of dielectric layers 113 and metal wiring layers 123 in the redistribution layer 103 are not limited herein.
As a further embodiment of this embodiment, a first metal connection pad 114 is further included between the first metal connection post 104 and the redistribution layer 103, preferably, the first metal connection post 104 is located at the symmetric center of the first metal connection pad 114, and the cross-sectional area of the first metal connection pad 114 is larger than that of the first metal connection post 104, so that the contact area between the first metal connection pad 114 and the metal wiring layer 123 is increased, and the electrical stability is improved.
As shown in fig. 15, the first metal connection stud 104 is located on the second side of the redistribution layer 103 and is connected to the metal wiring layer 123 through the first metal connection pad 114. Further, the material of the first metal connection post 104 and the first metal connection block 114 includes one or a combination of Au, Ag, Cu and Al, which is not limited herein.
As a further embodiment of this embodiment, the semiconductor chip 105 electrically connected to the redistribution layer 103 further includes one or a combination of metal posts 115 and metal balls 125 connected to contact pads (not shown) of the semiconductor chip 105. The metal posts 115 and the metal balls 125 can be directly used as electrical connection terminals of the semiconductor chip 105, which facilitates process operation and avoids wire bonding on the contact pads of the semiconductor chip 105, thereby improving the stability and yield of the semiconductor chip 105.
As shown in fig. 15, the semiconductor chip 105 includes the metal pillar 115 having a certain height and the metal ball 125 connected to the metal pillar 115, the height of the metal pillar 115 ranges from 25 μm to 250 μm, and the material of the metal pillar 115 and the metal ball 125 includes one or a combination of copper, nickel, tin and silver. The number and type of the semiconductor chips 105 are not limited herein.
As a further embodiment of this embodiment, the side surfaces of the metal pillars 115 are covered by the dielectric layer 113 in the redistribution layer 103, and the metal pillars 113 are electrically connected to the metal wiring layer 123 in the redistribution layer 103 through the metal balls 125. Since the side surface of the metal pillar 115 having a certain height is covered by the dielectric layer 113, the electrical stability between the semiconductor chip 105 and the redistribution layer 103 can be further enhanced. The metal balls 125 at the ends of the metal posts 115 can improve the packaging efficiency, for example, after flux is coated on the redistribution layer 103, the semiconductor chip 105 is placed at a corresponding position, and then the semiconductor chip 105 can be quickly and conveniently soldered on the redistribution layer 103 by reflow soldering, so as to achieve electrical connection.
As a further embodiment of this embodiment, the height of the first metal connection pillar 104 is greater than the height of the semiconductor chip 105, that is, the sum of the heights of the first metal connection pillar 104 and the first metal connection block 114 is greater than the height of the second surface of the semiconductor chip 105 exposed on the redistribution layer 103. So that the first packaging layer 106 can cover the semiconductor chip 105, and the semiconductor chip 105 is protected; the height of the first metal connection post 104 is greater than that of the semiconductor chip 105, which also provides space for the distribution of the first antenna metal layer 107, i.e., the first package layer 106 can be distributed on the top surface; and the height of the first metal connection column 104 is greater than that of the semiconductor chip 105, the distance between the first antenna metal layer 107 and the semiconductor chip 105 can be increased, and the packaging performance is improved. The height of the first metal connection post 104 is preferably, but not limited to, 100 μm to 400 μm.
Specifically, the first package layer 106 includes one of an epoxy layer, a polyimide layer, and a silicone layer, and the top surface of the first package layer 106 is a ground or polished flat surface to improve the contact performance between the first antenna metal layer 107 and the first metal connection pillar 104. The material of the first antenna metal layer 107 may be Au, Cu, etc., and the first antenna metal layer 107 may have various patterns according to performance requirements, which is not limited herein.
As a further embodiment of this embodiment, a second metal connection block 118 is further included between the second metal connection post 108 on the first antenna metal layer 107 and the first antenna metal layer 107, and the cross-sectional area of the second metal connection block 118 is larger than that of the second metal connection post 108. Preferably, the second metal connection pillar 108 is located at the symmetric center of the second metal connection block 118, so that the contact area between the second metal connection block 118 and the first antenna metal layer 107 is increased, and the electrical stability is improved. Further, the material of the second metal connection post 108 and the second metal connection block 118 includes one or a combination of Au, Ag, Cu and Al, which is not limited herein.
As a further embodiment of this embodiment, the height of the second metal connection pillar 108 is smaller than the height of the first metal connection pillar 104, thereby further reducing the volume of the package structure.
Specifically, the second encapsulation layer 109 includes one of an epoxy layer, a polyimide layer, and a silicone layer, and the top surface of the second encapsulation layer 109 is a ground or polished flat surface to improve the quality of the second antenna metal layer 110. The material of the second antenna metal layer 110 may be Au, Cu, etc., and the second antenna metal layer 110 may have various patterns according to performance requirements, which is not limited herein. As shown in fig. 15, the second antenna metal layer 110 is formed on the second package layer 109, and the second antenna metal layer 110 is protruded on the surface of the second package layer 109.
As a further embodiment of the embodiment, the metal bump 111 includes one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump. The metal bump 111 may further include a pillar metal connected to the metal bump 111, which is not limited herein.
As shown in fig. 15, the semiconductor chip 105 is bonded to the second surface of the redistribution layer 103, and the semiconductor chip 105 is electrically connected to the first antenna metal layer 107 and the second antenna metal layer 110 through the redistribution layer 103, the first metal connection stud 104 and the second metal connection stud 108 to implement the function of an antenna. Therefore, the integration of multiple layers of antenna metal layers is further realized, the efficiency and the performance of the antenna are greatly improved, the integration of the antenna packaging structure is further improved, the packaging volume is reduced, and the antenna packaging structure has higher integration level.
As shown in fig. 1, this embodiment further provides a fan-out antenna packaging method, including the following steps:
s1: providing a supporting substrate, and forming a separation layer on the supporting substrate;
s2: forming a rewiring layer on the separation layer, wherein the rewiring layer comprises a first surface and an opposite second surface, and the first surface is in contact with the separation layer;
s3: forming a first metal connecting column on the second surface of the rewiring layer and electrically connecting the rewiring layer;
s4: providing a semiconductor chip, bonding the semiconductor chip on the second surface of the rewiring layer, and electrically connecting the semiconductor chip with the rewiring layer;
s5: packaging the rewiring layer, the first metal connecting column and the semiconductor chip by adopting a first packaging layer, and exposing the first metal connecting column on the top surface of the first packaging layer;
s6: forming a first antenna metal layer on the top surface of the first packaging layer, wherein the first antenna metal layer is electrically connected with the first metal connecting column;
s7: forming a second metal connecting column on the first antenna metal layer;
s8: packaging the first antenna metal layer and the second metal connecting column by adopting a second packaging layer, and exposing the second metal connecting column on the top surface of the second packaging layer;
s9: forming a second antenna metal layer on the top surface of the second packaging layer;
s10: stripping the support substrate based on the separation layer to expose the first side of the re-routing layer; and
s11: and forming a metal bump on the first surface of the rewiring layer.
Specifically, in this embodiment, the first metal connection pillar is formed before the semiconductor chip is bonded, so that the cleanliness of the bonding surface between the first metal connection pillar and the rewiring layer is improved, and the stability of the first metal connection pillar can be improved; the first packaging layer packages the first metal connecting column, and simultaneously packages the semiconductor chip, so that the stability of the semiconductor chip is improved, and the cost is saved; the fan-out type packaging method is adopted to package the antenna structure, so that the packaging volume can be effectively reduced, and the antenna packaging structure has higher integration level and better packaging performance. As shown in fig. 2 to 15, schematic structural diagrams of the steps of the antenna packaging method of the present invention are shown.
As shown in fig. 2, step S1 is performed to provide a supporting substrate 101, and a separation layer 102 is formed on the supporting substrate 101.
As a further embodiment of this embodiment, the support base 101 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the supporting substrate 101 is preferably a glass substrate, which has a low cost, is easy to form the separation layer 102 on the surface thereof, and can reduce the difficulty of the subsequent stripping process.
As a further example of this embodiment, the separation layer 102 includes one of an adhesive tape and a polymer layer, and the polymer layer is first applied on the surface of the supporting substrate 101 by a spin coating process and then cured and formed by a uv curing or thermal curing process.
Specifically, in this embodiment, the separation layer 102 is a polymer layer of the LTHC light-to-heat conversion layer, so that the subsequent step S10 may heat the LTHC light-to-heat conversion layer based on laser light to separate the supporting substrate 101 from the LTHC light-to-heat conversion layer.
As shown in fig. 3, step S2 is performed to form a redistribution layer 103 on the separation layer 102, where the redistribution layer 103 includes a first surface connected to the separation layer 102 and an opposite second surface.
As a further embodiment of this embodiment, in step S2, the step of fabricating the rewiring layer 103 includes the steps of:
s2-1: forming a dielectric layer 113 on the surface of the separation layer 102 by adopting a physical vapor deposition process or a chemical vapor deposition process, and etching the dielectric layer 113 to form a patterned dielectric layer 113;
s2-2: and forming a metal wiring layer 123 on the surface of the patterned dielectric layer 113 by adopting a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and etching the metal wiring layer 123 to form the patterned metal wiring layer 123.
Specifically, the material of the dielectric layer 113 includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass. The material of the metal wiring layer 123 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. Optionally, the step S2 may further include N times of loop steps formed by the combination of the steps S2-1 and S2-2, wherein N ≧ 1, which is not limited herein.
As shown in fig. 4, step S3 is then performed to form a first metal connection stud 104 on the second surface of the redistribution layer 103 and electrically connect to the redistribution layer 103.
As a further example of this embodiment, the step of forming the first metal connection stud 104 in step S3 includes the steps of:
s3-1: forming a first metal connection block 114 on an upper surface of the redistribution layer 103, wherein the first metal connection block 114 is electrically connected to the redistribution layer 103;
s3-2: the first metal connection post 104 is formed on the upper surface of the first metal connection block 114 by using a wire bonding process, and the cross-sectional area of the first metal connection block 114 is larger than that of the first metal connection post 104, preferably, the first metal connection post 104 is located at the symmetric center of the first metal connection block 114, so that the contact area between the first metal connection block 114 and the metal wiring layer 123 is increased, and the electrical stability is improved.
Specifically, the bonding process includes one of a thermocompression bonding process, an ultrasonic bonding process, and a thermocompression ultrasonic bonding process; the material of the first metal connection post 104 and the first metal connection block 114 includes one or a combination of Au, Ag, Cu, and Al.
As shown in fig. 5, step S4 is performed to provide a semiconductor chip 105, and the semiconductor chip 105 is bonded to the second surface of the redistribution layer 103 and electrically connected to the redistribution layer 103. The number and types of the semiconductor chips 105 are not limited herein.
Specifically, the semiconductor chip 105 further includes the metal pillar 115 having a certain height and the metal ball 125 connected to the metal pillar 115, the height of the metal pillar 115 ranges from 25 μm to 250 μm, and the material of the metal pillar 115 and the metal ball 125 includes one or a combination of copper, nickel, tin and silver. The side surfaces of the metal pillars 115 are covered by the dielectric layer 113 in the redistribution layer 103, and the metal pillars 113 are electrically connected to the metal routing layer 123 in the redistribution layer 103 through the metal balls 125. Since the side surface of the metal pillar 115 having a certain height is covered by the dielectric layer 113, the electrical stability between the semiconductor chip 105 and the redistribution layer 103 can be further enhanced. The metal balls 125 at the ends of the metal posts 115 can improve the packaging efficiency, for example, after flux is coated on the redistribution layer 103, the semiconductor chip 105 is placed at a corresponding position, and then the semiconductor chip 105 can be quickly and conveniently soldered on the redistribution layer 103 by reflow soldering, so as to achieve electrical connection.
As a further embodiment of this embodiment, the height of the first metal connection pillar 104 is greater than the height of the semiconductor chip 105, that is, the sum of the heights of the first metal connection pillar 104 and the first metal connection block 114 is greater than the height of the second surface of the semiconductor chip 105 exposed on the redistribution layer 103. So that the first packaging layer 106 can cover the semiconductor chip 105, and the semiconductor chip 105 is protected; the height of the first metal connection post 104 is greater than that of the semiconductor chip 105, which also provides space for the distribution of the first antenna metal layer 107, i.e., the first package layer 106 can be distributed on the top surface; and the height of the first metal connection column 104 is greater than that of the semiconductor chip 105, the distance between the first antenna metal layer 107 and the semiconductor chip 105 can be increased, and the packaging performance is improved. The height of the first metal connection post 104 is preferably, but not limited to, 100 μm to 400 μm.
As shown in fig. 6 to 7, step S5 is performed to encapsulate the redistribution layer 103, the first metal connection pillar 104 and the semiconductor chip 105 with the first encapsulation layer 106, and expose the first metal connection pillar 104 from the top surface of the first encapsulation layer 106.
As a further embodiment of the embodiment, the method for forming the first encapsulation layer 106 in step S5 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating, and the material of the first encapsulation layer 106 includes one of polyimide, silicone and epoxy resin.
Specifically, after the first encapsulation layer 106 is formed, a grinding or polishing method is further adopted to act on the top surface of the first encapsulation layer 106, so as to provide a flat top surface of the first encapsulation layer 106, and improve the quality of a subsequently formed first antenna metal layer.
As shown in fig. 8, step S6 is performed to form a first antenna metal layer 107 on the top surface of the first package layer 106, wherein the first antenna metal layer 107 is electrically connected to the first metal connection pillar 104.
Specifically, the first antenna metal layer 107 may be formed on the top surface of the first package layer 106 by using a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process, or a chemical plating process, and then the first antenna metal layer 107 to be patterned may be formed by using an etching process.
As shown in fig. 9, step S7 is performed to form a second metal connection stud 108 on the first antenna metal layer 107.
As a further example of this embodiment, forming the second metal connection stud 108 in step S7 includes the steps of:
s7-1: forming a second metal connection pad 118 on the upper surface of the first antenna metal layer 107, wherein the second metal connection pad 118 is electrically connected to the first antenna metal layer 107;
s7-2: the second metal connection post 108 is formed on the upper surface of the second metal connection block 118 by using a wire bonding process, and the cross-sectional area of the second metal connection block 118 is larger than that of the second metal connection post 108, preferably, the second metal connection post 108 is located at the symmetric center of the second metal connection block 118, so that the contact area between the second metal connection block 118 and the first antenna metal layer 107 is increased, and the electrical stability is improved.
Specifically, the bonding process includes one of a thermocompression bonding process, an ultrasonic bonding process, and a thermocompression ultrasonic bonding process; the material of the second metal connection post 108 and the second metal connection block 118 includes one or a combination of Au, Ag, Cu, and Al.
As shown in fig. 10 to 11, step S8 is performed to encapsulate the first antenna metal layer 107 and the second metal connection post 108 with a second encapsulation layer 109, and expose the second metal connection post 108 from the top surface of the second encapsulation layer 109.
As a further example of the embodiment, the method for forming the second encapsulation layer 109 in step S8 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating, and the material of the second encapsulation layer 109 includes one of polyimide, silicone, and epoxy resin.
Specifically, after the second encapsulation layer 109 is formed, a grinding or polishing method is further adopted to act on the top surface of the second encapsulation layer 109, so as to provide a flat top surface of the second encapsulation layer 109, and improve the quality of a subsequently formed second antenna metal layer.
As shown in fig. 12, step S9 is performed to form a second antenna metal layer 110 on the top surface of the second package layer 109, and the second antenna metal layer 110 is electrically connected to the second metal connection pillar 108.
Specifically, the second antenna metal layer 110 may be formed on the top surface of the second package layer 109 by using a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process, or a chemical plating process, and then the second antenna metal layer 110 to be patterned may be formed by using an etching process.
As shown in fig. 13, step S10 is performed to peel off the supporting substrate 101 based on the separation layer 102 to expose the first surface of the redistribution layer 103.
Specifically, the LTHC light-to-heat conversion layer is heated based on laser light to separate the supporting substrate 101 from each other at the LTHC light-to-heat conversion layer.
As shown in fig. 14 to 15, step S11 is performed to form a metal bump 111 on the first surface of the redistribution layer 103.
Specifically, after the package structure obtained in step S10 is turned over by 180 degrees, the patterned dielectric layer 113 and the patterned metal wiring layer 123 are continuously formed on the first surface of the redistribution layer 103 to serve as the contact layer of the metal bump 111, and then the metal bump 111 is formed on the metal wiring layer 123. The metal bump 111 includes one of a tin solder, a silver solder, and a gold-tin alloy solder. The metal bump 111 may further include a pillar metal connected to the metal bump 111, which is not limited herein.
In summary, the fan-out antenna packaging structure and the packaging method of the invention have the following beneficial effects: 1) the invention adopts the rewiring layer and the metal connecting column penetrating through the packaging layer to realize the integration of the metal layers of the multi-layer antenna, thereby greatly improving the efficiency and the performance of the antenna and improving the integration of the antenna packaging structure; 2) according to the invention, the semiconductor chip is arranged in the packaging layer, so that on one hand, the space volume is saved, and the volume of the packaging structure is smaller; on the other hand, the packaging layer realizes the packaging of the semiconductor chip while packaging the metal connecting column, thereby improving the stability of the semiconductor chip and saving the cost; 3) before the semiconductor chip is jointed, the metal connecting column is formed firstly, so that the cleanliness of the joint surface of the metal connecting column and the rewiring layer is improved, and the stability of the metal connecting column is improved; 4) the fan-out type packaging method is adopted to package the antenna structure, so that the packaging volume can be effectively reduced, the antenna packaging structure has higher integration level and better packaging performance, and the fan-out type packaging method has wide application prospect in the field of semiconductor packaging. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (17)
1. A fan-out antenna package, the package comprising:
a rewiring layer including opposing first and second faces;
a first metal connecting column located on the second surface of the rewiring layer and electrically connected with the rewiring layer;
a semiconductor chip located on the second surface of the rewiring layer and electrically connected to the rewiring layer;
the first packaging layer covers the rewiring layer, the first metal connecting column and the semiconductor chip, and the first metal connecting column is exposed on the top surface of the first packaging layer;
the first antenna metal layer is positioned on the top surface of the first packaging layer and is electrically connected with the first metal connecting column;
a second metal connection post on the first antenna metal layer;
the second packaging layer covers the first antenna metal layer and the second metal connecting column, and the top surface of the second packaging layer exposes the second metal connecting column;
the second antenna metal layer is positioned on the top surface of the second packaging layer and is electrically connected with the second metal connecting column; and
a metal bump on a first side of the re-wiring layer.
2. The fan-out antenna package structure of claim 1, wherein: the semiconductor chip further comprises one or a combination of metal posts and metal balls connected with the contact pads of the semiconductor chip.
3. The fan-out antenna package structure of claim 2, wherein: the side surface of the metal column is coated by the rewiring layer, and the metal column is electrically connected with the rewiring layer through the metal ball.
4. The fan-out antenna package structure of claim 1, wherein: the height of the first metal connecting column is larger than that of the semiconductor chip.
5. The fan-out antenna package structure of claim 1, wherein: a first metal connecting block is further arranged between the first metal connecting column and the rewiring layer, and the cross-sectional area of the first metal connecting block is larger than that of the first metal connecting column; and a second metal connecting block is further arranged between the second metal connecting column and the first antenna metal layer, and the cross sectional area of the second metal connecting block is larger than that of the second metal connecting column.
6. The fan-out antenna package structure of claim 1, wherein: the height of the second metal connecting column is smaller than that of the first metal connecting column.
7. The fan-out antenna package structure of claim 1, wherein: the first packaging layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer; the second packaging layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer.
8. The fan-out antenna package structure of claim 1, wherein: the rewiring layer comprises a patterned dielectric layer and a patterned metal wiring layer which are sequentially stacked.
9. The fan-out antenna package structure of claim 8, wherein: the dielectric layer comprises an epoxy resin layer, a silica gel layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer and a phosphorosilicate glass layer, one or more than two of fluorine-containing glass layers are combined, and the metal wiring layer comprises one or more than two of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer and a titanium layer.
10. The fan-out antenna package structure of claim 9, wherein: the metal bump comprises one of a copper metal bump, a nickel metal bump, a tin metal bump and a silver metal bump.
11. A fan-out antenna packaging method is characterized by comprising the following steps:
s1: providing a supporting substrate, and forming a separation layer on the supporting substrate;
s2: forming a rewiring layer on the separation layer, wherein the rewiring layer comprises a first surface and an opposite second surface, and the first surface is in contact with the separation layer;
s3: forming a first metal connecting column on the second surface of the rewiring layer and electrically connecting the rewiring layer;
s4: providing a semiconductor chip, bonding the semiconductor chip on the second surface of the rewiring layer, and electrically connecting the semiconductor chip with the rewiring layer;
s5: packaging the rewiring layer, the first metal connecting column and the semiconductor chip by adopting a first packaging layer, and exposing the first metal connecting column on the top surface of the first packaging layer;
s6: forming a first antenna metal layer on the top surface of the first packaging layer, wherein the first antenna metal layer is electrically connected with the first metal connecting column;
s7: forming a second metal connecting column on the first antenna metal layer;
s8: packaging the first antenna metal layer and the second metal connecting column by adopting a second packaging layer, and exposing the second metal connecting column on the top surface of the second packaging layer;
s9: forming a second antenna metal layer on the top surface of the second packaging layer;
s10: stripping the support substrate based on the separation layer to expose the first side of the re-routing layer; and
s11: and forming a metal bump on the first surface of the rewiring layer.
12. The fan-out antenna packaging method of claim 11, wherein: the supporting base comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate; the separation layer comprises one of an adhesive tape and a polymer layer, and the curing method of the polymer layer comprises one of an ultraviolet curing method and a thermal curing method.
13. The fan-out antenna packaging method of claim 11, wherein: forming the re-wiring layer in step S2 includes the steps of:
s2-1: forming a dielectric layer on the surface of the separation layer by adopting a physical vapor deposition process or a chemical vapor deposition process, and etching the dielectric layer to form a patterned dielectric layer;
s2-2: and forming a metal wiring layer on the surface of the patterned dielectric layer by adopting a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and etching the metal wiring layer to form the patterned metal wiring layer.
14. The fan-out antenna packaging method of claim 13, wherein: the step S2 further includes N times of circulation steps formed by the combination of the step S2-1 and the step S2-2, wherein N is larger than or equal to 1.
15. The fan-out antenna packaging method of claim 11, wherein: the method for forming the first encapsulation layer in step S5 includes one of compression molding, transfer molding, liquid seal molding, vacuum lamination, and spin coating; the method for forming the second encapsulation layer in step S8 includes one of compression molding, transfer molding, liquid seal molding, vacuum lamination, and spin coating.
16. The fan-out antenna packaging method of claim 11, wherein: the step of forming the first metal connection pillar in the step S3 includes the steps of:
s3-1: forming a first metal connecting block on the upper surface of the rewiring layer, wherein the first metal connecting block is electrically connected with the rewiring layer;
s3-2: and forming the first metal connecting column on the upper surface of the first metal connecting block by adopting a wire welding process, wherein the cross-sectional area of the first metal connecting block is larger than that of the first metal connecting column.
17. The fan-out antenna packaging method of claim 11, wherein: the step of forming the second metal connection pillar in the step S7 includes the steps of:
s7-1: forming a second metal connecting block on the upper surface of the first antenna metal layer, wherein the second metal connecting block is electrically connected with the first antenna metal layer;
s7-2: and forming the second metal connecting column on the upper surface of the second metal connecting block by adopting a wire welding process, wherein the cross-sectional area of the second metal connecting block is larger than that of the second metal connecting column.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810947668.5A CN110854106A (en) | 2018-08-20 | 2018-08-20 | Fan-out type antenna packaging structure and packaging method |
| US16/413,226 US10804229B2 (en) | 2018-08-20 | 2019-05-15 | Fan-out antenna package structure and packaging method |
| US17/019,093 US11302658B2 (en) | 2018-08-20 | 2020-09-11 | Fan-out antenna package structure and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810947668.5A CN110854106A (en) | 2018-08-20 | 2018-08-20 | Fan-out type antenna packaging structure and packaging method |
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| CN110854106A true CN110854106A (en) | 2020-02-28 |
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