CN110853556A - Pulse generating circuit - Google Patents

Pulse generating circuit Download PDF

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Publication number
CN110853556A
CN110853556A CN201911010248.5A CN201911010248A CN110853556A CN 110853556 A CN110853556 A CN 110853556A CN 201911010248 A CN201911010248 A CN 201911010248A CN 110853556 A CN110853556 A CN 110853556A
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China
Prior art keywords
voltage
terminal
node
transistor
circuit
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CN201911010248.5A
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Chinese (zh)
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CN110853556B (en
Inventor
林志隆
赖柏成
林祐陞
尤建盛
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AU Optronics Corp
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AU Optronics Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals

Abstract

A pulse generating circuit comprises an input circuit, a voltage stabilizing control circuit and a pull-up circuit. The input circuit receives a first voltage and is coupled to a first node, and the input circuit outputs the first voltage to the first node in response to a first signal. The voltage stabilizing circuit receives a first voltage and a second voltage and is coupled to the first node, the voltage stabilizing circuit responds to the first voltage to store the first voltage to the second node of the voltage stabilizing circuit, and the voltage stabilizing circuit stabilizes the voltage of the first node according to the voltage of the second node. The voltage stabilization control circuit receives a second voltage and a second signal, adjusts the voltage of a third node of the voltage stabilization control circuit to be the second voltage or the second signal in response to the voltage of the first node and the first and second clock signals, and controls the voltage of the second node according to the voltage of the third node. The pull-up circuit receives a third voltage and is coupled to the first node and the output end, and the pull-up circuit outputs the third voltage to the output end in response to the voltage of the first node.

Description

Pulse generating circuit
Technical Field
The present disclosure relates to a pulse generating circuit, and more particularly, to a pulse generating circuit that generates a wide pulse.
Background
In a conventional display panel architecture, the gate driver architecture cannot output pulses long enough, so that the light sensing circuit in the display panel cannot have complete sensing time, resulting in erroneous operation of the light sensing circuit. Therefore, it is necessary to design a pulse generating circuit capable of outputting a pulse signal with a sufficient width and stability so that the photo sensing circuit can have a sufficient circuit operation time.
Disclosure of Invention
In one embodiment of the present disclosure, a pulse generating circuit includes an input circuit, a voltage stabilizing circuit, a voltage stabilization control circuit, and a pull-up circuit. The input circuit is used for receiving a first voltage and is coupled to the first node, and the input circuit outputs the first voltage to the first node in response to a first signal. The voltage stabilizing circuit is used for receiving a first voltage and a second voltage and is coupled to the first node, the voltage stabilizing circuit responds to the first voltage and stores the first voltage to the second node of the voltage stabilizing circuit, and the voltage stabilizing circuit stabilizes the voltage of the first node according to the voltage of the second node. The voltage stabilization control circuit is used for receiving a second voltage and a second signal, adjusting the voltage of a third node of the voltage stabilization control circuit to be the second voltage or the second signal in response to the voltage of the first node, the first clock signal and the second clock signal, and controlling the voltage of the second node according to the voltage of the third node. The pull-up circuit is used for receiving a third voltage and is coupled to the first node and the output end, and the pull-up circuit responds to the voltage of the first node and outputs the third voltage to the output end.
In summary, the pulse generating circuit can output the voltage of the third voltage or the fourth voltage to the output terminal according to different input signals, and stabilize the voltage of the output terminal by using the voltage stabilizing circuit.
Drawings
Fig. 1 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
Fig. 2 illustrates a block diagram of a gate driver according to an embodiment of the present disclosure.
FIG. 3 shows a circuit diagram of a shift register according to an embodiment of the disclosure.
Fig. 4 shows a signal timing diagram corresponding to the shift register circuit of fig. 3.
Fig. 5 shows a pulse generation circuit diagram according to an embodiment of the present disclosure.
Fig. 6 shows a timing diagram of signals corresponding to the pulse generating circuit of fig. 5.
Fig. 7 is a schematic diagram illustrating an operation of a pulse generating circuit in an input time interval according to an embodiment of the disclosure.
Fig. 8 is a schematic diagram illustrating an operation of the pulse generating circuit during an enabling time interval according to an embodiment of the disclosure.
Fig. 9 is a schematic diagram illustrating an operation of a pulse generating circuit in a first pull-down time interval according to an embodiment of the disclosure.
Fig. 10 is a schematic diagram illustrating an operation of the pulse generating circuit in the second pull-down time interval according to an embodiment of the disclosure.
Fig. 11 illustrates an operation of the pulse generating circuit in a stable time interval according to an embodiment of the disclosure.
Description of reference numerals:
100: display panel
110: sequential control circuit
120: gate driver
122: shift register circuit
124: shift register circuit
126: pulse generating circuit
126 a: input circuit
126 b: voltage stabilizing circuit
126 c: voltage stabilization control circuit
126 d: pull-up circuit
126 e: pull-down circuit
130: source driver
140: image display area
142: display pixel
XCK: a first clock signal
CK: the second clock signal
TC1, TC 2: signal line
GL1, GL2, GL3, GLN, GLM: scanning line
SL1, SL2, SL3, SLK: data line
T1-T13, TS 1-TS 7: transistor with a metal gate electrode
VDDH, VDD, VH, VGH, U2D: high voltage
VSSL, VSS, VGL, D2U: low voltage
Δ V: voltage of
C1, C2, C3: capacitor with a capacitor element
TM1, TP 1: time of input
TM2, TP 2: enabling time
TM 3: pull down time
TP 3: first pull-down time
TP 4: second pull-down time
TP 5: time of settling
G1[ N-1 ]: first signal of upper stage
G1[ N +1 ]: next stage first signal
G1[ N ]: first signal
G2[ N ]: second signal
G2[ N +1 ]: third signal
Q1[ N ]: node point
Q2[ N ]: first node
A [ N ]: second node
P [ N ]: third node
K [ N ]: fourth node
S [ N ]: output signal
Detailed Description
As used herein, the terms "comprising," having, "and the like are open-ended terms that mean" including, but not limited to. Further, as used herein, "and/or" includes any and all combinations of one or more of the associated listed items.
When an element is referred to as being "connected" or "coupled," it can be referred to as being "electrically connected" or "electrically coupled. "coupled" or "coupled" may also be used to indicate a coordinated operation or interaction between two or more elements. Moreover, although terms such as "first," "second," … …, etc., may be used herein to describe various elements, these terms are used merely to distinguish one element or operation from another element or operation described in similar technical terms. Unless the context clearly dictates otherwise, the terms do not specifically refer or imply an order or sequence nor are they intended to limit the disclosure.
Referring to fig. 1, fig. 1 is a schematic diagram of a display panel according to an embodiment of the disclosure. As shown in fig. 1, the display panel 100 includes a timing control circuit 110, a gate driver 120, a source driver 130, and an image display area 140. The image display area 140 is formed by alternately disposing a plurality of scan lines GL 1-GLN and a plurality of data lines SL 1-SLN, and includes a plurality of display pixels 142, where the number N is taken as an example, and the number of N may be adjusted according to the panel size of the actual application. The timing control circuit 110 is coupled to the gate driver 120 and the source driver 130, and sends a timing control signal through the signal line TC1 and the signal line TC2 to control the timing of the circuit operations of the gate driver 120 and the source driver 130. The gate driver 120 outputs gate driving signals to the image display area 140 to the corresponding display pixels 142 through the M scan lines GL 1-GLM. The source driver 130 outputs source driving signals to the image display area 140 to the corresponding display pixels 142 through the K data lines SL1 to SLK. In one embodiment, the display panel 100 is a screen with a resolution of 1920 × 1080, M is 1080, and K is 1920.
Referring to fig. 2, fig. 2 shows a block diagram of a gate driver according to an embodiment of the disclosure. The gate driver 120 includes a shift register circuit 122, a shift register circuit 124, and a pulse generating circuit 126. As shown in FIG. 2, the shift register circuit 122 and the shift register circuit 124 are used for generating a first signal G1[ N ], a second signal G2[ N ] and a third signal G2[ N +1] to the pulse generating circuit 126, and the pulse generating circuit 126 receives the first signal G1[ N ], the second signal G2[ N ] and the third signal G2[ N +1] and generates an output signal S [ N ]. It should be noted that although the block diagram of the gate driver 120 in fig. 2 only shows one set of circuits, the practical application is not limited to one, and the gate driver 120 of the present disclosure is represented by the nth shift register circuit 122, the shift register circuit 124 and the pulse generating circuit 126 by using the numbers G1[ N ], G2[ N ] and S [ N ]. The shift register circuit G2[ N +1] is used as the next stage shift register circuit of the nth shift register circuit 122, and a plurality of shift register circuits 122, 124 and pulse generating circuits 126 may be applied to implement the present disclosure, the number of which may be adjusted according to the actual application, N is a number greater than or equal to 1 and less than or equal to M, and is a positive integer, in the foregoing embodiment, N is any one of values 1 to 1080. The circuit configurations of the shift register circuit 122, the shift register circuit 124 and the pulse generating circuit 126 are described in detail below.
Referring to fig. 3, fig. 3 is a circuit diagram of a shift register according to an embodiment of the disclosure. The shift register circuit 122 includes transistors TS1 to TS7, a high voltage U2D, a low voltage D2U, a previous stage first signal G1[ N-1], a next stage first signal G1[ N +1], a node Q1[ N ], a first clock signal XCK, a second clock signal CK, a capacitor C1, a capacitor C2, a low voltage VSS, and a first signal G1[ N ]. The transistors TS 1-TS 7 each include a first terminal, a second terminal, and a control terminal, the first terminal of the transistor TS1 is configured to receive the high voltage U2D, the second terminal of the transistor TS1 is coupled to the second terminal of the transistor TS2 and the node Q1[ N ], and the control terminal of the transistor TS1 is configured to receive the previous-stage first signal G1[ N-1] and conduct the high voltage U2D to the node Q1[ N ] according to the previous-stage first signal G1[ N-1 ]. The first terminal of the transistor TS2 is for receiving the low voltage D2U, the second terminal of the transistor TS2 is coupled to the second terminal of the transistor TS1 and the node Q1[ N ], and the control terminal of the transistor TS2 is for receiving the next stage first signal G1[ N +1], and turning on the low voltage D2U to the node Q1[ N ] according to the next stage first signal G1[ N +1 ]. The transistor TS3 has a first terminal for receiving the clock signal CK, a second terminal coupled to the output terminal of the transistor TS3, a control terminal coupled to the capacitor C2 and the node Q1[ N ], and a control terminal of the transistor TS3 for receiving the voltage at the node Q1[ N ] and turning on the clock signal CK to the output terminal according to the voltage at the node Q1[ N ]. The transistor TS4 has a first terminal coupled to the output terminal, a second terminal of the transistor TS4 receiving the low voltage VSS, and a control terminal of the transistor TS4 receiving the clock signal XCK and conducting the low voltage VSS to the output terminal according to the clock signal XCK. The first terminal of the transistor TS5 is coupled to the capacitor C1, the control terminal of the transistor TS6, and the control terminal of the transistor TS7, the second terminal of the transistor TS5 receives the low voltage VSS, and the control terminal of the transistor TS5 is configured to receive the voltage at the node Q1[ N ], and conduct the low voltage VSS to the capacitor C1, the control terminal of the transistor TS6, and the control terminal of the transistor TS7 according to the voltage at the node Q1[ N ]. The first terminal of the transistor TS6 is coupled to the node Q1[ N ], the second terminal of the transistor TS6 receives the low voltage VSS, and the control terminal of the transistor TS6 is coupled to the capacitor C1 and the first terminal of the transistor TS 5. A first terminal of the transistor TS7 is coupled to the capacitor C2, the output terminal, and a first terminal of the transistor TS4, a second terminal of the transistor TS7 receives the low voltage VSS, and a control terminal of the transistor TS7 is coupled to the capacitor C1, the first terminal of the transistor TS5, and the control terminal of the transistor TS 6. The operation of the shift register circuit 122 at each time will be described in detail below.
Referring to fig. 3 and fig. 4, fig. 4 is a timing diagram of signals corresponding to the shift register circuit of fig. 3. The shift register circuit 122 operates in the input time TM1, the enable time TM2, and the pull-down time TM3 intervals as shown in fig. 4. In this embodiment, VDD and VGH are shown as high voltages and VSS and VGL are shown as low voltages, e.g., VGH may be 25 volts, VDD may be 15 volts, and VSS and VGL may be-10 volts. When the shift register circuit 122 inputs the time TM1, the clock signal CK is a low voltage VSS, the clock signal XCK is a high voltage VDD, and the previous stage first signal G1[ N-1] is a high voltage VDD. The transistor TS1 is turned on to turn on the high voltage U2D to the node Q1[ N ] to increase the voltage of the node Q1[ N ], the transistor TS3 is turned on due to the voltage increase of the node Q1[ N ] to turn on the voltage of the clock signal CK to the output terminal, and at this time, the clock signal CK is the low voltage VSS and the clock signal XCK is the high voltage VDD, so the first signal G1[ N ] is the low voltage VSS. The rising voltage at node Q1[ N ] turns on transistor TS5, turns on low voltage VSS to the control terminals of transistor TS6 and transistor TS7, turns off transistor TS6 and transistor TS7, and maintains the voltage at node Q1[ N ].
When the shift register circuit 122 is enabled for the enabled time TM2, the clock signal CK is at the high voltage VDD, the clock signal XCK is at the low voltage VSS, and the previous stage first signal G1[ N-1] is at the low voltage VSS. At this time, the first signal G1[ N ] outputs a high voltage VGH close to the high voltage VDD because the clock signal CK is the high voltage VDD, the clock signal XCK is the low voltage VSS so that the transistor TS4 is turned off to enable the first signal G1[ N ] to maintain the high voltage, the voltage of the node Q1[ N ] is pulled up to the high voltage VDD + Δ V because of the capacitor C2, the high voltage of the node Q1[ N ] enables the transistor TS5 to be kept on and the transistor TS6 and the transistor TS7 to be kept off, and the first signal G1[ N ] can be maintained at the high voltage VGH because the transistors TS4, TS6 and TS7 are turned off.
When the shift register circuit 122 is at the pull-down time TM3, the clock signal CK is at the low voltage VSS, the clock signal XCK is at the high voltage VDD, and the next stage first signal G1[ N +1] is at the high voltage VDD. The transistor TS2 is turned on to turn on the low voltage D2U to the node Q1[ N ], so that the voltage of the node Q1[ N ] is reduced, the transistor TS3 and the transistor TS5 are turned off because the voltage of the node Q1[ N ] is reduced, the clock signal XCK is the high voltage VDD to turn on the transistor TS4, the low voltage VSS is turned on to the output end, and the first signal G1[ N ] is the low voltage VGL.
The effect of sequentially outputting a plurality of pulses can be achieved by connecting a plurality of shift register circuits 122 in series, and the circuit structures and operation modes of the shift register circuit 124 and the shift register circuit 122 are the same, which is not described herein again. The pulse signal generated by the shift register circuit 122 is denoted as the first signal G1[ N ], the pulse signal generated by the shift register circuit 124 is denoted as the second signal G2[ N ], the next-stage second signal is denoted as the third signal G2[ N +1], and the signals are transmitted to the pulse generating circuit 126, as shown in FIG. 2.
Referring to fig. 5, fig. 5 shows a circuit diagram of a pulse generation circuit according to an embodiment of the disclosure. The pulse generating circuit 126 includes an input circuit 126a, a voltage stabilizing circuit 126b, a voltage stabilizing control circuit 126c, a pull-up circuit 126d, and a pull-down circuit 126 e. The input circuit 126a receives a first voltage and is coupled to the first node Q2[ N ], and outputs the first voltage to the first node Q2[ N ] in response to a first signal G1[ N ]. In one embodiment, the first voltage is VDDH, such as 25 volts, and the subsequent first voltage is VDDH.
The regulator 126b receives the high voltage VDDH and a second voltage and is coupled to the first node Q2[ N ], the regulator 126b being responsive to the high voltage VDDH and storing the high voltage VDDH at a second node A [ N ] of the regulator 126b, the regulator stabilizing the voltage at the first node Q2[ N ] according to the voltage at the second node A [ N ]. In one embodiment, the second voltage is a low voltage VSSL, such as-13 volts, and the subsequent second voltage is illustrated by the low voltage VSSL as an example.
The voltage regulation control circuit 126c receives the low voltage VSSL and the second signal G2[ N ], the voltage regulation control circuit 126c adjusts the voltage of the third node P [ N ] of the voltage regulation control circuit 126c in response to the voltage of the first node Q2[ N ], the first clock signal XCK and the second clock signal CK, and the voltage regulation control circuit 126c controls the voltage of the second node a [ N ] according to the voltage of the third node P [ N ].
In one embodiment, the voltage regulation control circuit 126c is further configured to receive a fourth voltage, which may be a low voltage VSS, such as-10 volts, and the following fourth voltage is exemplified by the low voltage VSS. The voltage regulation control circuit 126c adjusts the voltage of the fourth node K [ N ] of the voltage regulation control circuit 126c in response to the first signal G1[ N ], the second signal G2[ N ], or the third signal G2[ N +1 ].
The pull-up circuit 126d receives a third voltage and is coupled to the first node Q2[ N ] and the output terminal, wherein the pull-up circuit 126d outputs the third voltage to the output terminal in response to the voltage at the first node Q2[ N ]. In one embodiment, the third voltage is the high voltage VDD, such as 15 volts, and the following third voltage is exemplified by the high voltage VDD.
The pull-down circuit 126e receives the high voltage VDD, the voltage of the third node P [ N ] and the voltage of the fourth node K [ N ] and is coupled to the output terminal, and the pull-down circuit 126e outputs the high voltage VDD to the output terminal in response to the voltage of the third node P [ N ] or the fourth node K [ N ].
The structure and operation of each circuit is described below. The input circuit 126a includes a transistor T1. The transistor T1 includes a first terminal, a second terminal and a control terminal, the first terminal of the transistor T1 receives the high voltage VDDH, the second terminal of the transistor T1 is coupled to the first node Q2[ N ], the control terminal of the transistor T1 receives the first signal G1[ N ], and the transistor T1 is selectively turned on according to the first signal G1[ N ].
The stabilizing circuit 126b includes a transistor T2, a transistor T3, and a transistor T4. The transistor T2 includes a first terminal receiving the high voltage VDDH, a second terminal receiving the high voltage VDDH, and a control terminal, wherein the first terminal of the transistor T2 is coupled to the second node a [ N ], the second terminal of the transistor T2 is coupled to the first node Q2[ N ] and the control terminal of the transistor T2 is coupled to the second terminal of the transistor T1. The transistor T3 includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the transistor T3 receives the low voltage VSSL, the second terminal of the transistor T3 is coupled to the second node A [ N ], and the control terminal of the transistor T3 receives the voltage of the third node P [ N ] and is selectively turned on according to the voltage of the third node P [ N ]. The transistor T4 includes a first terminal, a second terminal and a control terminal, the first terminal of the transistor T4 is coupled to the second node A [ N ], the second terminal of the transistor T4 is coupled to the first node Q2[ N ] and the second terminal of the transistor T1, and the control terminal of the transistor T4 receives the voltage of the third node P [ N ] and is selectively turned on according to the voltage of the third node P [ N ].
The voltage regulation control circuit 126c includes a transistor T7 and transistors T9 to T13. The transistor T7 and the transistors T9-T13 each include a first terminal, a second terminal, and a control terminal. The first terminal of the transistor T7 receives the high voltage VDD, the second terminal of the transistor T7 is coupled to the fourth node K [ N ], and the control terminal of the transistor T7 receives the third signal G2[ N +1] and is selectively turned on according to the third signal G2[ N +1 ]. The first terminal of the transistor T9 is coupled to the third node P [ N ], the second terminal of the transistor T9 is coupled to the fourth node K [ N ], and the control terminal of the transistor T9 receives the second signal G2[ N ] and is selectively turned on according to the second signal G2[ N ]. The first terminal of the transistor T10 receives the low voltage VSSL, the second terminal of the transistor T10 is coupled to the fourth node K [ N ], and the control terminal of the transistor T10 receives the voltage of the first node Q2[ N ] and is selectively turned on according to the voltage of the first node Q2[ N ]. The first terminal of the transistor T11 receives the second signal G2[ N ], the second terminal of the transistor T11 is coupled to the third node P [ N ], and the control terminal of the transistor T11 receives the first clock signal XCK and is selectively turned on according to the first clock signal XCK. The second terminal of the transistor T12 is coupled to the third node P [ N ], and the first terminal and the control terminal of the transistor T12 receive the second clock signal CK and are selectively turned on according to the second clock signal CK.
The pull-up circuit 126d includes a transistor T5 and a capacitor C3. The transistor T5 includes a first terminal receiving the high voltage VDD, a second terminal coupled to the output terminal of the transistor T5, and a control terminal coupled to the output terminal of the transistor T5, wherein the control terminal of the transistor T5 receives the voltage of the first node Q2[ N ] and is selectively turned on according to the voltage Q2[ N ] of the first node. The capacitor C3 includes a first terminal coupled to the first node Q2[ N ] and a second terminal coupled to the capacitor C3, the second terminal of the capacitor C3 receiving the high voltage VDD.
The pull-down circuit 126e includes a transistor T6 and a transistor T8. The transistor T6 includes a first terminal coupled to the output terminal of the transistor T6, a second terminal of the transistor T6 receiving the low voltage VSS, and a control terminal of the transistor T6 receiving the voltage at the fourth node K [ N ] and selectively turning on according to the voltage at the fourth node K [ N ].
Referring to fig. 6, fig. 6 shows a timing diagram of signals corresponding to the pulse generating circuit of fig. 5. In this embodiment, the pulse generating circuit 126 operates in an operation mode including an input time TP1, an enable time TP2, a first pull-down time TP3, a second pull-down time TP4, and a stable time TP5, and fig. 7 to 11 describe the operation manner of the pulse generating circuit 126 at each time in the operation mode.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating an operation of a pulse generating circuit in an input time interval according to an embodiment of the disclosure. At the input time TP1, a first signal G1[ N [ ]]And the first clock signal XCK is high voltage VGH, the second signal G2[ N [ ]]Third signal G2[ N +1]]And the second clock signal CK is a low voltage VGL. The transistor T1 in the input circuit 126a is driven by the first signal G1[ N ]]And is turned on, so that the input circuit 126a outputs the high voltage VDDH to the first node Q2[ N [ ]]First, aNode Q2[ N ]]Becomes a high Voltage VH, which is a Threshold Voltage (V) of the high Voltage VDDH-transistor T1TH). First node Q2[ N ]]When the voltage becomes the high voltage VH, the voltage body T2 in the voltage stabilizing circuit 126b and the transistor T5 in the pull-up circuit 126d are turned on. The transistor T5 is turned on to output the high voltage VDD to the output terminal, so that the signal S [ N ] is output]Is a high voltage VDD. The transistor T2 is turned on to output the high voltage VDDH to the second node A [ N ]]. The first clock signal XCK is a high voltage VGH and a first node Q2[ N [ ]]The high voltage VH turns on the transistors T10 and T11 in the regulator control circuit 126c, and outputs the low voltage VSSL to the third node P [ N ]]Let the third node P [ N ]]Is a low voltage VSSL, a first signal G1N]The transistor T13 is turned on for the high voltage VGH, and the low voltage VSS is output to the fourth node K [ N ]]Make the fourth node K [ N ]]Is a low voltage VSS.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating an operation of a pulse generating circuit in an enabling time interval according to an embodiment of the disclosure. The operation method of the pulse generating circuit 126 capable of maintaining the output signal S [ N ] at the high voltage level during the enabling time TP2 is described in detail below. Unlike the input time TP1 of FIG. 7, when the first signal G1[ N ] has changed from the high voltage to the low voltage VGL, the input circuit 126a ends outputting the high voltage VDDH to the first node Q2[ N ]. Since VDDH is outputted to the second node A [ N ], the voltage of the second node A [ N ] is set to VDDH, the high voltage VH of the first node Q2[ N ] turns on the transistor T10 to lower the voltage of the third node P [ N ] to VGL, and the low voltage VGL of the third node P [ N ] turns off the transistors T3 and T4, thereby greatly reducing the leakage of the first node Q2[ N ] through the paths of the transistor T3 and the transistor T4. Since the transistor may have a Leakage Current (Leakage Current) when it is turned off, even if the transistor is turned off, the voltage may not be maintained due to the Leakage Current of the transistor, and therefore, in addition to controlling the transistor to be turned off, the magnitude of the Leakage Current must be further limited to stabilize the voltage of the first node Q2[ N ].
The leakage current of the transistor and the voltage difference V between the control end and the second end of the transistorGS(gate-to-sources) is proportional. When enabledAt time TP2, the transistor T2 is turned on to output the high voltage of VDDH to the second node A [ N ]]The second terminals of the transistors T3 and T4 are turned to high voltage (high voltage close to VDDH), and the third node P [ N ] is turned to high voltage]The voltage VGL is low, so the control terminals of the transistor T3 and the transistor T4 are at the low voltage VGL. Using V of the transistor T3 and the transistor T4GSIs controlled to be at a low voltage (the voltage difference between VGL and VDDH), thereby limiting the leakage current of the transistor T3 and the transistor T4 and greatly reducing the first node Q2[ N ]]The voltage of the first transistor T5 can be stabilized at a high voltage due to the leakage current of the transistors T3 and T4, and the first transistor T5 is turned on continuously to output the signal S [ N ]]Can be maintained at a high voltage. In addition, a second node A [ N ]]Is increased to near the first node Q2N]Can also improve the first node Q2N]And (3) leakage of electricity.
Referring to fig. 9, fig. 9 is a schematic diagram illustrating an operation of a pulse generating circuit in a first pull-down time interval according to an embodiment of the disclosure. At the first pull-down time TP3, the second signal G2[ N ] becomes the high voltage VGH, and the transistor T5 is turned off to turn the output terminal to end outputting the high voltage and turn it to the low voltage. Specifically, the second signal G2[ N ] and the first clock signal XCK become the high voltage VGH, turning on the transistor T11 to change the third node P [ N ] to the high voltage VH. P [ N ] goes high turning on transistors T3 and T4 to lower the voltage at the first node Q2[ N ] to the low voltage VSSL. The voltage drop at the first node Q2[ N ] turns off the transistor T5, and the transistor T5 stops outputting the high voltage VDD to the output terminal. The high voltage of the second signal G2[ N ] turns on the transistor T9, the high voltage of the third node P [ N ] is output to the transistor T6 and the transistor T8, the transistor T6 and the transistor T8 are turned on, the low voltage VSS is output to the output terminal, and the output signal S [ N ] becomes a low voltage. In addition, in the operation mode of the pulse generating circuit 126, the transistor T6 is turned on only during the first pull-down time TP3, which can slow down the aging speed of the transistor T6.
Referring to fig. 10, fig. 10 is a schematic diagram illustrating an operation of the pulse generating circuit in the second pull-down time interval according to an embodiment of the disclosure. During the second pull-down time TP4, the second signal G2[ N ] becomes the low voltage VGL, and the third signal G2[ N +1] becomes the high voltage VGH. The voltage at the fourth node K [ N ] becomes the low voltage VSS because the transistor T7 is turned on, turning off the transistor T6. The second clock signal CK becomes the high voltage VGH to turn on the transistor T12, and the high voltage VGH is output to the transistor T8 to be turned on. The transistor T8 is turned on to output the low voltage VSS to the output terminal, so that the output signal S [ N ] is a low voltage. The third node P [ N ] is the high voltage VH, which keeps the transistor T3 and the transistor T4 turned on, and keeps outputting the low voltage of the low voltage VSSL to the first node Q2[ N ].
Referring to fig. 11, fig. 11 is a schematic diagram illustrating an operation of a pulse generating circuit in a stable time interval according to an embodiment of the disclosure. During the settling time TP5, the first clock signal XCK and the second clock signal CK periodically change to the high voltage VGH, the third node P [ N ] is periodically raised to the high voltage VH, the first node Q2[ N ] is maintained at the low voltage VSSL, and the output terminal is maintained at the low voltage VSS. In addition, the periodic turning on of the transistors T3, T4, and T8 slows down the aging of the devices of the transistors T3, T4, and T8.
In summary, the pulse generating circuit has different operation modes according to different input signals, and maintains the node voltage by using the cascode structure of the transistor in the voltage stabilizing circuit within the enabling time, so that the output signal of the pulse generating circuit can maintain a high potential for a long time, and the operation time of the subsequent circuit is prolonged. In addition, the clock pulse generating circuit utilizes the clock signal to periodically turn on the transistor in the non-enabling time, so that the transistor element is not rapidly worn due to long-time continuous conduction, and the service life of the transistor is further prolonged.
It should be understood by those skilled in the art that, in various embodiments, each circuit unit may be implemented by various types of digital or analog circuits, and may also be implemented by different integrated circuit chips. The various components may also be integrated into a single integrated circuit chip. The foregoing is merely exemplary, and the disclosure is not limited thereto. Electronic components such as resistors, capacitors, diodes, transistor switches, etc. may be implemented by any suitable means. For example, the transistors T1-T12 may be implemented by Metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs), Bipolar Junction Transistors (BJTs) or other various types of transistors as required.
Although the present disclosure has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be determined by that of the appended claims.

Claims (10)

1. A pulse generating circuit, comprising:
an input circuit, coupled to a first node, for receiving a first voltage, wherein the input circuit outputs the first voltage to the first node in response to a first signal;
a voltage regulator circuit, coupled to the first node, for receiving the first voltage and a second voltage, wherein the voltage regulator circuit is responsive to the first voltage and stores the first voltage to a second node of the voltage regulator circuit, and the voltage regulator circuit stabilizes a voltage of the first node according to a voltage of the second node;
a voltage regulation control circuit for receiving the second voltage and a second signal, wherein the voltage regulation control circuit adjusts a voltage of a third node of the voltage regulation control circuit in response to the voltage of the first node, a first clock signal and a second clock signal, and the voltage regulation control circuit controls the voltage of the second node according to the voltage of the third node; and
and a pull-up circuit for receiving a third voltage and coupled to the first node and an output terminal, wherein the pull-up circuit outputs the third voltage to the output terminal in response to the voltage of the first node.
2. The pulse generating circuit of claim 1, wherein the input circuit comprises:
a transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor receives the first voltage, the second terminal of the transistor is coupled to the first node, and the control terminal of the transistor is configured to receive the first signal, wherein the transistor is selectively turned on according to the first signal.
3. The pulse generating circuit of claim 1, wherein the voltage regulator circuit comprises:
a first transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor receives the first voltage, the second terminal of the first transistor is coupled to the second node, and the control terminal of the first transistor is coupled to the first node and the input circuit;
a second transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor receives the second voltage, the second terminal of the second transistor is coupled to the second node, and the control terminal of the second transistor receives the voltage of the third node and is selectively turned on according to the voltage of the third node; and
a third transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the second node, the second terminal of the third transistor is coupled to the first node and the input circuit, and the control terminal of the third transistor receives a voltage of the third node and is selectively turned on according to the voltage of the third node.
4. The pulse generating circuit according to claim 3, wherein the second transistor and the third transistor are turned on periodically according to the voltage of the third node, and output the second voltage to the first node.
5. The pulse generating circuit of claim 1, wherein the pull-up circuit comprises:
a transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal of the transistor receives the third voltage, the second terminal of the transistor is coupled to the output terminal, and the control terminal of the transistor receives the voltage of the first node and is selectively turned on according to the voltage of the first node; and
a capacitor including a first end and a second end, wherein the first end of the capacitor is coupled to the first node, and the second end of the capacitor receives the third voltage.
6. The pulse generating circuit of claim 1, wherein the regulation control circuit comprises:
a first transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor receives the second signal, the second terminal of the first transistor is coupled to the third node, and the control terminal of the first transistor receives the first clock signal and is selectively turned on according to the first clock signal;
a second transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor receives the second signal, and the control terminal of the second transistor receives the second signal and is selectively turned on according to the second signal;
a third transistor including a first terminal, a second terminal, and a control terminal, wherein the second terminal of the third transistor is coupled to the third node, and the first terminal and the control terminal of the third transistor receive the second clock signal and are selectively turned on according to the second clock signal; and
a fourth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor receives the second voltage, the second terminal of the fourth transistor is coupled to the third node and the second terminal of the third transistor, and the control terminal of the fourth transistor receives the voltage of the first node and is selectively turned on according to the voltage of the first node.
7. The pulse generating circuit of claim 6, wherein the regulation control circuit is further configured to receive a fourth voltage, wherein the regulation control circuit adjusts a voltage of a fourth node of the regulation control circuit in response to the first signal, the second signal, or a third signal;
wherein the voltage stabilization control circuit further comprises:
a fifth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor receives the third voltage, the second terminal of the fifth transistor is coupled to the fourth node, and the control terminal of the fifth transistor receives the third signal and is selectively turned on according to the third signal; and
a sixth transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor receives the third voltage, the second terminal of the sixth transistor is coupled to the fourth node, and the control terminal of the sixth transistor receives the first signal and is selectively turned on according to the first signal.
8. The pulse generating circuit of claim 7, further comprising:
a pull-down circuit coupled to the output terminal for receiving the third voltage, the voltage of the third node, and the voltage of the fourth node, wherein the pull-down circuit outputs the third voltage to the output terminal in response to the voltage of the third node or the fourth node.
9. The pulse generating circuit of claim 8, wherein the pull-down circuit comprises:
a first transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the output terminal, the second terminal of the first transistor receives the fourth voltage, and the control terminal of the first transistor receives the voltage of the fourth node and is selectively turned on according to the voltage of the fourth node; and
a second transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor is coupled to the output terminal, the second terminal of the first transistor receives the fourth voltage, and the control terminal of the second transistor receives the voltage of the third node and is selectively turned on according to the voltage of the third node.
10. The pulse generating circuit as claimed in claim 9, wherein the second transistor is turned on periodically according to the second clock signal to output the fourth voltage to the output terminal.
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