CN110851354A

CN110851354A - Test system and test method

Info

Publication number: CN110851354A
Application number: CN201911016289.5A
Authority: CN
Inventors: 李兴鹤; 糜尧杰; 吴芸; 刘小红
Original assignee: Shanghai Sigriner Step Electric Co Ltd
Current assignee: Shanghai Sigriner Step Electric Co Ltd
Priority date: 2019-10-24
Filing date: 2019-10-24
Publication date: 2020-02-28
Anticipated expiration: 2039-10-24
Also published as: CN110851354B

Abstract

The embodiment of the invention discloses a test system and a test method, wherein the test system comprises: the first central processing module, the first cache and the first interface module are connected with each other; the first interface module is connected with a tested device; the first interface module is used for reading first data to be tested from a first cache, sending the first data to the tested equipment, receiving second data to be tested from the tested equipment, and caching the second data to be tested to the first cache; the first central processing module is configured to determine that the data transmission test of the device under test is successful when the first data to be tested and the second data to be tested meet a preset condition. The technical scheme provided by the embodiment of the invention can improve the board-level test efficiency.

Description

Test system and test method

Technical Field

The embodiment of the invention relates to the field of board level test, in particular to a test system and a test method.

Background

At present, when a tested device requires to test different data to be tested and different test conditions, many test systems, especially board level test systems, need to manually write a test program, a test platform, and the tested device (for example, a tested board card), which seriously affects the test efficiency. In addition, different test programs and test platforms need to be customized and developed for different tested devices, which wastes time and labor and affects reliability, and brings great inconvenience to maintenance.

Disclosure of Invention

The embodiment of the invention aims to provide a test system and a test method, which solve the technical problem of low board-level test efficiency in the prior art.

To solve the above technical problem, an embodiment of the present invention provides a test system, including:

the first central processing module, the first cache and the first interface module are connected with each other; the first interface module is connected with a tested device;

the first interface module is used for reading first data to be tested from a first cache, sending the first data to the tested equipment, receiving second data to be tested from the tested equipment, and caching the second data to be tested to the first cache;

the first central processing module is configured to determine that the data transmission test of the device under test is successful when the first data to be tested and the second data to be tested meet a preset condition.

The embodiment of the invention also provides a test method, which is applied to the test system; the method comprises the following steps:

the first interface module reads first data to be tested from a first cache, sends the first data to be tested to tested equipment, receives second data to be tested from the tested equipment, and caches the second data to be tested to the first cache;

and when the first data to be tested and the second data to be tested meet preset conditions, the first central processing module determines that the data transmission test of the equipment to be tested is successful.

Compared with the prior art, the embodiment of the invention provides a testing system with a novel architecture, avoids manually writing a testing program and a testing platform, can automatically test the tested equipment only by writing preset conditions and data to be tested in the testing system, and has higher testing efficiency. In addition, different test programs do not need to be customized and developed for tested equipment with different test conditions and different test data requirements, and the tested equipment can be tested only by writing the conditions meeting the requirements and the data to be tested in the test system, so that the board-level test efficiency can be greatly improved.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1 is a schematic structural diagram of a test system according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a test platform according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a test platform according to another embodiment of the present invention;

fig. 4 is a schematic structural diagram of a test platform according to another embodiment of the present invention;

fig. 5 is a flowchart illustrating a testing method according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

Example one

Fig. 1 is a schematic structural diagram of a test system according to an embodiment of the present invention. As shown in fig. 1, the test system includes:

Wherein the content of the first and second substances,

the tested device is configured to cache the first data to be tested in a local second cache when receiving the first data to be tested, then determine second data to be tested according to the data cached in the second cache, and send the second data to be tested to the first interface module.

When the first data to be measured comprises first digital quantity data and first analog quantity data, and the second data to be measured comprises second digital quantity data and second analog quantity data, the preset condition comprises one of the following conditions:

the first condition is as follows: the first digital quantity data and the second digital quantity data in the first cache are the same, and the first analog quantity data and the second analog quantity data are the same;

and a second condition: the first digital quantity data and the second digital quantity data in the first cache are opposite and the first analog quantity data and the second analog quantity data are the same;

and (3) carrying out a third condition: the second data to be tested comprises two continuous second digital quantity data and one second analog quantity data, the first digital quantity data in the first cache is the same as the previous second digital quantity data in the second data to be tested but opposite to the next second digital quantity data, and the first analog quantity data is the same as the second analog quantity data;

and a fourth condition: the second data to be tested comprises two continuous second digital quantity data and one second analog quantity data, the first digital quantity data in the first cache is opposite to the previous second digital quantity data in the second data to be tested but is the same as the next second digital quantity data, and the first analog quantity data is the same as the second analog quantity data;

or, when the first data to be tested includes first communication data and the second data to be tested includes second communication data, the preset condition includes at least one of:

and a fifth condition: the first communication data and the second communication data in the first cache are the same;

and a sixth condition: and the check value and/or the coding mode of the first communication data and the second communication data are the same.

When the preset condition is a condition one, the tested device is configured to directly take the digital quantity data cached in the second cache as second digital quantity data, and take the analog quantity data cached in the second cache as second analog quantity data;

when the preset condition is a second condition, the tested device is configured to invert the digital quantity data cached in the second cache to be second digital quantity data, and the analog quantity data cached in the second cache to be second analog quantity data;

when the preset condition is a third condition, the tested device is configured to take the digital quantity data cached in the second cache as previous second digital quantity data, then reverse the digital quantity data cached in the second cache as next second digital quantity data, and take the analog quantity data cached in the second cache as second analog quantity data;

when the preset condition is a fourth condition, the tested device is configured to invert the digital quantity data cached in the second cache to be used as previous second digital quantity data, then use the digital quantity data cached in the second cache as next second digital quantity data, and use the analog quantity data cached in the second cache as second analog quantity data.

The first cache comprises a first read-only memory Buffer ROM Buffer and a first random access memory Buffer RAM Buffer;

the first interface module includes: the first output interface, the first input interface and the first bidirectional interface;

the device under test comprises: a second output interface, a second input interface and a second bidirectional interface;

the first output interface is connected with the second input interface, the input of the first input interface is connected with the second output interface, and the first bidirectional interface is connected with the second bidirectional interface;

the first data to be measured comprises first digital quantity data and first analog quantity data; the second data to be tested comprises second digital quantity data and second analog quantity data;

the first ROM Buffer is used for storing the first data to be tested;

the first output interface is used for reading the first digital quantity data from the first ROM Buffer and sending the first digital quantity data to a second input interface of the tested device;

the first input interface is used for receiving the second digital quantity data from a second output interface of the tested device and caching the second digital quantity data into the first RAM Buffer;

the first bidirectional interface is used for reading the first analog quantity data from the first ROM Buffer and sending the first analog quantity data to the second bidirectional interface; the first RAM Buffer is used for storing the first analog quantity data and the second analog quantity data;

the first central processing module is specifically configured to determine that the data transmission test of the device under test is successful when the first digital quantity data, the second digital quantity data, the first analog quantity data and the second analog quantity data satisfy a preset condition;

wherein the device under test is configured to cache the first digital quantity data into a local second cache upon receiving the first digital quantity data through the second input interface; outputting the digital quantity data and/or the negation cached in the second cache as second digital quantity data through the second output interface; when the first analog quantity data is received through the second bidirectional interface, the first analog quantity data is cached in a local second cache, and the analog quantity data cached in the second cache is taken as second analog quantity data to be sent through the second bidirectional interface.

The first address in the first ROM Buffer is used for caching first digital quantity data, and the second address is used for caching first analog quantity data;

a third address in the first RAM Buffer is used for caching second digital quantity data, and a fourth address is used for caching second analog quantity data;

the first output interface is specifically configured to read the first digital quantity data from the first address in the first ROM Buffer, and send the first digital quantity data to a second input interface of the device under test;

the first input interface is specifically configured to receive the second digital quantity data from the second output interface of the device under test, and cache the second digital quantity data in the third address of the first RAM Buffer;

the first bidirectional interface is used for reading the first analog quantity data from a second address in the first ROM Buffer and sending the first analog quantity data to the second bidirectional interface; the second analog quantity data is received from the second bidirectional interface and is cached in a fourth address of the first RAM Buffer;

the first central processing module is specifically configured to determine that the data transmission test of the device under test is successful when first digital quantity data in a first address in the first ROM Buffer and second digital quantity data in a third address of the first RAM Buffer, and first analog quantity data in a second address in the first ROM Buffer and second analog quantity data in a fourth address of the first RAM Buffer satisfy a preset condition.

Wherein, the second cache is a second RAM Buffer;

a fifth address in the second RAM Buffer is used for storing first digital quantity data received by the second input interface, and a sixth address is used for storing first analog quantity data received by the second bidirectional interface;

the second output interface is used for determining second digital quantity data according to the digital quantity data stored in the fifth address and sending the second digital quantity data to the first input interface;

and the second bidirectional interface is used for determining second analog quantity data according to the analog quantity data stored in the sixth address and sending the second analog quantity data to the first bidirectional interface.

The second cache comprises a second ROM Buffer and a second RAM Buffer;

a seventh address in the second RAM Buffer is used for storing the first digital quantity data received by the second input interface, and an eighth address is used for storing the first analog quantity data received by the second bidirectional interface; mapping the digital quantity data in the seventh address to a ninth address in a second ROM Buffer, and mapping the analog quantity data in the eighth address to a tenth address in the second ROM Buffer;

the second output interface is used for determining second digital quantity data according to the digital quantity data of the ninth address and sending the second digital quantity data to the first input interface;

and the second bidirectional interface is used for determining second analog quantity data according to the analog quantity data of the tenth address and sending the second analog quantity data to the first bidirectional interface.

The first central processing module is further configured to connect a set-top terminal, configure the first preset policy according to a command of the set-top terminal, and write the first to-be-detected data into the first cache.

The technical scheme provided by the embodiment provides a testing system with a novel architecture, and the testing system with the novel architecture can automatically test the tested equipment only by writing preset conditions and data to be tested in the testing system, so that the testing efficiency is high.

In addition, different test programs do not need to be customized and developed for tested equipment with different test conditions and different test data requirements, and the tested equipment can be tested only by writing the conditions meeting the requirements and the data to be tested in the test system, so that the board-level test efficiency can be greatly improved.

Example two

Fig. 2 is a schematic structural diagram of a test platform according to an embodiment of the present invention. As shown in fig. 2, the test platform includes: the device comprises a test system and a tested device;

the test system comprises: the system comprises a first central processing module CPM, a first cache and a first interface module which are connected with each other; the first interface module is connected with a second interface module of the tested device;

the device under test comprises: the second central processing module CPM, the second cache and the second interface module are connected with each other; the second interface module is connected with the first interface module of the tested device.

The first CPM is connected with the upper machine position, receives a command of the upper machine position, configures preset conditions according to the command of the upper machine position, stores the preset conditions in the first cache, and writes the first to-be-detected data into the first cache;

specifically, the first CPM is specifically configured to receive a command of the set-top bit through a first programming port, configure the preset condition, and write the first to-be-detected data into a first cache.

Therefore, the data to be tested and the preset conditions are stored in the first cache, and the tested equipment can be tested for many times only by adjusting the data to be tested or the preset conditions stored in the first cache. Different data to be tested and preset conditions can be stored in the first cache, and in practical application, different tested devices can be tested only by calling the corresponding data to be tested and the preset conditions, so that the application range of the test platform is wide.

When the first data to be measured comprises first digital quantity data and first analog quantity data; when the second data to be measured includes second digital quantity data and second analog quantity data, the preset condition includes one of:

or, when the first data to be measured includes first communication data; when the second data to be tested comprises second communication data, the preset condition comprises at least one of the following conditions:

It should be noted that the data being identical means that the data are identical or the difference between the data is within a preset threshold range.

The check value is obtained by calculating the first communication data and the second communication data respectively by using a check algorithm, and the check algorithm may be any one of the existing check algorithms, such as a parity check algorithm, a cyclic redundancy check algorithm, and the like.

The second CPM is also connected with the set-top bit, receives a command of the set-top bit, and configures the device to be tested according to the command of the set-top bit, so that when the first data to be tested is received through the second interface module, the first data to be tested is cached in a local second cache, then the second data to be tested is determined according to the data cached in the second cache, and the second data to be tested is sent to the first interface module.

Specifically, the second CPM is specifically configured to receive a command of the set-up bit through a second programming port, and configure the device under test.

Specifically, when the preset condition is a condition one, the device under test is configured to directly take the digital quantity data cached in the second cache as second digital quantity data, and take the analog quantity data cached in the second cache as second analog quantity data;

The first interface module is used for reading first data to be tested from the first cache and sending the first data to be tested to the second interface module of the tested device;

the second interface module is used for caching the first data to be tested into a local second cache after receiving the first data to be tested;

the second interface module is further configured to determine second data to be tested according to the data cached in the second cache, and send the second data to be tested to the first interface module;

specifically, when the device under test is configured to invert digital quantity data cached in the second cache as second digital quantity data and use analog quantity data cached in the second cache as second analog quantity data, the second interface module is configured to invert digital quantity data cached in the second cache as second digital quantity data, use analog quantity data cached in the second cache as second analog quantity data, and then send the second digital quantity data and the second analog quantity data to the first interface module;

specifically, the device under test is configured to invert digital quantity data cached in the second cache as second digital quantity data, and when analog quantity data cached in the second cache is taken as second analog quantity data, the second interface module is configured to invert digital quantity data cached in the second cache as second digital quantity data, take analog quantity data cached in the second cache as second analog quantity data, and then send the second digital quantity data and the second analog quantity data to the first interface module;

specifically, when the device under test is configured to use the digital quantity data cached in the second cache as previous second digital quantity data, then reverse the digital quantity data cached in the second cache as next second digital quantity data, and use the analog quantity data cached in the second cache as second analog quantity data, the second interface module is configured to use the digital quantity data cached in the second cache as previous second digital quantity data, then reverse the digital quantity data cached in the second cache as next second digital quantity data, use the analog quantity data cached in the second cache as second analog quantity data, and then send the previous second digital quantity data, the next second digital quantity data, and the second analog quantity data to the first interface module;

specifically, when the device under test is configured to invert digital quantity data cached in the second cache as previous second digital quantity data, use the digital quantity data cached in the second cache as next second digital quantity data, and use analog quantity data cached in the second cache as second analog quantity data, the second interface module is configured to invert the digital quantity data cached in the second cache as previous second digital quantity data, use the digital quantity data cached in the second cache as next second digital quantity data, use the analog quantity data cached in the second cache as second analog quantity data, and then send the previous second digital quantity data, the next second digital quantity data, and the second analog quantity data to the first interface module.

The negation means that when 0 represents a low level and 1 represents a high level, if the digital quantity data buffered in the second buffer is 0, the low level is represented, and negation, that is, the second digital quantity data outputs a high level, and if the digital quantity data buffered in the second buffer is 1, the high level is represented, and negation, that is, the second digital quantity data outputs a low level.

The first interface module is further configured to receive second data to be tested from a second interface module of the device under test, and cache the second data to be tested in the first cache;

the first central processing module is configured to determine whether the first to-be-tested data and the second to-be-tested data in the first cache are consistent according to a first preset policy, and when the first to-be-tested data and the second to-be-tested data are consistent, determine that the data transmission test of the to-be-tested device is successful.

Specifically, the first central processing module is specifically configured to determine that the data transmission test of the device under test is successful when the first data to be tested and the second data to be tested meet a preset condition.

According to the technical scheme provided by the embodiment, the test system is connected with the tested equipment through the interface, then the tested equipment can be automatically tested by writing the preset conditions and the data to be tested in the test system, and the test efficiency is high.

In addition, different test programs do not need to be customized and developed for tested equipment with different test conditions and different test data requirements, the tested equipment can be tested only by writing the conditions meeting the requirements and the data to be tested in the test system, and the board-level test efficiency can be greatly improved.

EXAMPLE III

Fig. 3 is a schematic structural diagram of a test platform according to another embodiment of the present invention.

As shown in fig. 3, in this embodiment, on the basis of the second embodiment, the first cache includes a first ROM Buffer and a first RAM Buffer;

the second interface module includes: a second output interface, a second input interface and a second bidirectional interface;

the first data to be measured comprises first digital quantity data and first analog quantity data; the second data to be tested comprises second digital quantity data and second analog quantity data; or the first data to be measured comprises first communication data; the second data to be tested comprises second communication data;

the first ROM Buffer is used for storing the first data to be tested; the system is also used for storing preset conditions;

the first central processing module is specifically configured to determine that the data transmission test of the device under test is successful when the first data to be tested and the second data to be tested meet a preset condition;

According to the technical scheme provided by the embodiment, besides the technical effects, the test system adopts a double-cache structure, so that the data reading and writing speed can be increased, and the test efficiency is further improved.

Example four

In this embodiment, on the basis of the second and third embodiments, a first address in the first ROM Buffer is used to cache first digital quantity data, and a second address is used to cache first analog quantity data;

EXAMPLE five

In this embodiment, on the basis of any one of the above embodiments, the second cache is a second RAM Buffer;

The technical scheme provided by the embodiment can realize the technical effects, the tested device can simultaneously read and write data by using RAMbuffer cache data, and compared with double caches, the device has a simple structure and low cost.

EXAMPLE six

In this embodiment, on the basis of any one of the above embodiments, the second cache includes a second ROM Buffer and a second RAM Buffer;

According to the technical scheme provided by the embodiment, besides the technical effects, the tested device can also accelerate the data reading and writing speed by using double caches, and the testing efficiency is further improved.

EXAMPLE seven

On the basis of the above embodiment, the specific manner of configuring the first address of the first ROM Buffer and the second address of the first RAM Buffer is as follows:

wherein, configuring an address mapping table for the first ROM Buffer and the first RAM Buffer includes:

the first ROM BUFFEER is configured to:

the first address is address 0x 01:

address 0x 01: the signals are hidden to Do 1-Do 8 states, 0 is low level, and 1 is high level; or 0 is high level and 1 is low level;

the second address is addresses 0x 18-0 x 1F:

addresses 0x 18-0 x 1F: data content sent by a frame corresponding to the first bidirectional interface;

the first RAM BUFFEER is configured to:

the third address is address 0x 01:

address 0x 01: saving Di 1-Di 8 states, wherein 0 is low level and 1 is high level; or 0 is high level and 1 is low level;

the fourth address is addresses 0x 18-0 x1F

Addresses 0x 18-0 x 1F: data content received by a frame corresponding to the first bidirectional interface;

wherein, configuring an address mapping table for the second RAM Buffer includes:

the fifth address is address 0x 01:

address 0x01(1 byte): the Di 1-Di 8 states are saved and simultaneously hidden to the Do 1-Do 8 states, 0 is low level, and 1 is high level; or 0 is high level and 1 is low level;

the sixth address is addresses 0x 18-0 x 1F:

addresses 0x 18-0 x1F (8 bytes): receiving data content corresponding to a frame of the second bidirectional interface; and simultaneously transmitting data content corresponding to one frame of the second bidirectional interface.

According to the technical scheme provided by the embodiment, besides the technical effects, data reading and writing are performed in an address mapping table mode, the data transmission speed is increased, and the test efficiency is further improved.

Example eight

Fig. 4 is a schematic structural diagram of a testing platform according to another embodiment of the present invention, as shown in fig. 4,

in this embodiment, the second cache includes a second ROM Buffer and a second RAM Buffer;

on the basis of the above embodiment, the internal structures of the test system and the device under test are consistent, and both include:

1. central Processing Module (CPM): configuring BUFFER data, judging whether the test is correct or passed, and receiving a user instruction of a set-up position through a programming port;

2. ROM Buffer (Read-Only Memory Buffer): the read-only buffer transmits the internal data to the output interface Yo or the bidirectional interface Zb;

3. RAM Buffer (Random Access Memory Buffer): the writable buffer, the internal data of which is written by the input interface Xi or the bidirectional interface Zb;

wherein, the mapping table of the external address of ROM Buffer and RAM Buffer: different range addresses map different peripherals.

In this embodiment, the upper computer may be used to configure the address mapping tables of the ROM Buffer and the RAM Buffer through the CPM, and the configuration may be disconnected after the configuration. In addition, the bidirectional interface Zb in this embodiment may be a CAN (Controller Area Network) communication interface.

The CPM can receive a user configuration instruction sent by the upper computer through a programming interface, update a ROMBUFFER \ RAM BUFFER address mapping table and the content of a ROM BUFFER, simultaneously read the content of the ROM BUFFER \ RAMBUFFER, and judge whether the test is correct or passed according to a preset peripheral mapping table rule. The judgment mechanism can also be completed by the upper computer, that is, the upper computer judges whether the test data in the first ROM buffer and the first RAM buffer meets the preset condition. An upper computer: the method is a user programming tool, and can configure an address mapping table and write ROM BUFFER data through an upper computer, read the BUFFER data and the like, or perform scanning self-test on a system. The upper computer can be matched in a standard way or an optional way, and can be connected or disconnected when in use.

For example, in this embodiment, the configuration of the ROM Buffer and the RAM Buffer is as follows:

the test system comprises:

the first ROM BUFFEER is configured as follows:

address 0x01(1 byte): a state of Do1 to Do8 (0 is low, 1 is high, or 1 is low, 0 is high) corresponding to the first address;

addresses 0x 18-0 x1F (8 bytes): data content sent by a frame corresponding to the first bidirectional interface; the first RAM BUFFEER corresponding to the second address is configured as follows:

address 0x01(1 byte): di 1-Di 8 states (0 is low, 1 is high, or 1 is low, 0 is high) are saved, which correspond to the third address

Addresses 0x 18-0 x1F (8 bytes): receiving data content corresponding to a frame of the first bidirectional interface; which corresponds to the fourth address;

the test system may also include other interfaces, which are not specifically configured because they are not used in this embodiment.

The tested device:

the second ROM BUFFEER configuration is as follows:

address 0x01(1 byte): the Do 1-Do 8 states are saved and simultaneously hidden to the Do 1-Do 8 states (0 is low level, 1 is high level or 1 is low level, 0 is high level), which correspond to the ninth address;

addresses 0x 18-0 x1F (8 bytes): mapping to addresses 0x 18-0 x1F of a second RAM BUFFEER, and corresponding to data content sent by a frame of a second bidirectional interface; which corresponds to the tenth address;

the second RAM BUFFEER is configured as follows:

address 0x01(1 byte): the Di1 to Di8 states (0 is low, 1 is high, or 1 is low, 0 is high) are saved, which correspond to the seventh address;

addresses 0x 18-0 x1F (8 bytes): data content received corresponding to a frame of the second bidirectional interface; which corresponds to the eighth address.

According to the technical scheme provided by the embodiment, the test system and the tested equipment both adopt a double-cache architecture, so that the data reading and writing speed can be accelerated, and the test efficiency is further improved.

Example nine

In this embodiment, the interfaces of the test system and the device under test can be abstracted into three types: an input interface Xi (such as digital quantity input and analog quantity input), an output interface Yo (such as digital quantity output and analog quantity output), and a bidirectional interface Zb (communication interface and the like).

The connection relationship between the test system and the tested equipment is as follows: the input interface is connected with the output interface of the other side, the output interface is connected with the input interface of the other side, and the two-way interfaces are interconnected.

In this embodiment, the input interface Xi, the output interface Yo, and the bidirectional interface Zb may be configured by the upper computer, and may be disconnected after configuration. In addition, the bidirectional interface Zb in this embodiment may be a CAN (controller area Network) communication interface.

On the basis of the above embodiment, the first output interface Yo reads out data from the address 0x01 of the first ROM BUFFER in real time and outputs the data in real time;

the first input interface Xi also receives data in real time, and writes the received data into the address 0x01 of the first RAM BUFFER in real time;

the first bidirectional interface Zb reads out data from addresses 0x 18-0 x1F of the first ROM BUFFER in real time and outputs the data in real time; meanwhile, data are received in real time, and the received data are written into addresses 0x 18-0 x1F of a first RAM BUFFER in real time;

the second CPM is further configured to receive a command of the set-up bit through the second programming port to configure a second output interface Yo, a second input interface Xi, and a second bidirectional interface Zb;

the second input interface Xi receives data in real time, and writes the received data into an address 0x01 of a second RAM BUFFER in real time;

the second output interface Yo reads out data from the address 0x01 of the second ROM BUFFER in real time and outputs the data in real time;

the second bidirectional interface Zb reads out data from addresses 0x 18-0 x1F of a second ROM BUFFER in real time and outputs the data in real time; meanwhile, data are received in real time, and the received data are written into addresses 0x 18-0 x1F of the second RAM BUFFER in real time.

Specifically, the test procedure is as follows:

step 1: do of the test system reads the content from 0x01 in the first ROM BUFFEER, and refreshes the states of Do 1-Do 8 for output;

step 2: di 1-Di 8 of the tested device reads the state and writes the state into the address 0x01 in the second RAM BUFFEER of the tested device;

step 3: the Do of the tested device reads the content from 0x01 in the second RAM BUFFEER, refreshes the states of the Do 1-the Do8 and outputs the content;

step 4: di 1-Di 8 reading states of the test system and writing the states into 0x01 in a first RAM BUFFEER of the test system;

step 5: the CAN communication interface of the test system reads contents from 0x 18-0 x1F in the first ROM BUFFEER, sends the contents through the CAN communication interface, and writes one frame of data received by the CAN communication interface into 0x 18-0 x1F in the first RAM BUFFEER;

step 6: one frame of data received by the CAN communication interface of the tested device is written into 0x 18-0 x1F in the second RAM BUFFEER, and the content is read from 0x 18-0 x1F in the second RAM BUFFEER and is sent through the CAN communication interface;

step 7: after a preset time, for example 20ms, the first CPM of the test system reads and compares the first ROM buffer address 0x01 data and the first ram buffer address 0x01 data; reading the data of the first ROM BUFFEER address 0x 18-0 x1F and the data of the first RAM BUFFEER address 0x 18-0 x1F, comparing, and if the data are equal, the test is passed; if not, the test fails.

Example ten

The embodiment of the invention also provides a test method which is applied to any one of the test systems.

Fig. 5 is a schematic flowchart of a testing method according to an embodiment of the present invention, and as shown in fig. 5, the method includes:

step 501, a first interface module reads first data to be tested from a first cache, sends the first data to be tested to tested equipment, receives second data to be tested from the tested equipment, and caches the second data to be tested to the first cache;

step 502, when the first data to be tested and the second data to be tested satisfy a preset condition, the first central processing module determines that the data transmission test of the device to be tested is successful.

Compared with the prior art, the embodiment of the invention provides a test system with a novel architecture, the tested equipment can be automatically tested only by writing preset conditions and data to be tested in the test system, and the test efficiency is higher.

Those skilled in the art can understand that the operations of the control unit in the method for implementing the above embodiments may be implemented by a program instructing related hardware (sensors), where the program is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, etc.) or a processor (processor) to execute the operations executed by the control unit in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific embodiments for practicing the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.

Claims

1. A test system, comprising:

2. The test system of claim 1,

3. The test system of claim 2,

when the first data to be measured includes first digital quantity data and first analog quantity data, and the second data to be measured includes second digital quantity data and second analog quantity data, the preset condition includes one of:

4. The test system of claim 3,

5. The test system of claim 1,

the first cache comprises a first read-only memory Buffer area ROM Buffer and a first random access memory Buffer area RAM Buffer;

the first ROM Buffer is used for storing the first data to be tested;

6. The test system of claim 5,

a first address in the first ROM Buffer is used for caching first digital quantity data, and a second address is used for caching first analog quantity data;

7. The test system of claim 5,

the second cache is a second RAM Buffer;

8. The test system of claim 5,

the second cache comprises a second ROM Buffer and a second RAM Buffer;

9. The test system of claim 1,

10. A test method, which is applied to the test system according to any one of claims 1 to 9; the method comprises the following steps: