CN1108397A - High-speed P.I.D. adjustment device for nerve network of digital type - Google Patents

High-speed P.I.D. adjustment device for nerve network of digital type Download PDF

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Publication number
CN1108397A
CN1108397A CN 94108684 CN94108684A CN1108397A CN 1108397 A CN1108397 A CN 1108397A CN 94108684 CN94108684 CN 94108684 CN 94108684 A CN94108684 A CN 94108684A CN 1108397 A CN1108397 A CN 1108397A
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adder
interlock device
subtracter
data interlock
output
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CN1035694C (en
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鲍立威
何敏
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Zhejiang University ZJU
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Zhejiang University ZJU
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Abstract

A digital nerve network high speed proportional integro-differential adjuster is comprised of voltage frequency converters VFC1, VFC2, counters JS1, JS2, subtracters JF1 to JF4, data lockers SS1 to SS8, multipliers CF1 to CF3, adders A1 to A3 and D/A converter DAC. The voltage signal amplitude is expressed as frequency codes through the voltage frequency converters, operation is performed on the base of the number of pulses expressed as binary number in a sampling period, thus greatly shortening the operation period, it can achieve the operation of PID control rule in microsecond order.

Description

High-speed P. I.
The present invention relates to a kind of digital proportional integral differential adjuster.
In the background technology field, existing various digital proportional integral differentials (PID) adjuster is realized by circuit such as D/A switch, serial arithmetic circuit and mould/number conversions, generally be that control program is solidified in memory in the mode of computing module, when carrying out the control law computing, call and finish the calculating of control law by CPU, its execution cycle is at least more than a few tens of milliseconds, this is fully applicable for general process, but just can not be suitable for for the high speed processes of Period Process at several milliseconds or Microsecond grade. Simultaneously because the complexity of the inherent characteristic of process own, currently used such as technology such as on-line identifications, not only prolong execution cycle, and strengthened the workload of Control System Design and exploitation, moreover usually be difficult to prove effective, can't tackle the problem at its root. Therefore, demand developing a kind of PID adjuster for high speed processes urgently, and consider the defective of Analogic Electronic Circuits aspect anti-interference, be digital so also need designed high speed PID adjuster, thereby fundamentally solve the automatic control problem of this class high speed processes.
Nerve network controller is a kind of adaptive controller based on study that proposes in recent years, and major part is to adopt software mode to realize that its execution cycle can't be realized at all in Microsecond grade; In addition, also useful hardware mode is realized, such as bold and unconstrained general Field (Hopfield) network that adopts analog circuit to realize, also has and adopts large scale integrated circuit or the modes such as optics or superconduction to realize. These or because the defective of analog circuit aspect anti-interference and accuracy; Or its starting point be placed on network self study in nature, in order to solving the control of common complex process, and for high speed processes, also do not have a kind of simple and reliable and applicable high-speed figure adjuster at present.
The objective of the invention is: a kind of nerve network of digital type high speed PID adjuster is provided, it is to be referred from Neurobiology about the relevant achievement of animal behavior control, adopt a kind of computing circuit and signal conversion regime with parallel character, computing is built on the basis of frequency coding of signal, make the cycle of conversion and computing dwindle several thousand times, thereby fundamentally solve the problem of the automatic adjusting of high speed processes, to be adapted to the needs of high speed processes control.
Technical scheme of the present invention is: it comprises sends into measured value signal V1Voltage-frequency converter VFC1The rear counter JS that connects1Connect afterwards again data interlock device SS1, with the voltage signal V that directly will represent setting value2The corresponding pulse train that produces through frequency coding is calculated at the pulse number in sampling period and is inputted respectively data interlock device SS1、SS 2, through subtracter JF1The rear data interlock device SS that connects3、SS 4, while subtracter JF1Through data interlock device SS3The rear subtracter JF that connects2, data interlock device SS3、SS 4The rear subtracter JF that connects3, subtracter JF2、JF 3The rear subtracter JF that connects4, subtracter JF4With data interlock device SS5Rear continued multiplication device CF1, subtracter JF1With data interlock device SS6Rear continued multiplication device CF2, multiplier CF2With subtracter JF2The rear adder A that connects1, adder A1With multiplier CF1The rear adder A that connects2, adder A2With data interlock device SS7Rear continued multiplication device CF3, multiplier CF3With data interlock device SS8The rear adder A that connects3, adder A3The rear digital to analog converter DAC that connects, it is output as control action voltage signal V3 In above-mentioned, subtracter can connect and compose counter JS by adder and former radix-minus-one complement selector1、JS 2Reset, by clock signal control, at the terminal point in each sampling period, counter JS1、JS 2Be reset.
To setting value V2Frequency coding also can be by voltage-frequency converter VFC2Sum counter JS2Consist of its count value input data interlock device SS2 The data interlock device can consist of with latch or register or trigger.
The present invention compares with background technology, the useful effect that has is: the voltage signal amplitude is expressed as frequency coding by voltage-frequency converter, the basis of computing is that the pulse number in the sampling period is expressed as binary number, it can shorten the cycle of computing greatly, in the computing of Microsecond grade realization PID control law, fundamentally solve the automatic adjusting problem of high speed processes.
Below in conjunction with accompanying drawing, by the detailed description to embodiment, provide details of the present invention.
Fig. 1, line construction block diagram of the present invention;
The enforcement illustration of Fig. 2, line construction block diagram of the present invention;
The execution cycle time network calculating chart of Fig. 3, the embodiment of the invention 1;
The line construction block diagram of Fig. 4, another kind of embodiment of the present invention.
In Fig. 1:
T 1-counter JS1Reseting controling signal; T2-counter JS2Reseting controling signal;
T 3-data device lock 1 control signal; T4-data device lock 2 control signals;
T 5-data device lock 3 control signals; T6-data device lock 4 control signals;
T 7-data device lock 6 control signals; T8-data device lock 5 control signals;
T 9-data device lock 8 control signals; T10-data device lock 7 control signals;
V 1The input of-measurement signal voltages; V2The input of-duty setting signal voltage;
P 1-T/T iThe parameter input; P2-T PThe input of/T parameter;
P 3-K PThe parameter input; V3-output control action voltage signal.
PID adjuster incremental form of the present invention is:
Δu n＝K P[(e n-e n-1)+T/T i·e n+T D/T(e n-2 en-1+e n-2)]
In the formula: Δ unIt is the output control action increment in n cycle; KP: be the adjuster amplification coefficient; Ti: be the time of integration; TD: be derivative time; T is the sampling period; en: be the deviation of measuring-signal and setting value.
Above-mentioned incremental form is turned to the position form:
u n＝Δu n+u n-1    u n-be the n cycle to export control action.
As shown in Figure 1, be located at the n cycle, the voltage signal of measured value and setting value is through voltage-frequency converter VFC1、VFC 2Be converted into pulse signal, the frequency correspondence of pulse train the amplitude of voltage signal, by counter JS1、JS 2To two pulse trains in the sampling period inside counting, at data interlock device SS1、SS 2Middlely two count values are deposited subtracter JF1Be output as the poor N of two step-by-step countingsn，N nThat corresponding is the deviation e of measured value and setting valuen(other Nn-1With en-1，N n-2With en-2Deng relation object with). At this moment data interlock device SS3In data be the N in a upper cyclen-1, and data interlock device SS4In data are Nn-2, subtracter JF2Be output as (Nn-N n-1), subtracter JF3Be output as (Nn-1-N n-2), subtracter JF4Be output as (Nn-2N n-1+N n-2), data interlock device SS5In data in (TD/ T), multiplier CF1Output be [TD/T(N n-2N n-1+N n-2)], data interlock device SS3In data are (T/Ti), multiplier CF2Output be (T/Ti·N n), adder A1Output in [(Nn-N n-1)+T/T i·N n], adder A2Output be [(Nn-N n-1)+T/T i·N n +T D/T(N n-2N n-1+N n-2)], data interlock device SS7In data are KP, multiplier CF3Output be Δ un＝K P[(N n-N n-1)+T/T i·N n+T D/T(N n-2N n-1+N n-2)]，Δ u nOutput control action Δ N in ' corresponding the PID adjuster incremental formn, data interlock device SS8In data are upper periodic Control effect u 'n-1, therefore, adder A3Output be control action un＝Δu n+u n, u at this momentnCorresponding control action un, with frequency coding, be converted into control action voltage signal u through DACnExecuting agency is sent in output. Wherein, data interlock device SS5In (TD/ T), data interlock device SS6In (T/Ti) and the data interlock device in KPIt is the parameter of controller designing institute input. Data interlock device SS8Middle uo(initial value) puts median, as adder A3Computing when finishing, data interlock device SS3Refresh Data be un When the n+1 cycle, data interlock device SS3Refresh Data be un, data interlock device SS4Refresh Data be Nn-1, subtracter JF1Output be Nn+1。
Embodiment 1: as shown in Figure 2, establishing specified sample period is 30 microseconds, voltage-frequency converter VFC1And VFC2Adopt AD650, the input voltage range of AD650 is 0～10V, maximum full scale frequency is 1MHz, if measuring-signal is III type standard signal, its amplitude range is 1～5V, then in 30 microseconds, the output pulse number of AD650 is 3～15, it is expressed as binary number, all computings are based upon on the basis of frequency coding of signal of these binary number forms, the digit chip that adopts and their operation time are shown in subordinate list, then according to the line assumption diagram of Fig. 2, finish the time of once-through operation, according to network calculations shown in Figure 3 be: 51,+30,+25,+25,+30,+30,+25,+25,+25,+25,+25,+5+,25+,25+,70+,25+,25+,5+2,5+2 5+103+25+25+25+135=859 (ns), namely finishing the required time of computing is 859 nanoseconds (ns). In Fig. 2The presentation logic high level.
Embodiment 2: as shown in Figure 4, it is on the basis of embodiment 1, increases by one take 8098 single-chip microcomputers as core, realizes regulator parameter TD/T，T/T i，K POptimization calculate, make the error accumulation of adjusting reach minimum, the optimization of parameter is that the observation by several cycles realizes. So just can realize that PID regulates the self adaptation of parameter, and among the embodiment 1, the adjusting by manually realizing of pid parameter.
Subordinate list:
Title and element Operation time and explanation
Voltage-frequency converter 1, AD650 Input voltage range 0～10V, maximum full scale frequency 1MHz.
Voltage-frequency converter 2, AD650 The same
Counter 1, SN74LS93 ＜51ns is controlled by clock signal, and the count value in per 30 microseconds send data interlock device 1 temporary.
Counter 2, SN74LS93 ＜51ns is controlled by clock signal, and the count value in per 30 microseconds send data interlock device 2 temporary.
Data interlock device 1, SN74LS75 The counted number of pulses of＜30ns storage counter 1 in 30 microseconds is when each cycle begins, by the counted number of pulses in 30 microseconds in the clock control upper cycle of output, as the current operand in this cycle.
Data interlock device 2, SN74LS75 Binary code and the output of the corresponding step-by-step counting number within the sampling period of＜30ns storage setting value.
Former radix-minus-one complement selector 1, SN74H87 ＜25ns sets low level at its control end, the output radix-minus-one complement, and it and adder 1 consist of subtracter
Adder 1, SN74LS283 ＜25ns consists of 8 adders by 2 SN74LS283, puts 1 at its minimum carry end, makes the radix-minus-one complement of former radix-minus-one complement selector 1 output become complement code, and this adder is finished signed addition. Its output is 7 figure place complement forms of tape symbol position (highest order).
Data interlock device 3, SN74LS75 The subtraction in a upper cycle of＜30ns storage poor by refreshing of clock control data, is made of two 74LS75.
Data interlock device 4, SN74LS75 The poor of a cycle gone up in＜30ns storage again, by refreshing of clock control data, is made of two 74LS75.
Former radix-minus-one complement selector 2, SN74H87 ＜25ns is made of 2 74H87, sets low level at its control end, and the output radix-minus-one complement consists of subtracters with adder 3, if subtrahend for just, complement code=true form, when subtraction becomes addition, the sign bit reversion, the value bit negate adds 1, so eight whole negates; If subtrahend is for negative, the value bit negate adds 1, turns to true form, when subtraction turns to addition, and the sign bit reversion
, so the complement code=true form of positive number is eight all negates
Former radix-minus-one complement selector 3, SN74H87 The relevant explanation of＜25ns is with former radix-minus-one complement selector 2
Not gate 1, SN74S04 Its input of 5ns be adder 1 and highest order, i.e. sign bit, symbol are zero, are positive numbers, by not gate 1 negate, the output high level is controlled former radix-minus-one complement selector 4 output true forms; Symbol is 1 to be negative, and by not gate 1 negate, output low level is controlled former radix-minus-one complement selector 4 output radix-minus-one complements.
Adder 2, SN74LS283 ＜25ns is made of 2 74LS283, and NAND gate 1, former radix-minus-one complement selector 4 consist of benefit/former transcoder, because multiplier 1 is to use the true form computing, if adder 1 and be negative, not gate 1 output low level then, former radix-minus-one complement selector 4 negates are if adder 2 realizes that negates add 1, adder 1 and for just, not gate 1 output high level, adder 2 adds 0, does not change, the value bit of output is sent multiplier 1, and sign bit send XOR gate 1.
Former radix-minus-one complement selector 4, SN74H87 ＜25ns is made of 2 74H87, and only to rear 7 effects of adder 1 output, namely a logarithm value position acts on, and control end is by the output control of not gate 1
Adder 3, SN74LS283 ＜25ns is made of 2 74LS283, and minimum carry end is put 1 and consisted of subtracters with former radix-minus-one complement selector 2, is output as complement form.
Adder 4, SN74LS283 ＜25ns is made of 2 74LS283, and lowest order carry end puts 1, consists of subtracter with former radix-minus-one complement selector 3, is output as complement form.
Data interlock device 6, SN74LS75 ＜30ns is made of 2 74LS75, presets the position of decimal point, T/T1 is turned to binary system be stored in wherein
Multiplier 2,8 * 8 multipliers 70ns consists of 8 * 8 multipliers by SN74284, SN74285, SN74H 183, SN74S181, SN74S182, produces 16 and amasss.
Adder 5, SN74LS283 ＜25ns consists of lowest order carry end by 2 74LS283 and puts 1, consists of subtracter with former radix-minus-one complement selector 10.
Former radix-minus-one complement selector 10, SN74H87 ＜25ns is made of 2 74H87, and control end is put
Low by flat, the output radix-minus-one complement consists of subtracter with adder 5, and other is referring to former radix-minus-one complement selector 2,3
Not gate 2, SN74S04 Its input of 5ns be adder 5 and sign bit, and for just, sign bit is 0, by not gate 2 output high level, controls former radix-minus-one complement selector 6 output true forms; With for negative, sign bit is 1, not gate 2 output low levels are controlled former radix-minus-one complement selector 6 output radix-minus-one complements.
XOR gate 1, SN74S86 7ns output is the sign bit that multiplier 2 amasss.
Not gate 3, SN74S04 Its input of 5ns is the output of exclusive-OR gate 1, i.e. the long-pending symbol of multiplier 2, and long-pending for just, not gate 3 output high level are controlled former radix-minus-one complement selector 5 and are exported true forms; Long-pending for negative, its output low level is controlled former radix-minus-one complement selector 5 output radix-minus-one complements.
Former radix-minus-one complement selector 5, SN74H87 ＜25ns is made of 4 74H87, and under the control of not gate 3, NAND gate 3, adder 7 consist of former/complement code converter, a value bit effect to product.
Former radix-minus-one complement selector 6, SN74H87 ＜25ns is made of 2 74H87, and under the control of not gate 2, NAND gate 2, adder 6 consists of benefits/former transcoders, to adder 5 and the value bit effect.
Adder 6, SN74LS283 If＜25ns adder 5 output and for just, addend from adder 5 high positions is 0, former radix-minus-one complement selector 6 output true forms, the true form of these positive numbers of adder 6 output: if adder 5 outputs and for negative, addend from adder 5 high positions is 1, the radix-minus-one complement of former radix-minus-one complement selector 6 output value bit through adder 6, is exported this negative true form. Adder 6 is made of two 74LS283
Adder 7, SN74LS283 If＜25ns consists of product for just by 4 74LS283, XOR gate 1 output 0, adder 7 output positive number true forms, its complement code namely, if product for negative, XOR gate 1 output 1, adder 7 adds 1 with the radix-minus-one complement of long-pending value bit, makes it to become complement code
Multiplier
7,8 * 8 multipliers 70ns consists of 8 * 8 multipliers by SN74284, SN74285, SN74H 183, SN74S181, SN74S182, produces 16 and amasss.
Data interlock device 5, SN74LS75 ＜30ns is made of 2 74LS75, presets the position of decimal point, with TD/ T turns to binary system and is stored in wherein
XOR gate 2, SN74S86 Its output of 7ns is the sign bit of multiplier 1 output product.
Former radix-minus-one complement selector 7, SN74H87 ＜25ns is made of 4 74H87, under the control of not gate 4, and NAND gate 4, adder 10 consists of former/complement code converter, a value bit effect to product.
Adder 9, SN74LS283 ＜25ns is made of 4 74LS283, and the complement code that adder 7 and adder 3 are inputted is made addition, is output as complement form, notes scaling position during line.
Adder 8, SN74LS283 ＜25ns is made of 4 74LS283, and the complement code that adder 9 and adder 10 are exported is made addition, is output as complement form. Note scaling position during line.
Not gate 4, SN74S04 Its input of 5ns is the output of exclusive-OR gate 2, i.e. the long-pending symbol of multiplier 1, and long-pending for just, not gate 4 output high level are controlled former radix-minus-one complement selector 7 and are exported true forms; Long-pending for negative, its output low level is controlled former radix-minus-one complement selector 7 output radix-minus-one complements.
Adder 10, SN74LS283 ＜25ns is made of 4 74LS283, if product for just, XOR gate 2 outputs 0, adder 10 output positive number true forms, its complement code namely, if product for negative, XOR gate 2 outputs 1, adder 10 adds 1 with the radix-minus-one complement of long-pending value bit, makes it to become complement code
Former radix-minus-one complement selector 8, SN74H87 ＜25ns is made of 4 74H87, and under the control of not gate 5, by not gate 5, former radix-minus-one complement selector 8, adder 11 consists of benefits/former transcoders, only adder 8 is exported and the value bit effect
Adder 11, SN74LS283 ＜25ns is made of 4 74LS283, and relevant explanation can be referring to adder 6.
XOR gate 3, SN74S86 Its input of 7ns be adder 11 and sign bit and data interlock device 7 in the sign bit of data, output is the sign bit of the product of multiplier 3.
Multiplier 3,16 * 16 multiplication 103ns consists of 16 * 16 multipliers by SN74284, SN74285, SN74 H183, SN74S181, SN74S182, produces 32 and amasss.
Data interlock device 7, SN74LS75 ＜30ns is made of 4 74LS75, presets the position of decimal point, with KPTurning to binary system is stored in wherein.
Former radix-minus-one complement selector 9, SN74H87 ＜25ns is made of 8 74H87, under the control of not gate 6, and NAND gate 6, adder 12 consists of former/complement code converter, a value bit effect to product.
Not gate 6, SN74S04 Its input of 5ns is the output of exclusive-OR gate 3, is used for controlling the output of former radix-minus-one complement selector 9, and relevant explanation is referring to adder 10.
Data interlock device 8, SN74LS75 ＜30ns is made of 8 74LS75, presets the position of decimal point, under clock signal control, send adder 13 with data, after the computing of digital to analog converter is finished, under clock control, with adder 13 and be stored in wherein, it is new to finish data system.
Adder 13, SN74LS283 ＜25ns is the position signalling of control action by the output that 8 74LS283 consist of it, just should be, so true form=complement code
Digital to analog converter, DAC-08H 135ns is made of 4 DAC-08H

Claims (3)

1. a high-speed P. I. is characterized in that: comprise and send into measured value voltage signal V1Voltage-frequency converter VFC1The rear counter JS that connects1, with the voltage signal V that directly will represent setting value2The corresponding pulse train that produces through frequency coding is calculated at the pulse number in sampling period and is inputted respectively data interlock device SS1、SS 2, through subtracter JF1The rear data interlock device SS that connects3、SS 4, while subtracter JF1With data interlock device SS3The rear subtracter JF that connects2, data interlock device SS3、SS 4The rear subtracter JF that connects3, subtracter JF2、JF 3The rear subtracter JF that connects4, subtracter JF4With data interlock device SS5Rear continued multiplication device CF1, subtracter JF1With data interlock device SS6Rear continued multiplication device CF2, multiplier CF2With subtracter JF2The rear adder A that connects1, adder A1With multiplier CF1The rear adder A that connects2, adder A2With data interlock device SS7Rear continued multiplication device CF3, multiplier CF3With data interlock device SS8The rear adder A that connects3, adder A3The rear digital to analog converter DAC that connects, it is output as the control action voltage signal.
2. adjuster according to claim 1 is characterized in that: can be by voltage-frequency converter VFC to the frequency coding that sets value2Sum counter JS2Consist of its count value input data interlock device SS2。
3. adjuster according to claim 1 is characterized in that: the data interlock device can use latch, register, trigger to consist of.
CN94108684A 1994-09-10 1994-09-10 High-speed P.I.D. adjustment device for nerve network of digital type Expired - Fee Related CN1035694C (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107733434A (en) * 2016-08-12 2018-02-23 中芯国际集成电路制造(上海)有限公司 Analog-digital converter and electronic equipment

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SU970319A1 (en) * 1981-04-06 1982-10-30 Предприятие П/Я В-8296 Digital control system
SU1180842A1 (en) * 1984-01-06 1985-09-23 Предприятие П/Я Г-4152 Digital self-adjusting system with combined control
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CN107733434A (en) * 2016-08-12 2018-02-23 中芯国际集成电路制造(上海)有限公司 Analog-digital converter and electronic equipment

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