CN1035695C - Digital Neural Network High Speed Incomplete Differential Proportional Integral Differential Regulator - Google Patents
Digital Neural Network High Speed Incomplete Differential Proportional Integral Differential Regulator Download PDFInfo
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Abstract
一种数字式神经网络高速不完全微分比例积分微分调节器，是由压频转换器VFC，计数器JS，减法器JF1～JF5，数据锁定器SS1～SS11，乘法器CF1～JF6，加法器A1～A5及数模转换器DAC为主要器件构成的。将电压信号幅度通过压频转换器表达为频率编码，运算的基础是采样周期内的脉冲个数表达为二进制数，它可大大缩短运算的周期，在微秒级实现不完全微分PID控制律的运算，从根本上解决高速过程的自动调节问题。
A digital neural network high-speed incomplete differential proportional integral differential regulator is composed of a voltage-frequency converter VFC, a counter JS, a subtractor JF 1 ～ JF 5 , a data locker SS 1 ～SS 11 , a multiplier CF 1 ～JF 6. Adders A 1 ~ A 5 and digital-to-analog converter DAC are the main components. The voltage signal amplitude is expressed as a frequency code through a voltage-frequency converter. The basis of the operation is to express the number of pulses in the sampling period as a binary number, which can greatly shorten the operation cycle and realize the incomplete differential PID control law at the microsecond level. Operation, fundamentally solve the problem of automatic adjustment of high-speed process.
Description
The present invention relates to a kind of digital proportional integral differential adjuster.
In the background technology field, existing various digital proportional integral differentials (PID) adjuster is realized by circuit such as D/A switch, serial arithmetic circuit and mould/number conversions, generally be that control program is solidified in memory in the mode of computing module, when carrying out the control law computing, call and finish the calculating of control law by CPU, its execution cycle is at least more than a few tens of milliseconds, this is fully applicable for general process, but just can not be suitable for for the high speed processes of Period Process at several milliseconds or Microsecond grade. Simultaneously because the complexity of the inherent characteristic of process own, currently used such as technology such as on-line identifications, not only prolong execution cycle, and strengthened the workload of Control System Design and exploitation, moreover usually be difficult to prove effective, can't tackle the problem at its root. In the background technology field, the disclosed former Soviet Union on the 23rd patent November in 1988 (SU1439-531-A) has proposed a kind of Digital Control System of continuous oscillation object, it is to have added again a digital circuit outside control module (control unit), thereby makes the frequency of continuous oscillation object and amplitude have fast response time and the high characteristics of precision. In the digital circuit that adds, used analog-digital converter (ADC), subtracter (subtracter), setting apparatus (setter), increment unit (increament unit), adder (summator), register (register), multiplier (miultiplier), counter (scaling unit), symbol is differentiated sum counter (sign discriminator and scaling unit), symbol extraction device (sign extractor), the purpose of these Control System Designs such as squarer (squarer) are that the effect by control module and digital circuit makes amplitude and frequency and the target amplitude that sets and the frequency error minimum of continuous oscillation object. This control system has still adopted analog-digital converter (ADC) on mentality of designing, the sort signal conversion regime has limited the further raising of this control system response speed, its system is fully for the control of continuous oscillation object, so be difficult to be applied to the automatic control of other general process simultaneously. Therefore, demand developing a kind of PID adjuster for high speed processes urgently, and consider the defective of Analogic Electronic Circuits aspect anti-interference, be digital so also need designed high speed PID adjuster, thereby fundamentally solve the automatic control problem of this class high speed processes.
Nerve network controller is a kind of adaptive controller based on study that proposes in recent years, and major part is to adopt software mode to realize that its execution cycle can't be realized at all in Microsecond grade; In addition, also useful hardware mode is realized, such as bold and unconstrained general Field (Hopfield) network that adopts analog circuit to realize, also has and adopts large scale integrated circuit or the modes such as optics or superconduction to realize. These or because the defective of analog circuit aspect anti-interference and accuracy; Or its starting point be placed on network self study in nature, in order to solving the control of common complex process, and for high speed processes, also do not have a kind of simple and reliable and applicable high-speed figure adjuster at present.
The objective of the invention is: a kind of nerve network of digital type high speed incomplete differential PID adjuster is provided, it is to be referred from Neurobiology about the relevant achievement of animal behavior control, adopt a kind of computing circuit and signal conversion regime with parallel character, computing is built on the basis of frequency coding of signal, make the cycle of conversion and computing dwindle several thousand times, thereby fundamentally solve the problem of the automatic adjusting of high speed processes, to be adapted to the needs of high speed processes control.
Technical scheme of the present invention is: comprise counter, subtracter, adder, multiplier, also comprise and send into measured value voltage signal V1The first voltage-frequency converter VFC; The the first counter JS that links to each other with the first voltage-frequency converter VFC; The the first data interlock device SS that links to each other with the first counter JS1 The second data interlock device SS2, setting value voltage signal V2Turn to the binary number of its frequency coding pulse number within the sampling period, send into the second data interlock device SS2 The first subtracter JF1, be connected in the first data interlock device SS1With the second data interlock device SS2Afterwards; The 3rd data interlock device SS3, be connected in the first subtracter JF1Afterwards; The 4th data interlock device SS4, be connected in the 3rd data interlock device SS3Afterwards; The first multiplier CF1, be connected in the 5th data interlock device SS5With the first subtracter JF1Afterwards; The second subtracter JF2, be connected in the 3rd data interlock device SS3With the first subtracter JF1Afterwards; The 3rd subtracter JF3, be connected in the 3rd data interlock device SS3With the 4th data interlock device SS4Afterwards; The 4th subtracter JF4, be connected in the second subtracter JF2With the 3rd subtracter JF3Afterwards; The second multiplier CF2, be connected in the 4th subtracter JF4With the 6th data interlock device SS6Afterwards; First adder A1, be connected in the second multiplier CF2With the second subtracter JF2Afterwards; Second adder A2, be connected in first adder A1With the first multiplier CF1Afterwards; The 3rd multiplier CF3, be connected in second adder A2With the 7th data interlock device SS7Afterwards; The 4th multiplier CF4, be connected in the 3rd subtracter JF3With the 8th data interlock device SS8Afterwards; The 5th multiplier CF5, be connected in the 9th data interlock device SS9With the tenth data interlock device SS10Afterwards; The 3rd adder A3, be connected in the 4th multiplier CF4With the 5th multiplier CF5Afterwards, the 3rd adder A3Output send again the tenth data interlock device SS10 The 5th subtracter JF5, be connected in the 3rd adder A3With the tenth data interlock device SS10Afterwards; The 6th multiplier CF6, be connected in the 5th subtracter JF5With the 9th data interlock device SS9Afterwards; The 4th adder A4, be connected in the 6th multiplier CF6With the 3rd multiplier CF3Afterwards; Slender acanthopanax musical instruments used in a Buddhist or Taoist mass A5, be connected in the 4th adder A4With the 11 data interlock device SS11Afterwards; Digital to analog converter DAC, slender acanthopanax musical instruments used in a Buddhist or Taoist mass A5Output send digital to analog converter DAC and the 11 data interlock device SS11, digital to analog converter DAC is output as control action voltage signal V3 In above-mentioned, subtracter can be made of adder and former radix-minus-one complement selector, and resetting of counter controlled by clock signal, and at the terminal point in each sampling period, counter is reset.
Frequency coding to duty setting signal can place the second data interlock device SS2In, also can as the coding processing mode of measured value voltage signal, will set value voltage signal V2Through the second voltage-frequency converter VFC2With the second counter JS2Send into the second data interlock device SS2Finish. Each data interlock device SS1～SS
11Can consist of with latch or register or trigger.
The present invention compares the useful effect that has with background technology: the voltage signal amplitude is expressed as frequency coding by voltage-frequency converter, the basis of computing is that the pulse number in the sampling period is expressed as binary number, it can shorten the cycle of computing greatly, in the computing of Microsecond grade realization PID control law, fundamentally solve the automatic adjusting problem of high speed processes.
Below in conjunction with accompanying drawing, by the detailed description to embodiment, provide details of the present invention.
Fig. 1, line construction block diagram of the present invention;
The enforcement figure of Fig. 2, line construction block diagram of the present invention.
In Fig. 1:
T
1: the counter reseting controling signal; T2: data interlock device SS1Control signal;
T
3: data interlock device SS2Control signal; T4: data interlock device SS3Control signal;
T
5: data interlock device SS4Control signal; T6: data interlock device SS5Control signal;
T
7: data interlock device SS11Control signal T8: data interlock device SS7Control signal;
T
9: data interlock device SS6The control letter; T10: data interlock device SS8Control signal;
T
11: data interlock device SS9Control signal; T12: data interlock device SS10Control signal;
V
1: the input of measured value voltage signal; V3: output control action voltage signal;
V
2: the duty setting signal input; P1：T/T
IThe parameter input;
P
2：K
PThe parameter input; P3：T
D/T
SThe parameter input;
P
4：K
P(T
D/T
S) the parameter input; P5: the input of K parameter.
The position form of incomplete differential PID adjuster is:
In the formula: T is the sampling period; TIIt is the time of integration; TDIt is derivative time; KPIt is the adjuster amplification coefficient; TS＝T
D/K
D+T；K
DIt is the differential gain;
k＝(T
D/K
D)/(T
D/K
D+T) ；
Y
D(n-1)＝K
P·T
D/T
6·(e
n-e
n-1)+k·Y
D(n-2)
According to following formula:
Like this:
Δu
n＝u
n-u
n-1
＝K
P{(e
n-e
n-1)+T/T
I·e
n+T
D/T
6·[(e
n-e
n-1)-(e
n-1
-e
n-2)]}+k·(Y
D()n-1-Y
D(n-2)) in the formula: unIt is the control action in n cycle; Δ unIt is the output control action increment in n cycle; enIt is the deviation of n period measurement signal and setting value.
The Dynamic Signal of this circuit is achieved in that the n cycle that is located at, as shown in Figure 1, and measured value voltage signal V1VFC is encoded to pulse train through voltage-frequency converter, and the frequency correspondence of pulse train the amplitude of voltage signal, and count value deposits in data interlock device SS1In, setting value V2Corresponding voltage amplitude turns to the number of the pulse train in the one-period of binary number form as calculated, is stored in data interlock device SS2Among, subtracter JF1Be output as the difference N of two pulse numbersn，N
nThat corresponding is the deviation e of measured value and setting valuen(other Nn-1With en-1，N
n-2With en-2Deng relation object with). At this moment data interlock device SS3In data be the N in a upper weekn-1, and data interlock device SS4In data be Nn-2, subtracter JF2Output (Nn-N
n-1), subtracter JF3Output be (Nn-1-N
n-2), subtracter JF4Output be (Nn-2N
n-1+N
n-2), data interlock device SS5In data are (T/TI), multiplier CF1(T/TI·N
n), data interlock device SS6In data are (TD/T
S), multiplier CF2Output be [TD/T
S·(N
n-2N
n-1+N
n-2)], adder A1Output be [(Nn-N
n-1)
+T
D/T
S·(N
n-2N
n-1+N
n-2)], adder A2Output be [(Nn-N
n-1)+T/T
I
·N
n+T
D/T
S(N
n-2N
n-1+N
n-2)], data interlock device SS7In data are KP, multiplier CF3Output be: KP·[(N
n-N
n-1)+T/T
I·N
n+T
D/T
S·(N
n-2N
n-1
+N
n-2)], data interlock device SS8In data are (KP·T
D/T
S), multiplier CF4Output be [KP·T
D/T
S(N
n-1-N
n-2)], data interlock device SS9In data are k, data interlock device SS10In data are YD(n-2), multiplier CF5Output be (kYD(n-2)), adder A3Output be: YD(n-1)＝K
P·T
D/T
S·(N
n-1-N
n-2)+k·
Y
Dn-2), subtracter JF5Output be [YD(n-1)-Y
D(n-2)], multiplier CF6Output be k (YD(n-1)-Y
D(n-2)), adder A4Output be Δ un, data interlock device SS11In data are un-1, adder A5Output be un＝Δu
n+u
n-1, the output of digital to analog converter DAC is the u with the voltage signal form after digital-to-analogue conversionn Wherein: SS5In T/TI、SS
6In TD/T
S、SS
7In KP、SS
8In KP·T
D/T
S、SS
9In k be predefined parameter, also can adjust online. SS10In YD(n-2)When initial, put an initial value, at JF5After computing was finished, its intermediate value refreshed and is A3Output, SS11Middle un-1Put an initial value when initial, after the DAC conversion was complete, its intermediate value refreshed and is A5Output. When the n+1 cycle, SS3Refresh Data be Nn，SS
4Refresh Data be Nn-1，JF
1Output be Nn+1。
Embodiment: as shown in Figure 2, if specifying the sampling period is 30 microseconds, voltage-frequency converter VFC adopts AD650, the input voltage range of AD650 is 0～10V, maximum full scale frequency is 1MHz, if measuring-signal is III type standard signal, its amplitude range is 1～5V, then in 30 microseconds, the output pulse number of AD650 is 3～15, and it is expressed as binary number, and all computings are based upon on the basis of signal frequency coding of these binary number forms, the digit chip that adopts and their operation time are shown in subordinate list, among Fig. 2The presentation logic high level. According to line assumption diagram shown in Figure 2, the time of finishing once-through operation is 1029ns.
Subordinate list:
| Title and element | Operation time and relevant explanation |
| Voltage-frequency converter, AD650 | Input voltage range 0～10V, maximum full scale frequency 1MHz. |
| Counter, SN74LS93 | ＜51ns, by clock signal control, the count value in per 30 microseconds send data interlock device 1 temporary. |
| Data interlock device 1, SN74LS75 | ＜30ns, the counted number of pulses of storage counter in 30 microseconds is when each cycle begins, by the counted number of pulses in 30 microseconds in the clock control upper cycle of output, as the current operand in this cycle. |
| Data interlock device 2, SN74LS75 | ＜30ns, binary code and the output of the corresponding step-by-step counting number within the sampling period of storage setting value. |
| Former radix-minus-one complement selector 1, SN74H87 | ＜25ns sets low level at its control end, the output radix-minus-one complement, and it and adder 1 consist of subtracter. |
| Adder 1, SN74LS283 | ＜25ns, the radix-minus-one complement that consists of 8 outputs by two SN74LS283 becomes adds musical instruments used in a Buddhist or Taoist mass, puts 1 at its minimum carry end, makes 1 yard of former radix-minus-one complement selector, and this adder is finished signed addition. Its output is 7 figure place complement forms of tape symbol position (highest order). |
| Data interlock device 3, SN74LS75 | ＜30ns stored subtraction poor in a upper cycle, by refreshing of clock control data, was made of two 74LS75. |
| Data interlock device 4, SN74LS75 | ＜30ns, the poor of a cycle gone up in storage again, by refreshing of clock control data, is made of 2 74LS75. |
| Former radix-minus-one complement selector 2, SN74H87 | ＜25ns is made of 2 74H87, sets low level at its control end, and the output radix-minus-one complement consists of subtracters with adder 3, if subtrahend for just, complement code=true form, when subtraction becomes addition, the sign bit reversion, the value bit negate adds 1, so eight whole negates; If subtrahend side is negative, the value bit negate adds 1, turns to true form, and when subtraction turned to addition, so the complement code=true form of sign bit reversion positive number was eight all negates. |
| Former radix-minus-one complement selector 3SN74H87 | ＜25ns, relevant explanation is with former radix-minus-one complement selector 2 |
| Not gate 1, SN74S04 | 5ns, its input be adder 1 and highest order, i.e. sign bit, symbol are zero, are positive numbers, by not gate 1 negate, the output high level is controlled former radix-minus-one complement selector 4 output true forms; Symbol is 1 to be negative, and by not gate 1 negate, output low level is controlled former radix-minus-one complement selector 4 output radix-minus-one complements. |
| Adder 2, SN74LS283 | ＜25ns is made of two 74LS283, and NAND gate 1, former radix-minus-one complement selector 4 consist of benefit/former transcoder, because multiplier 1 is to use the true form computing, if adder 1 and be negative, not gate 1 output low level then, former radix-minus-one complement selector 4 negates, adder 2 realizes that negates add 1, if adder 1 and for just, not gate 1 is exported high level, adder 2 adds 0, do not change, the value bit of output is sent multiplier 1, and sign bit send XOR gate 1. |
| Former radix-minus-one complement selector 4, SN74H87 | ＜25ns is made of 2 74H87, and only to rear 7 effects of adder 1 output, namely a logarithm value position acts on, and control end is by the output control of not gate 1 |
| Adder 3, SN74LS283 | ＜25ns is made of 2 74LS283, and minimum carry end puts 1, consists of subtracter with former radix-minus-one complement selector 2, is output as complement form. |
| Data interlock device 5, SN74LS75 | ＜30ns is made of two 74LS75, presets the position of decimal point, T/TI is turned to binary system be stored in wherein. |
| Multiplier 1,8 * 8 multipliers | 70ns consists of 8 * 8 multipliers by SN74284, SN74285, SN74H 183, SN74S181, SN74S182, produces 16 and amasss |
| XOR gate 1, SN74S86 | 7ns, its output is the value of the long-pending sign bit of multiplier 1. |
| Former radix-minus-one complement selector 5, SN74H87 | ＜25ns by four 74H87 consist of, NAND gate 2, adder 6 consists of former/complement code converter, only to the long-pending value bit effect of multiplier 1. |
| Not gate 2, SN74S04 | 5ns, if control former radix-minus-one complement selector 6 products for just, former radix-minus-one complement selector should be exported true form; If product is for bearing not gate 2 output low levels, former radix-minus-one complement |
| Selector 6 output radix-minus-one complements. | |
| Adder 6, SN74LS283 | ＜25ns, if multiplier 1 is long-pending for just, then adder 6 addend is 0, complement code=true form: if long-pending for bearing, adder 6 is output as radix-minus-one complement+1=complement code. |
| Adder 4, SN74LS283 | ＜25ns is made of 2 74LS283, and minimum carry puts 1, consists of subtracter with former radix-minus-one complement selector 3, is output as complement form. |
| Not gate 3, SN74S04 | 5ns, input be adder 4 and sign bit, control former radix-minus-one complement selector 6, consist of benefit/former transcoders with former radix-minus-one complement selector 6, adder 5, |
| Former radix-minus-one complement selector 6, SN74H87 | ＜25ns is made of two 74H87, is subjected to not gate 3 controls, and relevant explanation is referring to former radix-minus-one complement selector 4 |
| Adder 5, SN74LS283 | ＜25ns is made of 2 74LS283, NAND gate 3, and former radix-minus-one complement selector 6 consists of benefit/former transcoder, is output as true form. |
| Former radix-minus-one complement selector 7, SN74H87 | ＜25ns is made of 2 74H87, consists of subtracter with adder 7, and relevant explanation is referring to former radix-minus-one complement selector 2. |
| Adder 7, SN74LS283 | ＜25ns consists of minimum carry end by 3 74LS283 and puts 1, consists of subtracter with former radix-minus-one complement selector 4, is output as poor complement form. |
| Not gate 4, SN74S04 | 5ns, input be adder 7 and sign bit, control former radix-minus-one complement selector 8, relevant explanation is referring to non-1 亅 I. |
| Former radix-minus-one complement selector 8, SN74H87 | ＜25ns is referring to former radix-minus-one complement selector 4. |
| Adder 8, SN74LS283 | ＜25ns consists of benefit/former transcoder by 2 74LS283 NAND gates, 4 former radix-minus-one complement selectors 8. |
| Data interlock device 6, SN74LS75 | ＜30ns is made of two 74LS75, presets scaling position, TD/TS is turned to binary system be stored in wherein. |
| Multiplier 2,8 * 8 multipliers | 70ns is with multiplier 1. |
| XOR gate 2, SN74S86 | 7ns, output is the value of the sign bit of multiplier 2, |
| Former radix-minus-one complement selector 9, SN74H87 | ＜25ns is made of 4 74H87, the value bit effect of only multiplier 2 being amassed. |
| Not gate 5, SN74S04 | 5ns consists of former/complement code converter with former radix-minus-one complement selector 9 adders 9, referring to not gate 2. |
| Adder 9, SN74LS283 | ＜25ns is made of 4 74LS283, referring to adder 6. |
| Adder 10, SN74LS283 | ＜25ns is made of 4 74LS283, and the complement code of adder 9 and adder 3 outputs is made addition, be output as and complement form, note the position of decimal point. |
| Adder 11, SN74LS283 | ＜25ns is made of 4 74LS283, and addition is done in 10 outputs to adder 6 and adder, be output as and complement form, note the position of decimal point, |
| Former radix-minus-one complement selector 10, SN74H87 | ＜25ns is made of 4 74H87, and relevant explanation is referring to former radix-minus-one complement selector 4. |
| Not gate 6, SN74S04 | 5ns, relevant explanation is referring to not gate 1. |
| Adder 12, SN74LS283 | ＜25ns is made of 4 74LS283, consists of benefit/former code converter with former radix-minus-one complement selector 10, not gate 6, and relevant explanation is referring to adder 2. |
| Multiplier 3,16 * 16 | 103ns, multiplier 1 produces 32 and amasss. |
| Data interlock device 7, SN74LS75 | ＜30ns is made of 4 74LS75, presets scaling position, KP is turned to binary system be stored in wherein. |
| XOR gate 3, SN74S86 | 7ns, output is the value of the sign bit of multiplier 3 |
| Former radix-minus-one complement selector 11, SN74H87 | ＜25ns is made of 8 74H87, the value bit effect of only multiplier 3 being amassed. |
| Not gate 7, SN74S04 | 5ns and former radix-minus-one complement selector 11, adder 13 consist of former/complement code converter, referring to not gate 2. |
| Adder 13, SN74LS283 | ＜25ns is made of 8 74LS283, and relevant explanation is referring to adder 6. |
| Multiplier 4,8 * 8 | 70ns is with multiplier 1. |
| Data interlock device 8, SN74LS75 | ＜30ns is made of two 74LS75, presets scaling position, with KP·T D/T STurning to binary number is stored in wherein. |
| XOR gate 4, SN74S86 | 7ns output is the value of the sign bit of multiplier 4 |
| Former radix-minus-one complement selector 12, SN74H87 | ＜25ns is made of 4 74H87, the value bit effect of only multiplier 4 being amassed. |
| Not gate 8, SN74S04 | 5ns and former radix-minus-one complement selector 12, adder 14 consist of former/complement code converter, referring to not gate 2 |
| Data interlock device 9, SN74LS75 | ＜30ns is made of two 74LS75, presets scaling position, k is turned to binary system be stored in wherein. |
| XOR gate 5, SN74S86 | 7ns output is the value of the sign bit of multiplier 5 |
| Adder 14, SN74LS283 | ＜25ns is made of 4 74LS283, consists of former/complement code converter, the output complement form with former radix-minus-one complement selector 12, not gate 8. |
| Not gate 9, SN74S04 | 5ns and former radix-minus-one complement selector 13, adder 16 consist of former/complement code converter, referring to not gate 2. |
| Former radix-minus-one complement selector 13, SN74H87 | ＜25ns is made of 4 74H87, the value bit effect of only multiplier 5 being amassed. |
| Adder 16, SN74LS283 | ＜25ns is made of 4 74LS283, and relevant explanation is referring to adder 6. |
| Multiplier 5,8 * 8 | 70ns is with multiplier 1. |
| Adder 15, SN74LS283 | ＜25ns is made of 4 74LS283, and the counting of two complement forms of adder 14 and adder 16 outputs sued for peace, and its output is complement form |
| Data interlock device 10, SN74LS75 | ＜30ns is made of 4 74LS75, presets the decimal point position, after the computing in each cycle is finished, under clock signal control, with adder 15 and be stored in wherein, finish Refresh Data, wherein the complement form that saves as. |
| Former radix-minus-one complement selector 14, SN74H87 | ＜25ns is made of 4 74H87, only to the value bit effect in the data lock 10. |
| Adder 17, SN74LS283 | ＜25ns is made of 4 74LS283, is output as complement form. |
| Not gate 10, SN74S04 | 5ns and former radix-minus-one complement selector 14, adder 17 consist of benefit/former transcoder. |
| Former radix-minus-one complement selector 15, SN74H87 | ＜25ns is made of 4 74H87, is negated together in number tape symbol position in the data lock 10, and relevant explanation is referring to former radix-minus-one complement selector 2. |
| Adder 18, SN74LS283 | ＜25ns is made of 4 74LS283, consists of subtracter with former radix-minus-one complement selector 15, sees adder 3 |
| Former radix-minus-one complement selector 14, SN74H87 | ＜25ns is made of 4 74H87, only to adder 18 and the value bit effect. |
| Adder 19, SN74LS283 | ＜25ns is made of 4 74LS283, is output as complement form. |
| Not gate 11, SN74S04 | 5ns and former radix-minus-one complement selector 16, adder 19 consist of benefit/former transcoder. |
| Multiplier 6,16 * 16 | 103ns amasss but produce 32 with multiplier 1. |
| XOR gate 6, SN74S86 | 7ns output is the value of the long-pending sign bit of multiplier 6. |
| Former radix-minus-one complement selector 17, SN74H87 | ＜25ns is made of 8 74H87, only to the value of the long-pending sign bit of multiplier 6. |
| Adder 20, SN74LS283 | ＜25ns is made of 8 74LS283, is output as complement form. |
| Not gate 12, SN74S04 | 5ns and former radix-minus-one complement selector 17, adder 20 consist of former/complement code converter. |
| Adder 21, SN74LS283 | ＜25ns does addition to the number of two complement forms of adder 13 and adder 20 outputs, output be complement form and. |
| Data interlock device 11, SN74LS75 | ＜30ns is made of 4 74LS75, presets the decimal point position, after the computing in each cycle is finished, under clock signal control, with adder 22 and be stored in wherein, finish Refresh Data |
| Adder 22, SN74LS283 | ＜25ns is made of 8 74LS283, and its output is the position signalling of control action, just should be, so true form=complement code. |
| Digital to analog converter, DAC-08H | 135ns is made of four DAC-08H. |
Claims (3)
1. nerve network of digital type high speed incomplete differential proportional integral derivative controller, it comprises counter, subtracter, adder, multiplier, it is characterized in that this adjuster also comprises:
A, send into measured value voltage signal (V1) the first voltage-frequency converter (VFC);
B, the first counter (JS) that links to each other with the first voltage-frequency converter (VFC);
C, the first data interlock device (SS that links to each other with the first counter (JS)1)；
D, the second data interlock device (SS2), setting value voltage signal (V2) turn to the binary number of its frequency coding pulse number within the sampling period, send into the second data interlock device (SS2)；
E, the first subtracter (JF1), be connected in the first data interlock device (SS1) and the second data interlock device (SS2) afterwards;
F, the 3rd data interlock device (SS3), be connected in the first subtracter (JF1) afterwards;
G, the 4th data interlock device (SS4), be connected in the 3rd data interlock device (SS3) afterwards;
H, the first multiplier (CF1), be connected in the 5th data interlock device (SS5) and the first subtracter (JF1) afterwards;
I, the second subtracter (JF2), be connected in the 3rd data interlock device (SS3) and the first subtracter (JF1) afterwards;
J, the 3rd subtracter (JF3), be connected in the 3rd data interlock device (SS3) and the 4th data interlock device (SS4) afterwards;
K, the 4th subtracter (JF4), be connected in the second subtracter (JF2) and the 3rd subtracter (JF3) afterwards;
L, the second multiplier (CF2), be connected in the 4th subtracter (JF4) and the 6th data interlock device (SS6) afterwards;
M, first adder (A1), be connected in the second multiplier (CF2) and the second subtracter (JF2) afterwards;
N, second adder (A2), be connected in first adder (A1) and the first multiplier (CF1) afterwards;
O, the 3rd multiplier (CF3), be connected in second adder (A2) and the 7th data interlock device (SS7) afterwards;
P, the 4th multiplier (CF4), be connected in the 3rd subtracter (JF3) and the 8th data interlock device (SS8) afterwards;
Q, the 5th multiplier (CF5), be connected in the 9th data interlock device (SS9) and the tenth data interlock device (SS10) afterwards;
R, the 3rd adder (A3), be connected in the 4th multiplier (CF4) and the 5th multiplier (CF5) afterwards, the 3rd adder (A3) output send again the tenth data interlock device (SS10)；
S, the 5th subtracter (JF5), be connected in the 3rd adder (A3) and the tenth data interlock device (SS10) afterwards;
T, the 6th multiplier (CF6), be connected in the 5th subtracter (JF5) and the 9th data interlock device (SS9) afterwards;
U, the 4th adder (A4), be connected in the 6th multiplier (CF6) and the 3rd multiplier (CF3) afterwards;
V, slender acanthopanax musical instruments used in a Buddhist or Taoist mass (A5), be connected in the 4th adder (A4) and the 11 data interlock device (SS11) afterwards;
W, digital to analog converter (DAC), slender acanthopanax musical instruments used in a Buddhist or Taoist mass (A5) output send digital to analog converter (DAC) and the 11 data interlock device (SS11), digital to analog converter (DAC) is output as control action voltage signal (V3)。
2. adjuster according to claim 1, it is characterized in that: the frequency coding to duty setting signal can place the second data interlock device (SS2) in, also can as the coding processing mode of measured value voltage signal, will set value voltage signal (V2) through the second voltage-frequency converter (VFC2) and the second counter (JS2) send into the second data interlock device (SS2) consist of.
3. according to claim 1. described adjuster is characterized in that: each data interlock device (SS1～SS
11) can consist of with latch or register or trigger.
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| CN94108685A CN1035695C (en) | 1994-09-10 | 1994-09-10 | Digital Neural Network High Speed Incomplete Differential Proportional Integral Differential Regulator |
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| CN94108685A CN1035695C (en) | 1994-09-10 | 1994-09-10 | Digital Neural Network High Speed Incomplete Differential Proportional Integral Differential Regulator |
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| CN1035695C true CN1035695C (en) | 1997-08-20 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SU824139A1 (en) * | 1979-06-04 | 1981-04-23 | Серпуховское Высшее Военное Командноеучилище Им. Ленинского Комсомола | Discrete sele-adjusting system |
| SU970319A1 (en) * | 1981-04-06 | 1982-10-30 | Предприятие П/Я В-8296 | Digital control system |
| SU1180842A1 (en) * | 1984-01-06 | 1985-09-23 | Предприятие П/Я Г-4152 | Digital self-adjusting system with combined control |
| SU1439531A1 (en) * | 1986-06-20 | 1988-11-23 | Таганрогский радиотехнический институт им.В.Д.Калмыкова | Digital control system |
| US4794313A (en) * | 1987-07-21 | 1988-12-27 | Ohmen Douglass J | Three element digital control system |
| US5130921A (en) * | 1987-06-12 | 1992-07-14 | Bts Broadcast Television Systems Gmbh | Digital controller for scanned actual condition signals |
| RU1793428C (en) * | 1989-12-11 | 1993-02-07 | Научно-Производственное Объединение "Метрология" | Device for selection of optimal action on investigated object |
-
1994
- 1994-09-10 CN CN94108685A patent/CN1035695C/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SU824139A1 (en) * | 1979-06-04 | 1981-04-23 | Серпуховское Высшее Военное Командноеучилище Им. Ленинского Комсомола | Discrete sele-adjusting system |
| SU970319A1 (en) * | 1981-04-06 | 1982-10-30 | Предприятие П/Я В-8296 | Digital control system |
| SU1180842A1 (en) * | 1984-01-06 | 1985-09-23 | Предприятие П/Я Г-4152 | Digital self-adjusting system with combined control |
| SU1439531A1 (en) * | 1986-06-20 | 1988-11-23 | Таганрогский радиотехнический институт им.В.Д.Калмыкова | Digital control system |
| US5130921A (en) * | 1987-06-12 | 1992-07-14 | Bts Broadcast Television Systems Gmbh | Digital controller for scanned actual condition signals |
| US4794313A (en) * | 1987-07-21 | 1988-12-27 | Ohmen Douglass J | Three element digital control system |
| RU1793428C (en) * | 1989-12-11 | 1993-02-07 | Научно-Производственное Объединение "Метрология" | Device for selection of optimal action on investigated object |
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| CN1108398A (en) | 1995-09-13 |
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