CN110838479A - Test structure, failure analysis positioning method and failure analysis method - Google Patents
Test structure, failure analysis positioning method and failure analysis method Download PDFInfo
- Publication number
- CN110838479A CN110838479A CN201911183955.4A CN201911183955A CN110838479A CN 110838479 A CN110838479 A CN 110838479A CN 201911183955 A CN201911183955 A CN 201911183955A CN 110838479 A CN110838479 A CN 110838479A
- Authority
- CN
- China
- Prior art keywords
- comb
- test
- short
- shaped
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/265—Contactless testing
- G01R31/2653—Contactless testing using electron beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a test structure which comprises a snake-shaped metal wire and two test comb-shaped structures which are oppositely arranged in a staggered mode, wherein each test comb-shaped structure is divided into at least two sub comb-shaped structures, an interval is formed between every two adjacent sub comb-shaped structures in each test comb-shaped structure, and a bonding pad is led out of at least one turning position of the snake-shaped metal wire at least one interval in each test comb-shaped structure. The test structure is divided into a plurality of small-area test structures by the method, so that the problem that the EBIRCH cannot be positioned to a short-circuit point of nA-level leakage of the super-large-area structure can be solved; meanwhile, by combining a resistance ratio method, the EBIRCH can be easily positioned to a short-circuit point of nA-level leakage of an ultra-large area structure, so that the root cause of failure can be found, and great help can be provided for solving the process problem and promoting the research and development progress.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a test structure, a failure analysis positioning method and a failure analysis method.
Background
The semiconductor manufacturing process is divided into a front-stage device process and a rear-stage metal interconnection process, and the rear-stage metal interconnection layer is used for leading out the front-stage device for testing or working. During semiconductor manufacturing, the back-end metal interconnection lines often suffer from short-circuit failures or open-circuit failures, which are mainly due to design problems and process problems. In order to evaluate the stability of the design structure and the on-line process, a complex product structure is extracted independently or is recombined into a repetitive, large-area and convenient-to-Test structure by taking the structure as a unit, a large number of corresponding electrical parameters are obtained through electrical tests on the Test structures, and the electrical parameters are analyzed to find problems in advance and solve the problems, wherein the structure is called a Test-key (Test-key). The test structure is distributed almost at all levels in the manufacturing process, has various structures, and has the characteristics of easy test and failure analysis.
The existing snake-shaped and comb-shaped combined test structure for monitoring the metal short circuit judges whether the metal short circuit problem occurs or not by testing whether current passes between a snake-shaped metal wire and a comb-shaped metal wire or not. If the metal short circuit problem occurs, a short circuit point needs to be found through a failure analysis means and the root cause of the metal short circuit needs to be deduced. The failure analysis is divided into electrical analysis and physical analysis, for the problem of metal short circuit, the electrical analysis is taken as an entry point, a professional electrical failure positioning device is used for positioning a failure point, then the physical analysis is used for determining the physical performance of the metal short circuit, and finally the root cause of the failure is deduced, wherein the positioning of the failure point is a very critical step.
At present, OBIRCH (photoinduced resistance value change technology), Thermal (Thermal emission microscope technology) and EBIRCH (electrogenerated resistance value change technology) are commonly used as metal short circuit failure positioning means in the semiconductor industry. Wherein, OBIRCH's theory of operation does: scanning the surface of the device by using a laser beam under constant voltage or constant current, inducing resistance change by using the laser, and detecting the change amount of the current or voltage value of an induced point to locate the position of the defect. It is generally applied to short circuit, void in interconnection of wiring and through hole, silicon deposition in metal and other defects. The OBIRCH can locate the short circuit defect of the back-end metal interconnection layer, but not only emphasize the short circuit position, but also emphasize a long hot point line containing the short circuit position. The working principle of Thermal is as follows: and the fault point is positioned by the medium infrared sensor receiving the heat radiation abnormity generated by the fault point. The method is generally applied to microampere (muA) level leakage, low impedance short circuit, ESD breakdown, latch-up failure and metal layer bottom short circuit. Thermal can locate the defects of the front section and the rear section, but the heat released by the leakage position reaches the level of dozens or even hundreds of microwatts (mu W), but with the advanced semiconductor process technology and the stronger and stronger process stability of the rear section, the leakage of many metal short circuit failure samples becomes very small (the level of nanoampere nA), and Thermal can not locate the short circuit of the leakage at the level of nA. In addition, the maximum magnification of OBIRCH and Thermal is only 100 times, and the positioning accuracy of the failure point of the test structure with large area and densely arranged metal wires is not high. The working principle of the EBIRCH is as follows: scanning the surface of the device by using an electron beam under constant voltage, inducing resistance change by using the electron beam, and detecting the variation of the current value of the induced point to locate the defect position. Typically for short circuits. The EBIRCH perfectly makes up the defects of the OBIRCH and Thermal, and the electric resistance value changing technology is a high-order function of a new generation Nano-Prober (Nano-scale probe measurement) machine, is provided with an electron microscope, has high magnification (the highest magnification can reach tens of thousands of times), has high positioning accuracy and can position nA-level short circuit.
But in subsequent tests it was found that for very large area serpentine comb test structures (area S > 1 × 10)5μm2) The EBIRCH is not effective in locating the short circuit point.
Disclosure of Invention
The invention aims to provide a test structure to solve the problem that the electroresistance value change technology cannot locate the short-circuit point of nA-level leakage of a super-large-area structure.
The invention further aims to provide a failure analysis positioning method, so that the short-circuit point of nA-level leakage of a super-large area structure can be easily positioned by using an electroresistance value change technology.
In order to solve the technical problem, the invention provides a test structure, which comprises a snakelike metal wire and two test comb-shaped structures which are oppositely and alternately arranged, wherein each test comb-shaped structure comprises at least two sub comb-shaped structures which are arranged side by side, each sub comb-shaped structure comprises a plurality of finger-shaped structures which are parallel to each other and a handle part which connects one end of each finger-shaped structure at the same side together, and the shanks of all sub-comb structures in each of the test comb structures are connected together using leads, the serpentine metal wire is positioned between the finger-shaped structures which are mutually interpenetrated, is positioned on the same plane with all the finger-shaped structures and is not contacted with each other, an interval is arranged between every two adjacent sub-comb-shaped structures in each test comb-shaped structure, and a bonding pad is led out from at least one turning part of the snake-shaped metal wire at least one interval in each test comb-shaped structure.
Optionally, in the test structure, one pad is disposed between each two adjacent handles in each test comb structure.
Optionally, in the test structure, all sub-comb structures in each test comb structure are the same.
To achieve the above and other related objects, the present invention further provides a failure analysis positioning method, including:
providing a sample having the test structure described above;
obtaining a corresponding resistance ratio value by using two ends of a snake-shaped metal wire in the test structure and one end of a lead of the test comb-shaped structure in the test structure, and positioning an area where a short-circuit point is located according to the resistance ratio;
and connecting corresponding voltage to pads led out from corresponding turning positions of the leads of the sub-comb-shaped structures in the area and the snake-shaped metal wire, scanning the area by using electron beams, so that the resistance of the corresponding induction points of the short circuit in the area is changed, the circuit is changed due to the resistance change, and the short circuit points are accurately positioned according to the result of the current change value of the induction points.
Optionally, in the failure analysis positioning method, the step of positioning the area where the short-circuit point is located according to the resistance ratio includes:
measuring the resistance R between the two ends A, B of the serpentine wireABA resistance R between the A end of the serpentine metal line and the C end of the lead of the test comb structureACAnd a resistance R between the B end of the serpentine metal line and the C end of the lead lineBC；
Set RAB＝R1+R2，RAC＝R1+R3，RBCR2+ R3, and based on the measured resistance RAB、RACAnd RBCThe value of the resistance ratio R1/R2 is calculated, wherein R1 is the resistance from the A terminal to the short-circuit point, R2 is the resistance from the B terminal to the short-circuit point, and R3 is the resistance of the short-circuit point;
according to the value of the resistance ratio R1/R2, the area where the short-circuit point is located.
Optionally, in the failure analysis positioning method, after the area where the short-circuit point is located, an ion beam of an FIB machine is used to scan and bombard the lead of the sub-comb-shaped structure in the area and the pad led out from the bent portion of the serpentine metal line, so that the metal layer of the pad is exposed, and an FIB sample is obtained.
Optionally, in the failure analysis positioning method, a Nano-Prober stage is used to apply corresponding voltages to the lead and the pad in the area in the FIB sample, and an electron beam is scanned over the area to change the corresponding resistance in the FIB sample.
Optionally, in the failure analysis positioning method, the step of accurately positioning the short-circuit point includes:
placing the FIB sample in the Nano-Prober stage;
respectively connecting the bonding pad in the area where the short circuit point of the FIB sample is positioned with positive bias voltage through two nanometer probes of the Nano-Prober machine table, and grounding the lead of the sub-comb structure;
and after setting relevant parameters of the EBIRCH function, observing whether a bright spot appears in a test picture on a display screen of the Nano-Prober machine, wherein the position of the bright spot is the position of the short circuit point.
To achieve the above and other related objects, the present invention further provides a failure analysis method, including:
positioning a short-circuit point in the test structure by adopting the failure analysis positioning method;
inspecting the defects at the positions of the short-circuit points through an SEM (scanning electron microscope);
TEM samples were prepared and failure mechanisms leading to shorts were determined by TEM.
Optionally, in the failure analysis method, the TEM sample is prepared by a FIB machine.
In summary, the present invention provides a test structure, which includes a serpentine metal line and two test comb structures disposed in an interlaced manner, each test comb structure includes at least two sub-comb structures disposed side by side, a space is provided between two adjacent sub-comb structures in each test comb structure, and a pad is led out from at least one corner of the serpentine metal line at least one space in each test comb structure. The test structure is divided into a plurality of small-area test structures by the method, so that the problem that the short circuit point of nA-level leakage of a super-large-area structure cannot be positioned by the resistance value variation technology can be solved; meanwhile, by combining a resistance ratio method, the EBIRCH can be easily positioned to a short-circuit point of nA-level leakage of an ultra-large area structure, so that the root cause of failure can be found, and great help can be provided for solving the process problem and promoting the research and development progress.
Drawings
FIG. 1 is a schematic structural diagram of a serpentine comb test structure;
FIG. 2 is a schematic diagram of a short circuit failure electrical test structure of the test structure of FIG. 1;
FIG. 3 shows the result of EBIRCH positioning nA-level short circuit;
FIG. 4 is a graph of the relationship between EBIRCH positioning capability and test structure area and resistance;
FIG. 5 is a schematic structural diagram of a test structure according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of a test structure in an embodiment of the invention;
FIG. 7 is an equivalent circuit diagram of a test structure according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of an EBIRCH accurate positioning short-circuit point according to an embodiment of the present invention;
in fig. 1 to 4:
01-snake-shaped metal wire, 0201-finger-shaped structure, 0202-handle part, 03-short circuit point, a-short circuit point with successful positioning and b-short circuit point with failed positioning;
in fig. 5 to 8:
1-test structure, 10-serpentine metal line, 201-sub-comb structure, 202-lead, 2011-finger structure, 2012-handle, 30-pad, 40-short, 50-nanoprobe.
Detailed Description
The conventional snake-shaped and comb-shaped combined test structure for monitoring metal short circuit is shown in fig. 1, the test structure comprises a snake-shaped metal wire 01 and two test comb-shaped structures which are arranged oppositely and alternately, each test comb-shaped structure comprises a plurality of finger-shaped structures 0201 which are parallel to each other and a handle portion 0202 which connects one end of each finger-shaped structure 0201 at the same side, and the snake-shaped metal wire 01 is positioned between the finger-shaped structures 0201 which are mutually interpenetrated, is positioned on the same plane with all the finger-shaped structures 0201 and is not in contact with each other.
Whether a metal short circuit problem occurs is judged by testing whether current passes between the snake-shaped metal wire 01 and the comb-shaped structure. If the metal short circuit problem occurs, as shown in fig. 2, a failure analysis means is required to find the short circuit point and deduce the root cause of the metal short circuit. The failure analysis is divided into electrical analysis and physical analysis, for the problem of metal short circuit, the electrical analysis is taken as an entry point, a professional electrical failure positioning device is used for positioning a failure point, then the physical analysis is used for determining the physical performance of the metal short circuit, and finally the root cause of the failure is deduced, wherein the positioning of the failure point is a very critical step.
The common metal short failure positioning means in the semiconductor industry at present are OBIRCH, Thermal and EBIRCH technologies. The OBIRCH can locate the short circuit defect of the back-end metal interconnection layer, but not only emphasize the short circuit position, but also emphasize a long hot point line containing the short circuit position. Thermal can locate the defects of the front section and the rear section, but the heat released by the leakage position reaches the level of dozens or even hundreds of μ W (microwatts), but as the semiconductor process technology is advanced, the stability of the rear section process is stronger, the leakage of many metal short circuit failure samples becomes very small (nA level), and Thermal can not locate the short circuit of the leakage at the nA level. The disadvantage of the OBIRCH and Thermal is perfectly compensated by the electroresistance value variation technology, the EBIRCH (electroresistance value variation) technology is a high-order function possessed by a new generation Nano-Prober machine, and is equipped with an electron microscope, has high magnification (up to tens of thousands of times), high positioning accuracy and can position short circuit at the nA level, and referring to fig. 3, the short circuit point 03 of the test structure in the drawing can be accurately positioned by the electroresistance value variation technology. But in subsequent tests it was found that for very large area serpentine comb test structures (area S > 1 × 10)5μm2) The short circuit fails, and the short circuit point 03 cannot be effectively positioned by the electroresistance value change technology. As shown in FIG. 4, a represents the short circuit point with successful positioning, and b represents the short circuit point with failed positioning, it can be seen that when the area S of the test structure is shaped like a snake comb<1×105μm2When the area S of the snake-shaped comb-shaped test structure is larger than 1 multiplied by 105μm2And when the resistance R is more than 1M omega, the short circuit point cannot be effectively positioned by the resistance value variation technology.
In order to solve the problem that the electrical resistance value variation technology cannot locate the short-circuit point of the leakage at the nA level of the super-large area structure (namely, the EBIRCH technology cannot accurately locate the short-circuit point of the leakage at the nA level by using the super-large area test structure), an embodiment of the invention provides a test structure, and the problem that the electrical resistance value variation technology cannot locate the short-circuit point of the leakage at the nA level of the super-large area structure is solved by a method of dividing the super-large area test structure into a plurality of small area test structures.
Referring to fig. 5, the test structure 1 includes a serpentine metal line 10 and two test comb structures disposed in an interlaced manner, each of the test comb structures includes at least two sub-comb structures 201 disposed side by side, and preferably, all the sub-comb structures 201 in each of the test comb structures are identical. Each sub-comb-shaped structure 201 comprises a plurality of finger-shaped structures 2011 which are parallel to each other and a handle 2012 which connects one end of each finger-shaped structure 2011 at the same side, the handles 2012 of all the sub-comb-shaped structures 201 in each test comb-shaped structure are connected together by a lead 202, the serpentine metal wire 10 is positioned between the finger-shaped structures 2011 which are mutually inserted and is positioned on the same plane with all the finger-shaped structures 2011 and is not contacted with each other, a space is arranged between every two adjacent sub-comb-shaped structures 201 in each test comb-shaped structure, and a bonding pad 30 is led out from at least one turning part of the serpentine metal wire 10 at least one space in each test comb-shaped structure. The number of the pads 30 is at least two, and preferably, one pad 30 is disposed between each two adjacent shanks 2012 in each test comb structure.
At least one bent portion of the serpentine metal wire 10 is spaced between every two adjacent shanks 2012, and the pad 30 is located at the bent portion of the serpentine metal wire 10 at the spaced portion.
Wherein, every two sub-comb structures 201 which are oppositely arranged and mutually interpenetrated and the serpentine metal line 10 arranged in the area where the two sub-comb structures 201 are located form a small-area test structure, and the small-area test structure can also be called a small-area serpentine comb structure. The test structure 1 is thus substantially divided into at least two small-area test structures (i.e. small-area serpentine comb structures) having an area S < 1 x 105um2。
That is, in the embodiment, the test structure 1 is divided into a plurality of small-area test structures, and when the test structure is short-circuited, the short-circuit point is positioned to the small-area test structure first, and then the small-area test structure is further operated by an electric resistance value changing technology, so that the short-circuit point of the small nA-level leakage current can be accurately positioned. Therefore, the problem that the short-circuit point of nA-level leakage of an ultra-large area structure cannot be positioned by the resistance value variation technology is solved.
The embodiment also provides a failure analysis positioning method, which comprises the following steps:
first, a sample having the test structure 1 of the present embodiment is provided;
secondly, obtaining a corresponding value of the resistance ratio by using two ends of the serpentine metal wire 10 in the test structure 1 and one end of the lead 202 connecting the handle 2012 of the test comb structure together in the test structure 1, and positioning an area where the short-circuit point 40 is located according to the resistance ratio, that is, positioning a test structure with a small area where the short-circuit point 40 is located;
then, corresponding voltage is connected to the bonding pads 30 led out from the corresponding turning positions of the leads 202 of the sub-comb-shaped structure in the area and the serpentine metal wire, and the electron beam scans the area to change the resistance of the corresponding induction points of the short circuit in the area, so that the current change is caused by the resistance change, and the short circuit point 40 is accurately positioned according to the current change value of the induction points.
Referring to fig. 6 and 7, the serpentine wire 10 may be equivalent to one copper wire connecting a and B, and the resistance of the copper wire is uniform. The step of locating the area of the short-circuit point 40 according to the resistance ratio comprises:
first, the resistance R between the two ends A, B of the serpentine wire 10 is measuredABResistance R between the A-terminal of the serpentine metal line 10 and the C-terminal of the lead 202 in the test comb structureACAnd a resistance R between the B terminal of the serpentine metal line 10 and the C terminal of the lead 202BC；
Then, set RAB＝R1+R2，RAC＝R1+R3，RBCR2+ R3, and based on the measured resistance RAB、RACAnd RBCThe resistance is calculated according to the magnitude ofThe ratio R1/R2, wherein R1 is the resistance of the terminal A to the shorting point 40, R2 is the resistance of the terminal B to the shorting point 40, R3 is the resistance of the shorting point 40, and the resistance of the terminal C to the shorting point 40 is negligible.
Then, according to the value of the resistance ratio R1/R2, the area where the short circuit point 40 is located. I.e. according to the values of R1/R2, it can be determined that the short-circuit point 40 is located at a fraction of the copper line, so that a small-area test structure can be located, where the short-circuit point 40 is located, and the small-area test structure includes two sub-comb-shaped test structures 201 which are oppositely arranged and are mutually staggered and the serpentine metal line 10 which is arranged between the two sub-comb-shaped test structures 201.
After the area where the short-circuit point 40 is located (i.e., the small-area test structure) is located, an ion beam of a FIB (focused ion beam) machine may be used to bombard the lead 202 of the sub-comb structure and the pad 30 led out from the bent portion of the serpentine metal wire in the small-area test structure where the short-circuit point 40 is located, so as to expose the metal layer thereof, thereby obtaining a FIB sample. The FIB (focused ion beam) machine is a machine which accelerates ion beams generated by an ion source through an ion gun, focuses the ion beams and then acts on the surface of a sample, can be used for generating secondary electronic signals to obtain electronic images, and uses a strong current ion beam to strip surface atoms so as to finish micro-nano surface topography processing and match chemical gas reaction in a physical sputtering mode, and selectively strips metals, silicon oxide layers or deposited metal layers.
Due to the area S of the small-area test structure<1×105μm2Thus, the shorting dots 40 can then be precisely located using an electrical resistance variation technique using a Nano-Prober (Nano-probe metrology) tool. Among them, the Nano-Prober (Nano probe measurement) machine can be used to perform Nano failure analysis on devices in the integrated circuit chip. Applying corresponding voltages to the leads 202 and the pads 30 of the sub-comb structures in the small-area test structure in the FIB sample using a Nano-Prober stage and scanning the area with an electron beam enables the FIB to be fabricatedThe corresponding resistance in the sample changes.
Referring to fig. 8, the step of accurately positioning the short-circuit point 40 by the electrical resistance value variation technology in the present embodiment specifically includes:
firstly, placing the FIB sample in the Nano-Prober machine;
then, the pad 30 in the area (i.e. small-area test structure) where the short-circuit point 40 of the FIB sample is located is forward biased through two nanoprobes 50 of the Nano-Prober machine, the lead 202 of one sub-comb structure in the area is grounded, that is, one nanoprobe 50 is connected with the metal layer of the lead 202 of one sub-comb structure in the area, the other nanoprobe 50 is connected with the metal layer of the pad 30, the pad 30 in the area where the short-circuit point 40 of the FIB sample is located is forward biased, and the lead 202 of one sub-comb structure in the area is grounded;
and then, after setting relevant parameters of the EBIRCH function, observing whether a bright spot appears in a test picture on a display screen of the Nano-Prober machine, wherein the position of the bright spot is the position of the short-circuit point 40, and accurately positioning the short-circuit point 40 of the nA-level electric leakage of the test structure with a small area.
The embodiment also provides a failure analysis method, which comprises the following steps:
firstly, positioning a short-circuit point 40 of a test structure by adopting the failure analysis positioning method described in the embodiment;
then, examining the defect appearance of the position of the short circuit point 40 through an SEM (scanning electron microscope);
TEM samples were prepared and failure mechanisms leading to shorting were determined by TEM (transmission electron microscopy).
After recording the position of the short-circuit point 40, firstly checking the appearance of the position of the short-circuit point 40 by adopting an SEM, preparing a TEM sample by using an FIB machine after finding a defect, and determining a failure mechanism causing metal short circuit by using the TEM.
According to the invention, by designing a test structure and combining a resistance ratio method, the EBIRCH can be easily positioned to a short-circuit point of nA-level leakage of an ultra-large area structure, so that the root cause of failure is found, and great help is provided for solving the process problem and promoting the research and development progress.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. That is, all equivalent changes and modifications made according to the content of the claims of the present invention should be within the technical scope of the present invention.
Claims (10)
1. A test structure is characterized by comprising a snake-shaped metal wire and two test comb-shaped structures which are oppositely and alternately arranged, each test comb-shaped structure comprises at least two sub comb-shaped structures which are arranged side by side, each sub comb-shaped structure comprises a plurality of finger-shaped structures which are parallel to each other and a handle part which connects one end of the same side of each finger-shaped structure together, and the shanks of all sub-comb structures in each of the test comb structures are connected together using leads, the serpentine metal wire is positioned between the finger-shaped structures which are mutually interpenetrated, is positioned on the same plane with all the finger-shaped structures and is not contacted with each other, an interval is arranged between every two adjacent sub-comb-shaped structures in each test comb-shaped structure, and a bonding pad is led out from at least one turning part of the snake-shaped metal wire at least one interval in each test comb-shaped structure.
2. The test structure of claim 1, wherein one of the pads is disposed between each two adjacent of the handles in each of the test comb structures.
3. The test structure of claim 1, wherein all sub-comb structures in each of the test comb structures are identical.
4. A failure analysis positioning method is characterized by comprising the following steps:
providing a sample having a test structure according to any one of claims 1 to 3;
obtaining a corresponding resistance ratio value by using two ends of a snake-shaped metal wire in the test structure and one end of a lead of the test comb-shaped structure in the test structure, and positioning an area where a short-circuit point is located according to the resistance ratio;
and connecting corresponding voltage to pads led out from corresponding turning positions of the leads of the sub-comb-shaped structures in the area and the snake-shaped metal wire, scanning the area by using electron beams, so that the resistance of a corresponding induction point of the short circuit in the area is changed, the current change is caused by the resistance change, and the short circuit point is accurately positioned according to the current change value of the induction point.
5. The failure analysis locating method according to claim 4, wherein the step of locating the area where the short-circuit point is located according to the resistance ratio comprises:
measuring the resistance R between the two ends A, B of the serpentine wireABA resistance R between the A end of the serpentine metal line and the C end of the lead of the test comb structureACAnd a resistance R between the B end of the serpentine metal line and the C end of the lead lineBC；
Set RAB＝R1+R2，RAC＝R1+R3，RBCR2+ R3, and based on the measured resistance RAB、RACAnd RBCThe value of the resistance ratio R1/R2 is calculated, wherein R1 is the resistance from the A terminal to the short-circuit point, R2 is the resistance from the B terminal to the short-circuit point, and R3 is the resistance of the short-circuit point;
according to the value of the resistance ratio R1/R2, the area where the short-circuit point is located.
6. The failure analysis positioning method according to claim 4, wherein after the area where the short-circuit point is located, an ion beam of an FIB machine is used for bombarding the bonding pads led out from the bending parts of the leads of the sub-comb-shaped structure and the snake-shaped metal wire in the area, so that the metal layers of the bonding pads are exposed, and an FIB sample is obtained.
7. The failure analysis localization method of claim 6, wherein the leads and pads in the area in the FIB sample are connected to respective voltages using a Nano-Prober stage, and the area is scanned using an electron beam to cause a corresponding resistance change in the FIB sample.
8. The failure analysis locating method of claim 6, wherein the step of accurately locating the short circuit point comprises:
placing the FIB sample in the Nano-Prober stage;
respectively connecting the bonding pad in the area where the short circuit point of the FIB sample is positioned with positive bias voltage through two nanometer probes of the Nano-Prober machine table, and grounding the lead of the sub-comb structure;
and after setting relevant parameters of the EBIRCH function, observing whether a bright spot appears in a test picture on a display screen of the Nano-Prober machine, wherein the position of the bright spot is the position of the short circuit point.
9. A method of failure analysis, comprising:
locating a short-circuit point in the test structure by using the failure analysis locating method as claimed in any one of claims 4 to 8;
inspecting the defects at the positions of the short-circuit points through an SEM (scanning electron microscope);
TEM samples were prepared and failure mechanisms leading to shorts were determined by TEM.
10. The failure analysis method of claim 9, wherein the TEM sample is prepared by a FIB bench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911183955.4A CN110838479B (en) | 2019-11-27 | 2019-11-27 | Test structure, failure analysis positioning method and failure analysis method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911183955.4A CN110838479B (en) | 2019-11-27 | 2019-11-27 | Test structure, failure analysis positioning method and failure analysis method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110838479A true CN110838479A (en) | 2020-02-25 |
| CN110838479B CN110838479B (en) | 2021-07-16 |
Family
ID=69577502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911183955.4A Active CN110838479B (en) | 2019-11-27 | 2019-11-27 | Test structure, failure analysis positioning method and failure analysis method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110838479B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111239590A (en) * | 2020-02-24 | 2020-06-05 | 珠海格力电器股份有限公司 | Method and device for positioning electrostatic damage of chip |
| CN112103202A (en) * | 2020-11-10 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN112269045A (en) * | 2020-10-12 | 2021-01-26 | 上海华力集成电路制造有限公司 | Test structure for failure analysis |
| CN113092978A (en) * | 2021-04-06 | 2021-07-09 | 苏州通富超威半导体有限公司 | Testing component and testing method for short circuit failure positioning of electronic component |
| CN114236364A (en) * | 2022-02-24 | 2022-03-25 | 上海聚跃检测技术有限公司 | Failure analysis method and system for integrated circuit chip |
| TWI769962B (en) * | 2021-12-03 | 2022-07-01 | 新唐科技股份有限公司 | Driving apparatus and detection system for memory module failure detection, and memory device using the driving apparatus |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020063249A1 (en) * | 1999-08-16 | 2002-05-30 | David E. Sloman | Kerf contact to silicon redesign for defect isolation and analysis |
| US20020089345A1 (en) * | 2001-01-05 | 2002-07-11 | Yih-Yuh Doong | Method and device for semiconductor wafer testing |
| CN102386167A (en) * | 2010-09-03 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Structure of semiconductor device |
| CN105097583A (en) * | 2014-05-09 | 2015-11-25 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure failure analysis method |
| CN109490758A (en) * | 2018-12-12 | 2019-03-19 | 上海华力集成电路制造有限公司 | A kind of localization method of short-circuit failure |
-
2019
- 2019-11-27 CN CN201911183955.4A patent/CN110838479B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020063249A1 (en) * | 1999-08-16 | 2002-05-30 | David E. Sloman | Kerf contact to silicon redesign for defect isolation and analysis |
| US20020089345A1 (en) * | 2001-01-05 | 2002-07-11 | Yih-Yuh Doong | Method and device for semiconductor wafer testing |
| CN102386167A (en) * | 2010-09-03 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Structure of semiconductor device |
| CN105097583A (en) * | 2014-05-09 | 2015-11-25 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure failure analysis method |
| CN109490758A (en) * | 2018-12-12 | 2019-03-19 | 上海华力集成电路制造有限公司 | A kind of localization method of short-circuit failure |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111239590A (en) * | 2020-02-24 | 2020-06-05 | 珠海格力电器股份有限公司 | Method and device for positioning electrostatic damage of chip |
| CN112269045A (en) * | 2020-10-12 | 2021-01-26 | 上海华力集成电路制造有限公司 | Test structure for failure analysis |
| CN112269045B (en) * | 2020-10-12 | 2024-06-07 | 上海华力集成电路制造有限公司 | Test structure for failure analysis |
| CN112103202A (en) * | 2020-11-10 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN112103202B (en) * | 2020-11-10 | 2021-02-12 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN113092978A (en) * | 2021-04-06 | 2021-07-09 | 苏州通富超威半导体有限公司 | Testing component and testing method for short circuit failure positioning of electronic component |
| TWI769962B (en) * | 2021-12-03 | 2022-07-01 | 新唐科技股份有限公司 | Driving apparatus and detection system for memory module failure detection, and memory device using the driving apparatus |
| CN114236364A (en) * | 2022-02-24 | 2022-03-25 | 上海聚跃检测技术有限公司 | Failure analysis method and system for integrated circuit chip |
| CN114236364B (en) * | 2022-02-24 | 2022-05-31 | 上海聚跃检测技术有限公司 | Failure analysis method and system for integrated circuit chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110838479B (en) | 2021-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110838479B (en) | Test structure, failure analysis positioning method and failure analysis method | |
| US6445199B1 (en) | Methods and apparatus for generating spatially resolved voltage contrast maps of semiconductor test structures | |
| US7655482B2 (en) | Chemical mechanical polishing test structures and methods for inspecting the same | |
| US6528818B1 (en) | Test structures and methods for inspection of semiconductor integrated circuits | |
| US6636064B1 (en) | Dual probe test structures for semiconductor integrated circuits | |
| US20020187582A1 (en) | Inspectable buried test structures and methods for inspecting the same | |
| US11709199B2 (en) | Evaluation apparatus for semiconductor device | |
| US7179661B1 (en) | Chemical mechanical polishing test structures and methods for inspecting the same | |
| JP2011215112A (en) | Multi-probe afm nanoprober and measurement method using the same | |
| JP3776902B2 (en) | Substrate inspection apparatus, substrate inspection method, program, and semiconductor device manufacturing method | |
| JP4090657B2 (en) | Probe device | |
| JP3955445B2 (en) | Semiconductor device inspection method and sample inspection apparatus | |
| US7715997B2 (en) | Intelligent inspection based on test chip probe failure maps | |
| Sikul et al. | SEM-based nanoprobing on in-situ delayered advanced 10 nm technology node IC | |
| JPH04305954A (en) | Apparatus and method for testing manufacturing process | |
| US11391756B2 (en) | Probe module and probe | |
| Huat et al. | Physical fault isolation of complex BEOL defects in advanced microprocessors using EBAC technique in nano-prober | |
| JP4290316B2 (en) | Inspection method and inspection device for wiring short-circuited portion | |
| US11977099B2 (en) | Method for manufacturing semiconductor device | |
| JP4901154B2 (en) | Semiconductor device inspection method and inspection device, and semiconductor device manufacturing method | |
| CN111081682B (en) | Semiconductor test structure and test method | |
| US20040017212A1 (en) | Apparatus and method for enhanced voltage contrast analysis | |
| JP2005347773A5 (en) | ||
| US4745360A (en) | Electron-beam probe system utilizing test device having interdigitated conductive pattern and associated method of using the test device | |
| EP0498007A1 (en) | Method and apparatus for contactless testing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |