CN110828321A - Large-board fan-out type system integration packaging structure and method thereof - Google Patents

Large-board fan-out type system integration packaging structure and method thereof Download PDF

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Publication number
CN110828321A
CN110828321A CN201910941935.2A CN201910941935A CN110828321A CN 110828321 A CN110828321 A CN 110828321A CN 201910941935 A CN201910941935 A CN 201910941935A CN 110828321 A CN110828321 A CN 110828321A
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chip
packaging
fan
layer
large board
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崔成强
匡自亮
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Guangdong Xinhua Microelectronics Technology Co Ltd
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Guangdong Xinhua Microelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The invention provides a large-board fan-out type system integrated packaging structure and a method thereof.A board-level system-level fan-out package is characterized in that a fine circuit is prepared by utilizing a semi-additive method, a plurality of chips with different functions and packaged units are manufactured according to a single-chip fan-out process, and the plurality of chips with different functions and the packaged units are subjected to system-level packaging to form a micro-electromechanical system; the technical scheme integrates a fan-out packaging technology and a system-in-package technology, and can package a plurality of chips with different functions and packaged units in the same package, so that the miniaturization of semiconductor packaging is realized, and the density of components on a semiconductor is increased; the technical scheme adopts a large-board fan-out type packaging process to prepare the SiP packaging module, is different from the traditional SiP packaging process, does not have a packaging substrate, can greatly reduce the thickness of the whole packaging structure and reduce the production cost of the packaging structure; according to the technical scheme, more independent packaging bodies can be manufactured at the same time, and the production efficiency is effectively improved.

Description

Large-board fan-out type system integration packaging structure and method thereof
Technical Field
The invention relates to the field of board Level System In Package (Panel Level System In Package) fan-out packaging, In particular to a large-board fan-out type System integrated packaging structure and a method thereof.
Background
Since the 60's of the last century, the development of semiconductor technology has followed moore's law. However, as the width of gate circuits in a chip is reduced below 14nm, semiconductor technology is approaching the limits of silicon technology, thereby incurring new development costs and equipment and facilities for upgrading wafer fabrication, making the provision of such costs for semiconductor device fabrication very expensive. The development direction of future products is high-density integration and volume miniaturization, and the improvement of product performance in the post-mole era is a technical breakthrough depending on advanced packaging, and board-level fan-out type packaging is one of the representatives. How to apply board-level system-in-fan-out package to realize a plurality of chips with different functions and packaged units together is a problem to be solved urgently.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
The invention aims to solve the defects of the prior art, combines the advantages of fan-out type packaging and system-in-package, and provides a large-board fan-out type system integrated packaging structure and a method thereof.
The technical scheme of the invention is as follows: a large board fan-out type system integration packaging method is disclosed, wherein chips with different functions and packaged units are packaged together on a large board surface, and the method belongs to board-level system-level packaging and specifically comprises the following steps:
adhering the chip on the large plate surface in a face up or face down mounting mode and the packaged unit;
performing injection molding on the chip and the packaged unit, and wrapping the chip and the packaged unit by using an injection molding material;
removing the large plate surface from the injection-molded chip and the packaged unit, and cleaning the sticking surfaces of the chip and the packaged unit and the large plate surface;
adhering a dielectric layer on the I/O of the chip;
punching a dielectric layer above the chip salient points to expose the chip salient points;
forming a metal seed layer on the dielectric layer and the chip salient points;
laminating a layer of dry film on the surface of the metal seed layer and carrying out corresponding treatment at the position where a subsequent circuit is not required to be formed to form a metal circuit layer;
removing the film from the dry film and removing the redundant metal seed layer;
and coating solder resist ink on the surfaces of the dielectric layer and the metal circuit layer, and then planting balls on the solder resist ink to obtain a chip and a packaged unit integrated package body.
The large board fan-out type system integration packaging method is characterized in that the size of the large board surface is 300mm multiplied by 300 mm-1000 mm multiplied by 1000mm, and the thickness is 0.3 mm-1 mm.
The large board fan-out type system integration packaging method is characterized in that a chip and a packaged unit are pasted on a large board surface through temporary bonding glue.
The large-board fan-out type system integration packaging method is characterized in that a metal seed layer is formed on a dielectric layer and a chip bump in an electroplating, chemical plating and PVD (physical vapor deposition) sputtering mode.
According to the large-board fan-out type system integration packaging method, a layer of dry film is laminated on the surface of the metal seed layer, exposure and development, pattern electroplating or PVD (physical vapor deposition) sputtering are carried out at the position where a subsequent circuit does not need to be formed, and a metal circuit layer is formed.
A large board fan-out type system integrated packaging structure is manufactured by adopting the large board fan-out type system integrated packaging method, and comprises a chip and a packaged unit which are wrapped together through injection molding materials, a dielectric layer is arranged above I/O of the chip, salient points of the chip are exposed relative to the dielectric layer, a metal seed layer is arranged on the dielectric layer and the salient points of the chip, a metal circuit layer is arranged on the metal seed layer, a solder resist ink layer is coated on the surfaces of the dielectric layer and the metal circuit layer, and balls are planted on the solder resist ink layer.
The large-board fan-out type system integrated package structure is characterized in that the number of the chips is set according to actual needs; the chip includes but is not limited to a digital chip, a passive component, and a power management chip.
The large-board fan-out type system integrated packaging structure is characterized in that the I/O number of each chip with different functions does not exceed 300.
The large board fan-out type system integrated packaging structure is characterized in that the packaged unit is an independent device and an independent packaging functional module.
The large-board fan-out type system integrated packaging structure is characterized in that the number of packaged units is set according to actual needs; the packaged units include, but are not limited to, radio frequency units, filters.
The invention has the beneficial effects that: the invention provides a large-board fan-out type system integrated packaging structure and a method thereof, wherein board-level system-level fan-out packaging is to prepare a fine circuit by using a semi-additive method, manufacture a plurality of chips with different functions and packaged units according to a single-chip fan-out process, and carry out system-level packaging on the chips with different functions and the packaged units to form a Micro Electro Mechanical System (MEMS); the technical scheme integrates a fan-out packaging technology and a system-in-package technology, and can package a plurality of chips with different functions and packaged units in the same package, so that the miniaturization of semiconductor packaging is realized, and the density of components on a semiconductor is increased; the technical scheme adopts a large-board fan-out type packaging process to prepare the SiP packaging module, is different from the traditional SiP packaging process, does not have a packaging substrate, can greatly reduce the thickness of the whole packaging structure and reduce the production cost of the packaging structure; according to the technical scheme, more independent packaging bodies can be manufactured at the same time, and the production efficiency is effectively improved.
Drawings
FIG. 1 is a flow chart of steps of a method for packaging a large board fan-out system integration according to the present invention.
Fig. 2 is a schematic view of the present invention with a chip and packaged units attached to a large board surface.
FIG. 3 is a flow chart of a large board fan-out system integrated packaging method when the chips are attached in a face up mounting manner according to the present invention.
FIG. 4 is a flow chart of a large-board fan-out system integrated packaging method when the chip is pasted in a face down mounting manner according to the present invention.
FIG. 5 is a schematic structural diagram of a large board fan-out system in package according to the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
As shown in fig. 1 to 4, a large board fan-out type system integrated packaging method packages chips 31 with different functions and packaged units 32 together on a large board surface 1, belongs to board-level system-level packaging, and specifically includes the following steps:
step S1: adhering the chip 31 and the packaged unit 32 on the large board surface 1 in a face up or face down mounting mode;
step S2: the chip 31 and the packaged unit 32 are subjected to injection molding, and the injection molding material 4 wraps the chip 31 and the packaged unit 32;
step S3: the large board surface 1 is detached from the injection molded chip 31 and the packaged unit 32, and the sticking surfaces of the chip 31 and the packaged unit 32 and the large board surface 1 are cleaned;
step S4: a dielectric layer 5 is adhered above the Input/Output (I/O) of the chip 31;
step S5: punching the dielectric layer 5 above the salient points of the chip 31 to expose the salient points of the chip;
step S6: forming a metal seed layer 6 on the dielectric layer 5 and the chip salient points;
step S7: laminating a dry film 7 on the surface of the metal seed layer 6, and performing corresponding treatment at a position where a subsequent circuit is not required to be formed to form a metal circuit layer 8;
step S8: carrying out film stripping treatment on the dry film 7, and removing the redundant metal seed layer 6;
step S9: coating solder resist ink 9 on the surfaces of the dielectric layer 5 and the metal circuit layer 8, and then planting balls 10 on the solder resist ink 9;
step S10: the whole is diced to obtain a package in which the chip 31 and the packaged unit 32 are integrated.
Wherein, the size of the large plate surface 1 is 300mm multiplied by 300 mm-1000 mm multiplied by 1000mm, and the thickness is 0.3 mm-1 mm.
The number of the chips 31 is set according to actual requirements according to the requirements of an integrated package, and may be one, two or more; chips 31 with different functions, such as digital chips, passive components, power management chips, etc., can be selected for packaging according to actual needs.
Wherein, the I/O number of each chip 31 with different functions does not exceed 300.
The packaged unit 32 is an independent device, an independent packaging functional module (that is, the packaged unit 32 can be taken out and applied to other places), and is packaged with a plurality of chips 31 with different functions in a combined manner, belonging to board-level system-level packaging.
The number of the packaged units 32 is set according to actual requirements, and may be one, two or more; different packaged units 32 can be selected for packaging according to actual needs, such as radio frequency units, filters, and the like.
In order to facilitate the subsequent separation of the large board surface 1 from the chip 31 and the packaged unit 32, in step S1, the chip 31 and the packaged unit 32 are adhered to the large board surface 1 by the temporary bonding adhesive 2.
As shown in fig. 3, when the chip 31 is attached to the large board surface 1 in a face up mounting manner, after the injection molding process is performed on the chip 31 and the packaged unit 32, a certain amount of plastic molding material needs to be ground to expose the chip bumps from the chip 31, and then the temporary bonding adhesive 2 and the large board surface 1 of the carrier board below are removed. As shown in fig. 4, when the chip 31 is attached to the large board surface 1 in a face down mounting manner, after the injection molding process is performed on the chip 31 and the packaged unit 32, the large board surface 1 may be directly removed from the injection-molded chip 31 and the packaged unit 32.
In step S2, the chip 31 and the packaged unit 32 are injection molded with an EMC material (the EMC material refers to an epoxy injection molding compound).
In step S3, the bonding surfaces of the chip 31 and the packaged unit 32 and the large board surface 1 are cleaned by plasma cleaning.
The dielectric layer 5 is made of ABF (Ajinomoto Build-up Film) resin, BT (BismaleimidIreacine) resin and other materials, and the thickness of the dielectric layer is 9-20 mu m.
In step S5, the dielectric layer 5 above the bumps of the chip 31 is punched by laser to expose the bumps of the chip.
In step S6, a metal seed layer 6 is formed on the dielectric layer 5 and the bumps of the chip 31 by electroplating, electroless plating, PVD sputtering, or the like. The metal seed layer 6 is a metal seed layer 6 of Cu, Ti, Ag, Au and the like, and the thickness is 5-15 mu m.
In step S7, a layer of dry film 7 is laminated on the surface of the metal seed layer 6, and exposure development, pattern plating or PVD sputtering (PVD sputtering, i.e., magnetron sputtering) is performed at a position where a subsequent circuit is not required to be formed, so as to form the metal circuit layer 8.
As shown in fig. 5, a large board fan-out type system integrated package structure is manufactured by the large board fan-out type system integrated package method described above, and includes a chip 31 and a packaged unit 32 wrapped together by an injection molding material 4, a dielectric layer 5 is disposed above an I/O of the chip 31, bumps of the chip 31 are exposed relative to the dielectric layer 5, a metal seed layer 6 is disposed on the bumps of the dielectric layer 5 and the chip 31, a metal circuit layer 8 is disposed on the metal seed layer 6, a solder resist ink 9 layer is coated on the surfaces of the dielectric layer 5 and the metal circuit layer 8, and balls 10 are planted on the solder resist ink 9 layer.
The following embodiments are described in terms of the above-described large board fan-out system integrated package structure and method thereof: sticking a digital chip and/or a passive component (chips 31 with different functions) and a radio frequency unit on a carrier plate (namely a large plate surface 1) through a temporary bonding adhesive 2, wherein the carrier plate adopts a steel plate with the size of 300 multiplied by 300mm and the thickness of 0.5mm, then performing injection molding on the digital chip, the passive component and the radio frequency unit, then removing the carrier plate and the temporary bonding adhesive 2, cleaning the sticking surfaces of the chip 31 and the packaged unit 32 and the large plate surface 1 by plasma, then sticking a 10 mu m dielectric layer 5 on an I/O of the chip 31, then punching the dielectric layer 5 by laser to expose a chip salient point, sputtering a 7 mu m Cu seed layer 6 (copper seed layer 6) on the dielectric layer 5 and the chip salient point by PVD, covering a dry film 7 on the surface of the Cu seed layer 6, then exposing and developing to form a Cu rewiring layer (RDL) (namely a metal circuit layer 8), and removing the dry film 7 and the redundant seed layer 6, finally coating the solder resist ink 9, carrying out ball planting 10 and cutting to obtain a single chip 31 and a packaged unit 32 integrated package body.
In the technical scheme, the board-level system-in-fan-out package is to prepare a fine circuit by using a semi-additive method, manufacture a plurality of chips 31 with different functions and packaged units 32 according to a fan-out process of a single chip 31, and perform system-in-package on the chips 31 with the different functions and the packaged units 32 to form a Micro Electro Mechanical System (MEMS). The method integrates a fan-out packaging technology and a system-in-package technology, and can package a plurality of chips 31 with different functions and packaged units 32 in the same package, so that the miniaturization of semiconductor packaging is realized, and the density of components on a semiconductor is increased; the technical scheme adopts a large-board fan-out type packaging process to prepare the SiP packaging module, is different from the traditional SiP packaging process, does not have a packaging substrate, can greatly reduce the thickness of the whole packaging structure and reduce the production cost of the packaging structure; according to the technical scheme, more independent packaging bodies can be manufactured at the same time, and the production efficiency is effectively improved.
In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.

Claims (10)

1. A large board fan-out type system integration packaging method is characterized in that chips with different functions and packaged units are packaged together on a large board surface, and belongs to board-level system-level packaging, and the method specifically comprises the following steps:
adhering the chip on the large plate surface in a face up or face down mounting mode and the packaged unit;
performing injection molding on the chip and the packaged unit, and wrapping the chip and the packaged unit by using an injection molding material;
removing the large plate surface from the injection-molded chip and the packaged unit, and cleaning the sticking surfaces of the chip and the packaged unit and the large plate surface;
adhering a dielectric layer on the I/O of the chip;
punching a dielectric layer above the chip salient points to expose the chip salient points;
forming a metal seed layer on the dielectric layer and the chip salient points;
laminating a layer of dry film on the surface of the metal seed layer and carrying out corresponding treatment at the position where a subsequent circuit is not required to be formed to form a metal circuit layer;
removing the film from the dry film and removing the redundant metal seed layer;
and coating solder resist ink on the surfaces of the dielectric layer and the metal circuit layer, and then planting balls on the solder resist ink to obtain a chip and a packaged unit integrated package body.
2. The large board fan-out system integration packaging method as claimed in claim 1, wherein the large board surface has a size of 300mm x 300mm to 1000mm x 1000mm and a thickness of 0.3mm to 1 mm.
3. The large board fan-out system integration packaging method of claim 1, wherein the chips and the packaged units are attached to the large board surface by temporary bonding glue.
4. The integrated packaging method for the large board fan-out system as claimed in claim 1, wherein a metal seed layer is formed on the dielectric layer and the chip bumps by electroplating, electroless plating or PVD sputtering.
5. The integrated packaging method of the large board fan-out type system according to claim 1, wherein a dry film is laminated on the surface of the metal seed layer, and exposure development, pattern plating or PVD sputtering is performed at a position where a subsequent circuit is not required to be formed, so as to form a metal circuit layer.
6. A large board fan-out type system integrated packaging structure is characterized by being manufactured by the large board fan-out type system integrated packaging method according to any one of claims 1 to 5, the large board fan-out type system integrated packaging structure comprises a chip and a packaged unit which are packaged together through injection molding materials, a dielectric layer is arranged above I/O of the chip, salient points of the chip are exposed relative to the dielectric layer, a metal seed layer is arranged on the dielectric layer and the salient points of the chip, a metal circuit layer is arranged on the metal seed layer, a solder resist ink layer is coated on the surfaces of the dielectric layer and the metal circuit layer, and balls are planted on the solder resist ink layer.
7. The large board fan-out system integrated package structure of claim 6, wherein the number of the chips is set according to actual needs; the chip includes but is not limited to a digital chip, a passive component, and a power management chip.
8. The large board fan-out system-in-package structure of any one of claims 6 or 7, wherein the number of I/Os per different-function chip is no more than 300.
9. The large board fan-out system in package structure of claim 6, wherein the packaged unit is a stand-alone device, stand-alone packaged functional module.
10. The large board fan-out system integrated package structure according to any one of claims 6 or 9, wherein the number of the packaged units is set according to actual needs; the packaged units include, but are not limited to, radio frequency units, filters.
CN201910941935.2A 2019-09-30 2019-09-30 Large-board fan-out type system integration packaging structure and method thereof Pending CN110828321A (en)

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