CN110808736A - Method for realizing phase shift of phase-locked loop - Google Patents
Method for realizing phase shift of phase-locked loop Download PDFInfo
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- H—ELECTRICITY
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses a method for realizing phase offset of a phase-locked loop, which relates to the field of phase adjustment of phase-locked loop circuits, and realizes the phase offset by two modes: one is to adjust the phase by precisely adjusting the variation time of the frequency dividing ratio of the phase-locked loop; the other is to adjust the phase by changing the frequency division ratio by fixing the time value for a phase-locked loop circuit capable of realizing a high-resolution fractional frequency division ratio. Both modes can realize phase shift in circuits with adjustable frequency division ratio, such as a phase-locked loop, and the like, without increasing any hardware cost, and are simple to operate, and the phase-locked loop cannot be unlocked.
Description
Technical Field
The invention relates to the field of phase adjustment of phase-locked loop circuits, in particular to a method for realizing phase offset of a phase-locked loop.
Background
In the field of communications and the like, since a communication system needs to change the phase of a signal, it is necessary to adjust the phase without interrupting the signal, and the phase adjustment results in a phase shift.
For a direct digital frequency synthesis (DDS) technology, phase debugging can be easily realized in an FPGA, and the initial phase of a signal can be accurately controlled by controlling an initial value, but for a phase-locked loop, because the phase-locked loop is a closed-loop system, the opening and closing process of a loop can be carried out in the signal switching process, so that the initial phase cannot be determined, and if accurate phase control is required, only a phase offset method can be used. As phase adjustment becomes more and more important, circuits such as phase locked loops need to be able to control phase offset precisely like digital circuits.
The conventional phase adjustment is to add a phase adjuster to the output of the pll circuit, as shown in fig. 1, which is a complicated way to control the phase and increases the cost.
Disclosure of Invention
Aiming at the problems of high cost and complex realization in the phase shift of the traditional phase-locked loop circuit, the invention provides a method for realizing the phase shift of the phase-locked loop, which controls the phase by adjusting time.
The invention adopts the following technical scheme:
a method for realizing phase offset of a phase-locked loop, for the phase-locked loop circuit of which the frequency dividing ratio of the phase-locked loop can only be changed in an integer, adjusts the phase by accurate adjusting time, and comprises the following steps:
step 1: calculating delta t, wherein the delta t is the change time of the frequency dividing ratio of the adjusted phase-locked loop, and the calculation formula of the delta t is as follows:
wherein the content of the first and second substances,
for the phase offset to be implemented, Δ N is the amount of change in the division ratio of the phase locked loop,fphthe phase demodulation frequency of the phase-locked loop;
step 2: timing is performed in the phase-locked loop circuit, and when the timing reaches delta t, the phase of the phase-locked loop circuit is shifted
Preferably, the specific process of step 2 is:
step 2.1: setting the frequency dividing ratio of a frequency divider in the phase-locked loop circuit to be N + delta N, wherein N is an initial value of the frequency dividing ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when the time reaches delta t, the frequency dividing ratio of the frequency divider in the phase-locked loop circuit is changed into N, and the phase offset of the whole phase-locked loop circuit
The second object of the present invention is to provide a method for realizing phase offset of a phase-locked loop, which controls the phase by adjusting the frequency division ratio.
A method for realizing phase offset of a phase-locked loop changes a frequency division ratio to adjust the phase of a phase-locked loop circuit which can realize a high-resolution fractional frequency division ratio, and comprises the following steps:
step 1: calculating delta N, wherein the delta N is the variation of the frequency dividing ratio of the phase-locked loop, and the calculation formula of the delta N is as follows:
wherein the content of the first and second substances,
for the phase offset to be achieved, t is the variation time of the division ratio of the phase-locked loop, the value of t is fixed, fphThe phase demodulation frequency of the phase-locked loop;
step 2: timing is carried out in the phase-locked loop circuit, and when the timing reaches t, the phase of the phase-locked loop circuit is shifted
Preferably, the specific process of step 2 is:
step 2.1: setting the frequency dividing ratio of a frequency divider in the phase-locked loop circuit to be N + delta N, wherein N is an initial value of the frequency dividing ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when t is timed out, the frequency dividing ratio of the frequency divider in the phase-locked loop circuit is changed into N, and the phase of the whole phase-locked loop circuit is shifted
The invention has the beneficial effects that:
the method provided by the invention can realize phase offset by changing the frequency dividing ratio or time in circuits such as a phase-locked loop and the like with adjustable frequency dividing ratio under the condition of not increasing any hardware cost, is simple to operate and can not cause the phase-locked loop to lose lock.
Drawings
Fig. 1 is a schematic diagram of phase adjustment in the prior art.
Fig. 2 is a schematic diagram of a phase-locked loop circuit according to embodiment 4.
Detailed Description
The following description of the embodiments of the present invention will be made with reference to the accompanying drawings:
phase offset in phase-locked loop circuitThe calculation formula of (2) is as follows:
where Δ N is the variation of the frequency dividing ratio of the phase-locked loop, fphThe phase demodulation frequency of the phase-locked loop is t, and the change time of the frequency division ratio of the phase-locked loop is t.
The process of solving the formula is as follows:
since the phase-locked loop circuit is basically a sine wave signal, which is taken as an example, a normal sine wave is:
where f is the frequency of the phase locked loop output,
is the initial phase due to the initial phase of the phase locked loop
Is uncontrollable and therefore cannot be changed
If one wants to change the phase of the sine wave, one can only change the output frequency f and the time t.
Suppose that the frequency dividing ratio of the phase-locked loop is N and the phase discrimination frequency is fphThat is, the sine wave output by the phase-locked loop is:
let Δ N be the variation of the frequency division ratio of the phase-locked loop, that is:
if the phase is to be shifted
It is necessary to obtain:
so that the time is made while changing the frequency dividing ratioΔ N can be achieved precisely by controlling the frequency division ratio, t can be changed to the initial frequency division ratio at the time of frequency division change, and the frequency division ratio Δ N becomes 0 after t time.
Example 1
A method for realizing phase offset of a phase-locked loop, for the phase-locked loop circuit of which the frequency dividing ratio of the phase-locked loop can only be changed in an integer, adjusts the phase by accurate adjusting time, and comprises the following steps:
step 1: calculating delta t, wherein the delta t is the change time of the frequency dividing ratio of the adjusted phase-locked loop, and the calculation formula of the delta t is as follows:
wherein the content of the first and second substances,
for the phase offset to be realized, Δ N is the amount of change in the division ratio of the phase locked loop, fphThe phase demodulation frequency of the phase-locked loop;
step 2: timing is performed in the phase-locked loop circuit, and when the timing reaches delta t, the phase of the phase-locked loop circuit is shifted
The specific process of the step 2 is as follows:
step 2.1: setting the frequency dividing ratio of a frequency divider in the phase-locked loop circuit to be N + delta N, wherein N is an initial value of the frequency dividing ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when the time reaches delta t, the frequency dividing ratio of the frequency divider in the phase-locked loop circuit is changed into N, and the phase offset of the whole phase-locked loop circuit
Example 2
Step 1: when Δ N is 1, fph50MHz, required phase offsetThen, Δ t is calculated to be 10 ns.
Step 2: setting the frequency dividing ratio of a frequency divider in the phase-locked loop circuit to be N +1, setting N as the initial value of the frequency dividing ratio of the set phase-locked loop, starting timing by using a clock signal of a controller in the phase-locked loop circuit, and changing the frequency dividing ratio of the frequency divider into N when the timing reaches 10ns, wherein the phase offset of the whole phase-locked loop circuit is 0.1 pi.
Example 3
A method for realizing phase offset of a phase-locked loop changes a frequency division ratio to adjust the phase of a phase-locked loop circuit which can realize a high-resolution fractional frequency division ratio, and comprises the following steps:
step 1: calculating delta N, wherein the delta N is the variation of the frequency dividing ratio of the phase-locked loop, and the calculation formula of the delta N is as follows:
wherein the content of the first and second substances,
for the phase offset to be achieved, t is the variation time of the division ratio of the phase-locked loop, the value of t is fixed, fphThe phase demodulation frequency of the phase-locked loop;
Step 2: in lockTiming is carried out in the phase-locked loop circuit, and when the timing reaches t, the phase of the phase-locked loop circuit is shifted
The specific process of the step 2 is as follows:
step 2.1: setting the frequency dividing ratio of a frequency divider in the phase-locked loop circuit to be N + delta N, wherein N is an initial value of the frequency dividing ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when t is timed out, the frequency dividing ratio of the frequency divider in the phase-locked loop circuit is changed into N, and the phase of the whole phase-locked loop circuit is shifted
Example 4
As shown in fig. 2, when the phase locked loop starts to work or performs frequency switching, the whole phase locked loop performs configuration of circuits such as a VCO, a phase detector, an integrator, and the like, and sends a frequency dividing ratio, the frequency dividing ratio performs correlation operation through an FPGA, and then controls a frequency divider, where a typical operation is sigma-delta modulation. The circuit mainly has reference clock 1 as default phase discrimination frequency fphThe input reference clock 2 of the FPGA is a clock signal f with fixed frequencyref2When no phase adjustment is performed or the phase-locked loop is operated before the phase adjustment is started, all the device configurations are not different from the conventional circuit.
Step 1: setting t to 0.01s, fph50MHz, required phase offsetWhen the calculated Δ N is 5.56 × 10-10At present, the sigma-delta modulation frequency division ratio is generally 58 bits (binary), so the method is easy to realize.
Step 2: in the FPGA, after an instruction for starting phase change is sent, the frequency dividing ratio of a frequency divider in the phase-locked loop circuit is N + delta N, N is the initial value of the set frequency dividing ratio of the phase-locked loop, and f is usedref2Beginning meterWhen the timing reaches 0.01s, the frequency dividing ratio of the frequency divider becomes N, and the phase of the entire phase-locked loop circuit is shifted by 0.1 °.
Because the change of the frequency dividing ratio is calculated to be small, the phase locking of the loop cannot be influenced, other circuits of the whole phase-locked loop do not need to be controlled, and the operation is simple. Since the clock frequency of the reference clock 2 is typically high, for example 100MHz, it is required to count Δ t equal to 0.01s, which is 10 in total6The error is negligible for every cycle. Since the resolution design goal for phase adjustment is at 0.1 °, the division ratio is typically at 58 bits (binary) for sigma-delta modulation, with negligible error.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (4)
1. A method for realizing phase offset of a phase-locked loop is characterized in that for a phase-locked loop circuit of which the frequency dividing ratio of the phase-locked loop can only be changed in an integer, the phase is adjusted by accurate adjusting time, and the realization method comprises the following steps:
step 1: calculating delta t, wherein the delta t is the change time of the frequency dividing ratio of the adjusted phase-locked loop, and the calculation formula of the delta t is as follows:
wherein the content of the first and second substances,
for the phase offset to be realized, Δ N is the amount of change in the division ratio of the phase locked loop, fphThe phase demodulation frequency of the phase-locked loop;
Δ N and fphAre all known values;
step 2: in a phase-locked loop circuitLine timing, when timing to delta t, phase shift of phase-locked loop circuit
2. The method for implementing phase offset of phase-locked loop according to claim 1, wherein the specific process of step 2 is:
step 2.1: setting the frequency dividing ratio of a frequency divider in the phase-locked loop circuit to be N + delta N, wherein N is an initial value of the frequency dividing ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when the time reaches delta t, the frequency dividing ratio of the frequency divider in the phase-locked loop circuit is changed into N, and the phase offset of the whole phase-locked loop circuit
3. A method for realizing phase offset of a phase-locked loop is characterized in that for a phase-locked loop circuit which can realize high-resolution fractional frequency division ratio, the phase is adjusted by changing the frequency division ratio, and the realization method comprises the following steps:
step 1: calculating delta N, wherein the delta N is the variation of the frequency dividing ratio of the phase-locked loop, and the calculation formula of the delta N is as follows:
wherein the content of the first and second substances,
for the phase offset to be achieved, t is the variation time of the division ratio of the phase-locked loop, the value of t is fixed, fphThe phase demodulation frequency of the phase-locked loop;
step 2: timing is carried out in the phase-locked loop circuit, and when the timing reaches t, the phase of the phase-locked loop circuit is shifted
4. The method for implementing phase offset of phase-locked loop according to claim 3, wherein the specific process of step 2 is:
step 2.1: setting the frequency dividing ratio of a frequency divider in the phase-locked loop circuit to be N + delta N, wherein N is an initial value of the frequency dividing ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when t is timed out, the frequency dividing ratio of the frequency divider in the phase-locked loop circuit is changed into N, and the phase of the whole phase-locked loop circuit is shifted
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Citations (7)
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|---|---|---|---|---|
| JPS61170135A (en) * | 1985-01-23 | 1986-07-31 | Sony Corp | Phase locked loop circuit |
| CN1281294A (en) * | 1999-07-19 | 2001-01-24 | 三菱电机株式会社 | Clock forming circuit |
| US20060082417A1 (en) * | 2004-03-23 | 2006-04-20 | Burkhard Neurauter | Phase locked loop and method for phase correction of a frequency controllable oscillator |
| CN102959868A (en) * | 2011-05-18 | 2013-03-06 | 旭化成微电子株式会社 | Accumulator type fractional-n pll synthesizer and control method thereof |
| CN103152034A (en) * | 2013-02-26 | 2013-06-12 | 中国电子科技集团公司第四十一研究所 | Decimal frequency dividing phase-locked loop circuit and control method for frequency dividing ratio |
| US20160087639A1 (en) * | 2014-09-24 | 2016-03-24 | Intel IP Corporation | Phase tracker for a phase locked loop |
| US10236895B1 (en) * | 2017-12-19 | 2019-03-19 | Analog Bits Inc. | Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops |
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- 2019-11-26 CN CN201911169856.0A patent/CN110808736B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61170135A (en) * | 1985-01-23 | 1986-07-31 | Sony Corp | Phase locked loop circuit |
| CN1281294A (en) * | 1999-07-19 | 2001-01-24 | 三菱电机株式会社 | Clock forming circuit |
| US20060082417A1 (en) * | 2004-03-23 | 2006-04-20 | Burkhard Neurauter | Phase locked loop and method for phase correction of a frequency controllable oscillator |
| CN102959868A (en) * | 2011-05-18 | 2013-03-06 | 旭化成微电子株式会社 | Accumulator type fractional-n pll synthesizer and control method thereof |
| CN103152034A (en) * | 2013-02-26 | 2013-06-12 | 中国电子科技集团公司第四十一研究所 | Decimal frequency dividing phase-locked loop circuit and control method for frequency dividing ratio |
| US20160087639A1 (en) * | 2014-09-24 | 2016-03-24 | Intel IP Corporation | Phase tracker for a phase locked loop |
| US10236895B1 (en) * | 2017-12-19 | 2019-03-19 | Analog Bits Inc. | Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops |
Non-Patent Citations (1)
| Title |
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| 江率: "基于Sigma-Delta方法的相位调制技术研究" * |
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