CN110808736B - Method for realizing phase shift of phase-locked loop - Google Patents
Method for realizing phase shift of phase-locked loop Download PDFInfo
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- CN110808736B CN110808736B CN201911169856.0A CN201911169856A CN110808736B CN 110808736 B CN110808736 B CN 110808736B CN 201911169856 A CN201911169856 A CN 201911169856A CN 110808736 B CN110808736 B CN 110808736B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a method for realizing phase shift of a phase-locked loop, which relates to the field of phase adjustment of a phase-locked loop circuit and realizes the phase shift in two ways: one is a phase-locked loop circuit which can only change integer for the frequency division ratio of the phase-locked loop, and the phase is adjusted by precisely adjusting the change time of the frequency division ratio of the phase-locked loop; another is to adjust the phase by fixing the time value, changing the frequency division ratio for a phase-locked loop circuit that can achieve a high resolution fractional frequency division ratio. The two modes can realize phase shift in circuits with adjustable frequency dividing ratio such as phase-locked loops and the like without increasing any hardware cost, and the phase-locked loops are easy to operate and cannot lose lock.
Description
Technical Field
The invention relates to the field of phase adjustment of phase-locked loop circuits, in particular to a method for realizing phase shift of a phase-locked loop.
Background
In the field of communication and the like, since a communication system needs to change the phase of a signal, it is necessary to adjust the phase without interrupting the signal, and the result of this phase adjustment is a phase shift.
For the direct digital frequency synthesis (DDS) technology, the phase debugging can be easily realized in the FPGA, and the initial phase of a signal can be accurately controlled by controlling an initial value, but for a phase-locked loop, as the phase-locked loop is a closed loop system, the initial phase cannot be determined due to the loop opening and closing process in the signal switching process, and if accurate phase control is required, the phase shifting method can be only used. As phase adjustment becomes more and more important, circuits such as phase locked loops need to be able to control the phase offset as accurately as digital circuits.
The conventional phase adjustment is to add a phase adjuster to the output of the phase locked loop circuit, as shown in fig. 1, and this way of controlling the phase is complex to implement and increases the cost.
Disclosure of Invention
Aiming at the problems of high cost and complex realization when the phase shift is carried out by the existing phase-locked loop circuit, the first aim of the invention is to provide a method for realizing the phase shift of the phase-locked loop, which controls the phase by adjusting the time.
The invention adopts the following technical scheme:
a method for realizing phase shift of phase-locked loop, for phase-locked loop circuit whose frequency dividing ratio can only be changed in integer, the phase is regulated by accurate regulating time, the realization method includes:
step 1: and calculating delta t, wherein delta t is the change time of the frequency division ratio of the phase-locked loop after adjustment, and the calculation formula of delta t is as follows:
wherein,for the phase shift to be achieved, ΔN is the variation of the frequency division ratio of the phase locked loop, f ph Is the phase discrimination frequency of the phase-locked loop;
ΔN and f ph Are known values;
step 2: timing in a phase-locked loop circuit, the phase of the phase-locked loop circuit being shifted when the timing reaches deltat
Preferably, the specific process of step 2 is:
step 2.1: setting the frequency division ratio of a frequency divider in the phase-locked loop circuit to be N+delta N, wherein N is the initial value of the frequency division ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when the time reaches delta t, the frequency division ratio of the frequency divider in the phase-locked loop circuit becomes N, and the phase of the whole phase-locked loop circuit is shifted
A second object of the present invention is to provide a method for implementing phase shift of a phase locked loop, which controls the phase by adjusting the frequency division ratio.
A method for implementing phase shift of a phase locked loop, for a phase locked loop circuit capable of implementing a high resolution fractional division ratio, varying the division ratio to adjust the phase, the implementation method comprising:
step 1: and calculating delta N, wherein delta N is the variable quantity of the frequency division ratio of the phase-locked loop, and the calculation formula of delta N is as follows:
wherein,for the phase shift to be realized, t is the change time of the frequency division ratio of the phase-locked loop, the value of t is fixed, f ph Is the phase discrimination frequency of the phase-locked loop;
t and f ph Are known values;
step 2: timing in a phase-locked loop circuit, the phase of which is shifted when the timing reaches t
Preferably, the specific process of step 2 is:
step 2.1: setting the frequency division ratio of a frequency divider in the phase-locked loop circuit to be N+delta N, wherein N is the initial value of the frequency division ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when timing to t, the frequency dividing ratio of the frequency divider in the phase-locked loop circuit becomes N, and the phase of the whole phase-locked loop circuit is shifted
The invention has the beneficial effects that:
the method provided by the invention can realize phase shift by changing the frequency dividing ratio or time in circuits with adjustable frequency dividing ratio such as a phase-locked loop and the like without increasing any hardware cost, and has simple operation and no loss of lock of the phase-locked loop.
Drawings
Fig. 1 is a prior art phase adjustment schematic.
Fig. 2 is a schematic circuit diagram of a phase locked loop in embodiment 4.
Detailed Description
The following description of the embodiments of the invention will be given with reference to the accompanying drawings and examples:
phase offset in phase locked loop circuitThe calculation formula of (2) is as follows: />Wherein DeltaN is the variation of the frequency division ratio of the phase-locked loop, f ph And t is the change time of the frequency division ratio of the phase-locked loop.
The process of the formula is as follows:
since the phase-locked loop circuits are basically sine wave signals, one is exemplified by a sine wave signalThe normal sine wave is:wherein f is the frequency of the phase-locked loop output, < >>Is the initial phase due to the initial phase of the phase-locked loop +.>Is uncontrollable, so that +.>If one wants to change the phase of the sine wave, one can only change the output frequency f and the time t.
Assuming that the frequency division ratio of the phase-locked loop is N and the phase discrimination frequency is f ph Namely, the output sine wave of the phase-locked loop is as follows:
let Δn be the variation of the frequency division ratio of the phase locked loop, namely:
if the phase is to be shiftedIt is necessary to obtain: />So that time +.>The delta N can be accurately reached by controlling the frequency division ratio number of transmissions, t can be started at the beginning of frequency division change, and the frequency division ratio delta N becomes 0 after t time.
Example 1
A method for realizing phase shift of phase-locked loop, for phase-locked loop circuit whose frequency dividing ratio can only be changed in integer, the phase is regulated by accurate regulating time, the realization method includes:
step 1: and calculating delta t, wherein delta t is the change time of the frequency division ratio of the phase-locked loop after adjustment, and the calculation formula of delta t is as follows:
wherein,for the phase shift to be achieved, ΔN is the variation of the frequency division ratio of the phase locked loop, f ph Is the phase discrimination frequency of the phase-locked loop;
ΔN and f ph Are known values;
step 2: timing in a phase-locked loop circuit, the phase of the phase-locked loop circuit being shifted when the timing reaches deltat
The specific process of the step 2 is as follows:
step 2.1: setting the frequency division ratio of a frequency divider in the phase-locked loop circuit to be N+delta N, wherein N is the initial value of the frequency division ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when the time reaches delta t, the frequency division ratio of the frequency divider in the phase-locked loop circuit becomes N, and the phase of the whole phase-locked loop circuit is shifted
Example 2
Step 1: when Δn=1, f ph =50 MHz, required phase offsetAt that time, Δt=10ns is calculated.
Step 2: setting the frequency dividing ratio of the frequency divider in the phase-locked loop circuit as N+1, wherein N is the initial value of the frequency dividing ratio of the set phase-locked loop, starting to count by using the clock signal of the controller in the phase-locked loop circuit, and when the count reaches 10ns, the frequency dividing ratio of the frequency divider becomes N, and the phase of the whole phase-locked loop circuit is offset by 0.1 pi.
Example 3
A method for implementing phase shift of a phase locked loop, for a phase locked loop circuit capable of implementing a high resolution fractional division ratio, varying the division ratio to adjust the phase, the implementation method comprising:
step 1: and calculating delta N, wherein delta N is the variable quantity of the frequency division ratio of the phase-locked loop, and the calculation formula of delta N is as follows:
wherein,for the phase shift to be realized, t is the change time of the frequency division ratio of the phase-locked loop, the value of t is fixed, f ph Is the phase discrimination frequency of the phase-locked loop;
t and f ph Are known values.
Step 2: timing in a phase-locked loop circuit, the phase of which is shifted when the timing reaches t
The specific process of the step 2 is as follows:
step 2.1: setting the frequency division ratio of a frequency divider in the phase-locked loop circuit to be N+delta N, wherein N is the initial value of the frequency division ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when timing to t, the frequency dividing ratio of the frequency divider in the phase-locked loop circuit becomes N, and the phase of the whole phase-locked loop circuit is shifted
Example 4
As shown in fig. 2, when the phase-locked loop starts to operate or performs frequency switching, the complete machine performs circuit configuration such as VCO, phase detector, integration, etc., and sends the configuration to the frequency division ratio, and the frequency division ratio performs correlation operation through the FPGA and then controls the frequency divider, and a typical operation is sigma-delta modulation. The circuit mainly has reference clock 1 default phase discrimination frequency f ph The input reference clock 2 of the FPGA is a clock signal f with fixed frequency ref2 When no phase adjustment is performed or the phase locked loop operates before the phase adjustment starts, all device configurations do not differ from conventional circuits.
Step 1: set t=0.01 s, f ph =50 MHz, required phase offsetWhen Δn=5.56×10 is calculated -10 Since the current sigma-delta modulation division ratio is typically 58 bits (binary), it is easy to implement.
Step 2: in the FPGA, after sending the instruction of phase beginning to change, the frequency dividing ratio of the frequency divider in the phase-locked loop circuit is N+DeltaN, N is the initial value of the frequency dividing ratio of the set phase-locked loop, and f is utilized ref2 When the timing is started and reaches 0.01s, the frequency dividing ratio of the frequency divider becomes N, and the phase of the whole phase-locked loop circuit is shifted by 0.1 degrees.
The phase locking of the loop is not affected because the change of the frequency division ratio is small by calculating, so that other circuits of the whole phase locking loop do not need to be controlled, and the operation is simple. Since the clock frequency of the reference clock 2 is generally high, e.g. 100MHz, useIt counts Δt=0.01 s, 10 total 6 The error is negligible for each cycle. Since the resolution of the phase adjustment is designed to be at 0.1 °, the frequency division ratio is typically 58 bits (binary) for sigma-delta modulation, with negligible error.
It should be understood that the above description is not intended to limit the invention to the particular embodiments disclosed, but to limit the invention to the particular embodiments disclosed, and that the invention is not limited to the particular embodiments disclosed, but is intended to cover modifications, adaptations, additions and alternatives falling within the spirit and scope of the invention.
Claims (2)
1. A method for implementing phase shift of a phase locked loop, wherein for a phase locked loop circuit in which a frequency division ratio of the phase locked loop can be changed only by an integer, a phase is adjusted by an accurate adjustment time, the implementing method comprising:
step 1: and calculating delta t, wherein delta t is the change time of the frequency division ratio of the phase-locked loop after adjustment, and the calculation formula of delta t is as follows:
wherein,for the phase shift to be achieved, ΔN is the variation of the frequency division ratio of the phase locked loop, f ph Is the phase discrimination frequency of the phase-locked loop;
ΔN and f ph Are known values;
step 2: timing in a phase-locked loop circuit, the phase of the phase-locked loop circuit being shifted when the timing reaches deltat
The specific process of the step 2 is as follows:
step 2.1: setting the frequency division ratio of a frequency divider in the phase-locked loop circuit to be N+delta N, wherein N is the initial value of the frequency division ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when the time reaches delta t, the frequency division ratio of the frequency divider in the phase-locked loop circuit becomes N, and the phase of the whole phase-locked loop circuit is shifted
2. A method for implementing phase shift of a phase locked loop, wherein for a phase locked loop circuit capable of implementing a high resolution fractional division ratio, the phase is adjusted by changing the division ratio, the implementation method comprising:
step 1: and calculating delta N, wherein delta N is the variable quantity of the frequency division ratio of the phase-locked loop, and the calculation formula of delta N is as follows:
wherein,for the phase shift to be realized, t is the change time of the frequency division ratio of the phase-locked loop, the value of t is fixed, f ph Is the phase discrimination frequency of the phase-locked loop;
t and f ph Are known values;
step 2: timing in a phase-locked loop circuit, the phase of which is shifted when the timing reaches t
The specific process of the step 2 is as follows:
step 2.1: setting the frequency division ratio of a frequency divider in the phase-locked loop circuit to be N+delta N, wherein N is the initial value of the frequency division ratio of the set phase-locked loop;
step 2.2: starting timing by using a clock signal of a controller in the phase-locked loop circuit;
step 2.3: when timing to t, the frequency dividing ratio of the frequency divider in the phase-locked loop circuit becomes N, and the phase of the whole phase-locked loop circuit is shifted
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| JPS61170135A (en) * | 1985-01-23 | 1986-07-31 | Sony Corp | Phase locked loop circuit |
| CN1281294A (en) * | 1999-07-19 | 2001-01-24 | 三菱电机株式会社 | Clock forming circuit |
| CN102959868A (en) * | 2011-05-18 | 2013-03-06 | 旭化成微电子株式会社 | Accumulator type fractional-n pll synthesizer and control method thereof |
| CN103152034A (en) * | 2013-02-26 | 2013-06-12 | 中国电子科技集团公司第四十一研究所 | Decimal frequency dividing phase-locked loop circuit and control method for frequency dividing ratio |
| US10236895B1 (en) * | 2017-12-19 | 2019-03-19 | Analog Bits Inc. | Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004014204B4 (en) * | 2004-03-23 | 2006-11-09 | Infineon Technologies Ag | Phase-locked loop and method for phase correction of a frequency-controllable oscillator |
| US9584139B2 (en) * | 2014-09-24 | 2017-02-28 | Intel IP Corporation | Phase tracker for a phase locked loop |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61170135A (en) * | 1985-01-23 | 1986-07-31 | Sony Corp | Phase locked loop circuit |
| CN1281294A (en) * | 1999-07-19 | 2001-01-24 | 三菱电机株式会社 | Clock forming circuit |
| CN102959868A (en) * | 2011-05-18 | 2013-03-06 | 旭化成微电子株式会社 | Accumulator type fractional-n pll synthesizer and control method thereof |
| CN103152034A (en) * | 2013-02-26 | 2013-06-12 | 中国电子科技集团公司第四十一研究所 | Decimal frequency dividing phase-locked loop circuit and control method for frequency dividing ratio |
| US10236895B1 (en) * | 2017-12-19 | 2019-03-19 | Analog Bits Inc. | Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops |
Non-Patent Citations (1)
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| 江率.基于Sigma-Delta方法的相位调制技术研究.中国优秀硕士论文全文数据库 信息科技辑.(第07期),第23-24页，图3-1. * |
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