CN110798150A - A Chaos Oscillator Based on Multiple Memristors - Google Patents

Abstract

The present invention provides a chaotic oscillator based on multiple memristors, comprising: an operational amplifier U ₁ , capacitors C ₁ , C ₂ , C ₃ , two forward and reverse diodes D ₁ , D ₂ , a resistor R, and an inductor L ₁ and two load-controlled memristors M ₁ (q ₁ ), M ₂ (q ₂ ) and one magnetron memristor W(ξ), one end of the magnetron memristor W(ξ) is connected to the positive phase of the operational amplifier Input terminals, one terminal of the two load-controlled memristors is connected to the inverting input terminal of the operational amplifier, the positive terminal of the capacitor _C1 is connected to the non-inverting input terminal of the operational amplifier, the positive terminal of the capacitor _C2 is connected to the positive terminal of the capacitor _C1 , The capacitor C ₃ and the inductor L ₁ are connected in parallel with one end of the two forward and reverse diodes D ₁ and D ₂ at the same time, and the other end is grounded. The invention solves the problem that the structure of the memristive circuit model in the prior art is too simple, the circuit elements involved in the circuit are relatively few, and the single memristor oscillator is more than the ideal commercial memristive circuit model. relatively unreasonable structure.

Description

A Chaos Oscillator Based on Multiple Memristors

technical field

The invention relates to the fields of circuit design, communication and information technology, in particular, to a chaotic oscillator based on multiple memristors.

Background technique

A chaotic system is a nonlinear system that can generate similar random signals. It has the characteristics of good pseudo-randomness, strong initial value sensitivity, and long-term unpredictability. Therefore, it has great application value in the fields of secure communication and image encryption. The chaotic signals often used in practical engineering applications are generally divided into two types: analog chaotic signals and digital chaotic signals. Since the simulation step size is limited in accuracy, the digital chaotic signal will cause chaotic degradation phenomenon under long-term operation, so the experimental results often fail to meet the ideal expectations. The chaotic signal generated by the analog circuit is continuous, which can effectively avoid the occurrence of this phenomenon.

The memristor is a nonlinear resistor with super memory characteristics. It can control the change of voltage and current by changing the resistance value, and this change can be maintained even when the power is turned off. These advantages are all ordinary resistors. do not have. If applied to the design of computer chips, computers could run several times faster. Therefore, the commercial realization of memristors has always been one of the hot topics of recent research. In the design of future memristor circuit systems, the most ideal result that can be achieved is that memristors can completely replace fixed-value resistors, so the research on circuit models with multiple memristors is of great significance for the physical realization of commercial memristors. The purpose of studying memristor dynamics is to gain a better understanding of its properties and ultimately to replace resistors entirely with memristors. However, the structure of the existing memristive circuit model is too simple, and there are relatively few circuit elements involved in the circuit, and there are many single memristive oscillators. This is a certain deviation from the requirements of the ideal commercial memristor circuit model, and the design structure is relatively unreasonable, which is not enough as a basic demonstration teaching for commercial memristor research.

SUMMARY OF THE INVENTION

According to the above-mentioned technical problem, a chaotic oscillator based on a plurality of memristors is provided. The invention applies a plurality of memristors to a nonlinear chaotic circuit to form a memristor chaotic circuit. In this case, the performances of the memristors can be brought into full play, and at the same time, the chaotic oscillator has a complete RLC resonant structure and multiple hybrid memristors.

The technical means adopted in the present invention are as follows:

A chaotic oscillator based on multiple memristors, comprising: operational amplifier U ₁ , capacitor C ₁ , capacitor C ₂ , capacitor C ₃ , two forward and reverse diodes D ₁ , D ₂ , resistor R, inductor L ₁ and Two load-controlled memristors M ₁ (q ₁ ), M ₂ (q ₂ ) and one magnetron memristor W(ξ), one end of the magnetron memristor W(ξ) is connected to the non-inverting input of the operational amplifier terminals, one terminal of the two load-controlled memristors M ₁ (q ₁ ) and M ₂ (q ₂ ) is connected to the inverting input terminal of the operational amplifier, the positive terminal of the capacitor C ₁ is connected to the non-inverting input terminal of the operational amplifier, and the capacitor C The positive terminal of ₂ is connected to the positive terminal _of the capacitor _C1 , the capacitor C3 and the inductor L1 are connected in parallel with _one end _of the _two forward and reverse diodes D1 and D2, and the other end is grounded.

Further, the load-controlled memristor is an analog equivalent circuit of a load-controlled memristor, and the magnetron memristor is an analog equivalent circuit of a magnetron memristor.

Further, the chaotic oscillator is described by the following equation:

Among them, u ₁ , u ₂ , u ₃ , and i ₁ represent the state variables corresponding to capacitance C ₁ , capacitance C ₂ , capacitance C ₃ , and inductance L ₁ , respectively; ξ, q ₁ , and q ₂ represent magnetron memristor W, respectively (ξ), state variables corresponding to load-controlled memristors M ₁ (q ₁ ) and M ₂ (q ₂ ); _id is a piecewise linear function, which can be expressed as:

i _d =g _d [u ₁ -u ₃ +0.5(|u ₁ -u ₃ -U _th |-|u ₁ -u ₃ +U _th |)]

where g _d represents the negative conductance value and U _th represents the diode threshold voltage.

Further, the load-controlled memristors M ₁ (q ₁ ), M ₂ (q ₂ ) and the magnetron memristor W(ξ) are described by the following equations:

Among them, a _ξ1 and b _ξ1 represent the parameters of the magnetron memristor respectively; a _q1 , b _q11 , a _q2 , and b _q22 represent the parameters of the load-controlled memristor respectively.

Compared with the prior art, the present invention has the following advantages:

1. The chaotic oscillator based on a plurality of memristors provided by the present invention has a simple circuit implementation. By adjusting the parameters of each element, the oscillator has a wide chaotic parameter interval, and the generated signal has strong pseudo-randomness, making the output chaotic. Signals can have higher complexity and stronger stability to meet different application requirements.

2. The chaotic oscillator based on multiple memristors provided by the present invention uses operational amplifiers as active devices and nonlinear components at the same time. The model is closer to the ideal commercial memristive oscillation circuit model, and the simple memristive oscillator model The realization of it is beneficial to the demonstration and teaching of chaotic phenomena, and the research on basic chaotic phenomena can be better applied in the engineering field, which has important value.

Based on the above reasons, the present invention can be widely promoted in the fields of circuit design, communication and information.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

FIG. 1 is a circuit schematic diagram of a chaotic oscillator of the present invention.

FIG. 2 is a diagram of a magnetron memristive equivalent circuit diagram of the chaotic oscillator of the present invention.

FIG. 3 is a load-controlled memristive equivalent circuit diagram of the chaotic oscillator of the present invention.

FIG. 4 is a chaotic attractor phase diagram of a state variable of a chaotic oscillator in an x-z phase plane provided by an embodiment of the present invention.

FIG. 5 is a schematic diagram of a circuit simulation result provided by an embodiment of the present invention.

Detailed ways

It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, but not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terminology used herein is for the purpose of describing specific embodiments only, and is not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly dictates otherwise, the singular is intended to include the plural as well, furthermore, it is to be understood that when the terms "comprising" and/or "including" are used in this specification, it indicates that There are features, steps, operations, devices, components and/or combinations thereof.

The relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the invention unless specifically stated otherwise. Meanwhile, it should be understood that, for convenience of description, the dimensions of various parts shown in the accompanying drawings are not drawn in an actual proportional relationship. Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the authorized description. In all examples shown and discussed herein, any specific values should be construed as illustrative only and not limiting. Accordingly, other examples of exemplary embodiments may have different values. It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further discussion in subsequent figures.

In the description of the present invention, it should be understood that the orientations indicated by orientation words such as "front, rear, top, bottom, left, right", "horizontal, vertical, vertical, horizontal" and "top, bottom" etc. Or the positional relationship is usually based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and these orientation words do not indicate or imply the indicated device or element unless otherwise stated. It must have a specific orientation or be constructed and operated in a specific orientation, so it should not be construed as a limitation on the scope of protection of the present invention: the orientation words "inside and outside" refer to the inside and outside relative to the contour of each component itself.

For ease of description, spatially relative terms, such as "on", "over", "on the surface", "above", etc., may be used herein to describe what is shown in the figures. The spatial positional relationship of one device or feature shown to other devices or features. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or features would then be oriented "below" or "over" the other devices or features under its device or structure". Thus, the exemplary term "above" can encompass both an orientation of "above" and "below." The device may also be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing corresponding components. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood to limit the scope of protection of the present invention.

Example

As shown in FIG. 1 , the present invention provides a chaotic oscillator based on multiple memristors, including: an operational amplifier U ₁ , a capacitor C ₁ , a capacitor C ₂ , a capacitor C ₃ , two forward and reverse diodes D ₁ , D ₂ , resistance R, inductance L ₁ and two charge-controlled memristors M ₁ (q ₁ ), M ₂ (q ₂ ) and one magnetron memristor W(ξ), magnetron memristor W(ξ ) ) is connected to the non-inverting input terminal of the operational amplifier, one end of the two load-controlled memristors M ₁ (q ₁ ) and M ₂ (q ₂ ) is connected to the inverting input terminal of the operational amplifier, and the positive terminal of the capacitor C ₁ is connected to The non-inverting input terminal of the operational amplifier, the positive terminal of the capacitor C ₂ is connected to the positive terminal of the capacitor C ₁ , the capacitor C ₃ and the inductor L ₁ are connected in parallel and both are connected to one end of the two forward and reverse diodes D ₁ and D ₂ at the same time, and the other end ground.

Further, as a preferred embodiment of the present invention, the load-controlled memristor is an analog equivalent circuit of a load-controlled memristor, and the magnetron memristor is an analog equivalent circuit of a magnetron memristor. . The operational amplifier is a conventional voltage-type operational amplifier, such as model OP07. The diodes are conventional diodes, eg model 1N4148.

1, the chaotic oscillator based on multiple memristors provided by the present invention is described by the following equation:

Among them, u ₁ , u ₂ , u ₃ , and i ₁ represent the state variables corresponding to capacitance C ₁ , capacitance C ₂ , capacitance C ₃ , and inductance L ₁ , respectively; ξ, q ₁ , and q ₂ represent magnetron memristor W, respectively (ξ), state variables corresponding to load-controlled memristors M ₁ (q ₁ ) and M ₂ (q ₂ ); _id is a piecewise linear function, which can be expressed as:

i _d =g _d [u ₁ -u ₃ +0.5(|u ₁ -u ₃ -U _th |-|u ₁ -u ₃ +U _th |)]

where g _d represents the negative conductance value and U _th represents the diode threshold voltage.

The described load-controlled memristors M ₁ (q ₁ ), M ₂ (q ₂ ) and magnetron memristor W(ξ) are described by the following equations:

Among them, a _ξ1 and b _ξ1 represent the parameters of the magnetron memristor respectively; a _q1 , b _q11 , a _q2 , and b _q22 represent the parameters of the load-controlled memristor respectively.

In this embodiment, when the operational amplifier U1 in the circuit shown in FIG. ₁ is powered by ±12V dual power supplies, the saturated output voltage of the operational amplifier is approximately equal to 10V. The circuit parameters are selected as R=5.6kΩ, _C1 = _C2 =C3 ₌ 33nF, L1 ₌ 10mH. The magnetron memristive equivalent circuit model and the load-controlled memristive equivalent circuit model shown in Figure 2 and Figure 3 are used for experimental demonstration. The parameters are set as follows:

The parameters of the magnetron memristive equivalent circuit are set as Rw ₁ =2kΩ, Rw ₂ =Rw ₃ =15kΩ, Cw=33nF;

The parameters of the equivalent circuit of the load-controlled memristor M ₁ (q ₁ ) are set as Rq ₁ =1kΩ, Rq ₂ =10Ω, and Cq ₁ =33nF;

The parameters of the equivalent circuit of the load-controlled memristor M ₂ (q ₂ ) are set as Rq ₃ =15kΩ, Rq ₄ =100Ω, Cq ₂ =33nF;

As shown in Figure 4, it is the numerical simulation of the chaotic attractor phase diagram of the state variables of the system in the x-z phase plane. Correspondingly, as shown in Figure 5, it is the result of the circuit experiment, and the results show that the results of the numerical simulation are basically consistent with the results of the circuit experiment.

To sum up, the chaotic oscillator based on a plurality of memristors provided by the present invention has a simple circuit implementation. By adjusting the parameters of each element, the oscillator has a wide range of chaotic parameters, and the generated signal has strong pseudo-randomness. The output chaotic signal can have higher complexity and stronger stability, which can meet different application requirements.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that it can still be The technical solutions described in the foregoing embodiments are modified, or some or all of the technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (4)

1. A chaotic oscillator based on multiple memristors, comprising: operational amplifier U₁Capacitor C₁Capacitor C₂Capacitor C₃Two positive and negative diodes D₁、D₂Resistance R, inductance L₁And two charge-controlled memristors M₁(q₁)、M₂(q₂) One end of the magnetic control memristor W (ξ) is connected with the positive phase input end of the operational amplifier, and the two charge control memristors M₁(q₁)、M₂(q₂) One end of the capacitor C is connected with the inverting input end of the operational amplifier₁The positive terminal of the capacitor is connected with the positive input terminal of the operational amplifier and the capacitor C₂The positive terminal of the capacitor C is connected with the capacitor C₁Positive terminal of (1), capacitor C₃And an inductance L₁Are connected in parallel and are simultaneously connected with two positive and negative diodes D₁、D₂And the other end is grounded.

2. The chaotic oscillator based on multiple memristors according to claim 1, wherein the charge control memristor is an analog equivalent circuit of the charge control memristor, and the magnetic control memristor is an analog equivalent circuit of the magnetic control memristor.

3. The chaotic oscillator based on multiple memristors according to claim 1, characterized in that the chaotic oscillator is described by the following equation:

wherein u is₁、u₂、u₃、i₁Respectively represent capacitances C₁Capacitor C₂Capacitor C₃Inductor L₁Corresponding state variables ξ, q₁、q₂Respectively represents a magnetic control memristor W (ξ) and a charge control memristor M₁(q₁)、M₂(q₂) A corresponding state variable; i.e. i_dIs a piecewise linear function and can be expressed as:

i_d＝g_d[u₁-u₃+0.5(|u₁-u₃-U_th|-|u₁-u₃+U_th|)]

wherein, g_dRepresenting a negative conductance value, U_thRepresenting the diode threshold voltage.

4. The chaotic oscillator based on multiple memristors according to claim 3, wherein the charge-controlled memristor M₁(q₁)、M₂(q₂) And the magnetically controlled memristor W (ξ) is described by the following equation:

wherein, a_ξ1、b_ξ1Respectively representing parameters of the magnetic control memristor; a is_q1、b_q11、a_q2、b_q22Respectively representing the parameters of the charge-controlled memristor.

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