CN111339674B - Threshold type binary memristor implementation method based on LTspice model - Google Patents
Threshold type binary memristor implementation method based on LTspice model Download PDFInfo
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- CN111339674B CN111339674B CN202010156608.9A CN202010156608A CN111339674B CN 111339674 B CN111339674 B CN 111339674B CN 202010156608 A CN202010156608 A CN 202010156608A CN 111339674 B CN111339674 B CN 111339674B
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Abstract
The invention discloses a threshold type binary memristor implementation method based on an LTspice model. According to the mathematical model of the threshold type binary memristor, the invention designs a model of the threshold type binary memristor based on LTspice software, and combines circuit analysis to obtain a circuit structure corresponding to the model, and the circuit structure consists of two controlled current sources and one capacitor. The characteristics of the model are simulated in LTspice software, and ideal results are obtained. The result shows that the model accords with the definition of the memristor, has obvious threshold characteristics and binary characteristics, namely, the resistance value can be changed only when the exciting voltage exceeds the threshold voltage, and can maintain two stable memristors, so that the logic states 0 and 1 are represented, no intermediate state exists, and the design idea is met. This is of great significance for further investigation of memristors for use in digital logic circuits.
Description
Technical Field
The invention relates to a threshold type binary memristor implementation method based on an LTspice model.
Background
Cai Shaotang teaches that there is presumed to be a fourth basic circuit element memristor, a nonlinear two-terminal circuit element whose resistance value can vary with the history of the input current or voltage, with memristive properties, based on the mathematical relationship between the missing magnetic flux and charge.
In 2008, the HP laboratory gives out the physical realization of the memristor by adopting the nanotechnology for the first time, finds that the memristor value can be used as an operand of the logic operation to complete the logic operation, realizes a substantial implication circuit based on the logical operation, and has important significance for the application of the memristor in the logic operation circuit. However, the nano-scale memristor still has the technical problem of production so far, and the memristor LTspice model has the advantages of easiness in implementation, low cost, controllable characteristics and the like, and can provide certain help for application circuit research of the memristor.
In a conventional binary logic circuit, the logic state of the circuit is represented by a high level and a low level, but the logic state is often volatile, i.e. the logic state cannot be saved after power failure. The memristor is applied to a logic circuit, and the binary logic 0 and 1 are represented by the resistance states, namely the high resistance state and the low resistance state, so that the defect that the level logic is not easy to store is exactly overcome by the nonvolatile property of the memristor.
It has also been found that the switch cross structure of memristors can enable storage of information, and this feature enables memristors to be applied in memory to complete logic operations, which is of great significance in implementing a novel computer architecture different from the conventional von neumann architecture. In addition, the research finds that in the nanoscale memristor device, a threshold effect is common, namely, the resistance value of the memristor can be changed only when the excitation voltage exceeds the threshold voltage, so that stable and reliable logic operation is realized.
Disclosure of Invention
Aiming at the defects existing in the prior study, the invention provides an LTspice model of a threshold type binary memristor so as to realize stable and reliable binary characteristics.
The technical scheme adopted for solving the technical problems is as follows:
the threshold type binary memristor implementation method based on LTspice model comprises the following steps:
constructing a mathematical model of a threshold type binary memristor:
where x is a system internal state variable,the first derivative of the variable x represents the change in x. v (t) is the voltage at two ends of the memristor, namely the input voltage of the model, i (t) is the current passing through the memristor, and R (x) is the memristor value of the memristor. R is R ON 、R OFF Two different stable memristances for the memristor, and there are no other intermediate resistance states.
A binary memristor LTspice model is provided, and comprises a controlled current source G m 、G x And with a controlled current source G x Parallel 1F capacitor C x Wherein the current source G is controlled m Is the output current i of (1) Gm I.e. the output current of the binary memristor, is equal to that defined in the mathematical modelControlled current source G x And capacitor C x The built-up circuit obtains a system internal state variable x, and TE and BE are set to BE two ends of a binary memristor LTspice model respectively, wherein TE is a voltage input end and is connected with input voltage; BE is the common terminal, ground.
Based on the mathematical model and the designed binary memristor LTspice model, the resistance characteristic of the binary memristor LTspice model is realized:
when inputting voltage v (t)>In the case of 1.2 a, the process is carried out,the value of x increases to x>At 0, memristance R (x) =r ON ；
When the input voltage is-1.2<v(t)<In the case of 1.2 a, the process is carried out,x will remain unchanged, memristance R (x) will remain unchanged;
when inputting voltage v (t)<At the time of-1.2,the value of x is reduced to x<At 0, memristance R (x) =r OFF 。
Memristance R (x) is changed through typeControl such that the current source G is controlled m Generating currents i of different values Gm Therefore, the resistance characteristic of the binary memristor LTspice model is represented.
The invention has the beneficial effects that: according to the mathematical model of the threshold type binary memristor, the invention designs a model of the threshold type binary memristor based on LTspice software, and combines circuit analysis to obtain a circuit structure corresponding to the model, and the circuit structure consists of two controlled current sources and one capacitor. The characteristics of the model are simulated in LTspice software, and ideal results are obtained. The result shows that the model accords with the definition of the memristor, has obvious threshold characteristics and binary characteristics, namely, the resistance value can be changed only when the exciting voltage exceeds the threshold voltage, and can maintain two stable memristors, so that the logic states 0 and 1 are represented, no intermediate state exists, and the design idea is met. This is of great significance for further investigation of memristors for use in digital logic circuits.
Drawings
FIG. 1 is a circuit structure corresponding to a threshold binary memristor LTspice model of the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
The theoretical starting point of the invention is to construct a mathematical model of a threshold type binary memristor, the memristor model can show two different stable memristors through the change of exciting voltage, so as to meet the actual requirement of a digital logic circuit, and the formula of the binary memristor mathematical model used by the invention is shown as follows:
where x is a system internal state variable,the first derivative of the variable x represents the change in x. v (t) is the voltage at two ends of the memristor, namely the input voltage of the model, i (t) is the current passing through the memristor, and R (x) is the memristor value of the memristor. R is R ON 、R OFF Two different stable memristances for the memristor, and there are no other intermediate resistance states.
As shown in FIG. 1, G m 、G x Are all controlled current sources, wherein the current source G m Is the output current i of (1) Gm I.e. the output current of the memristor, etc. and defined in a mathematical modelTE and BE are the two ends of the memristor LTspice model, respectively. Wherein TE is a voltage input end and is connected with an input voltage; BE is the common terminal, ground.
As shown in fig. 1, a current source G x And capacitor C x The built-up circuit gets the internal state variable x, current source G of the system x Is the output current i of (1) Gx Is numerically equal to that defined in the mathematical modelC x A capacitor of 1F for i Gx And (3) finishing integral operation to obtain the value of the required system internal variable x, wherein the dimension of x is the voltage. If consider the initial value, capacitor C x Voltage value at both ends:
in the formula, v C0 For the capacitor C x Is equal in value to an initial value x of x 0 。
According to the mathematical model and the diagram, the characteristics of the memristor model and the internal state change process thereof are described as follows:
memristance R (x) varies with input voltage v (t). Input voltage v (t)>In the case of 1.2 a, the process is carried out,the value of x increases to x>At 0, memristance R (x) =r ON The method comprises the steps of carrying out a first treatment on the surface of the Input voltage-1.2<v(t)<1.2>x will remain unchanged, memristance R (x) will remain unchanged; input voltage v (t)<-1.2->The value of x is reduced to x<At 0, memristance R (x) =r OFF 。
Memristance R (x) is changed through typeControl such that current source G m Generating currents i of different values Gm I.e., the output current of the memristor model, this allows the resistive properties of the model to be represented.
The above description of the internal state change process of the memristor model shows that the model has obvious threshold characteristics, and obviously only when the excitation voltage V (t) reaches the threshold voltage + -1.2V, the first derivative of the state variable xThe variable x is switched into different differential equations, and under the action of the different differential equations, the variable x has different change conditions, finally approaches to different values, and the memristance R (x) is controlled to change. At the same time, the model also has good binary characteristicsAs can be seen from the model internal state change process and the expression of R (x), R (x) is only R ON And R is OFF The two values are switched, no other intermediate state exists, and when the exciting voltage v (t) does not reach the threshold voltage, the memristance R (x) is not changed, so that the memristance R (x) can exist stably. This meets the requirements of the logic operation circuit application.
It should be appreciated by those skilled in the art that the foregoing description is only a preferred embodiment of the invention, and is not intended to limit the invention, but any modifications, equivalent substitutions, improvements, etc. made to the above examples are intended to be included in the scope of the present invention.
Claims (1)
1. The method for realizing the threshold type binary memristor based on the LTspice model is characterized by comprising the following steps of:
constructing a mathematical model of a threshold type binary memristor:
where x is a system internal state variable,the first derivative of the variable x represents the change condition of x; v (t) is the voltage at two ends of the memristor, namely the input voltage of the model, i (t) is the current passing through the memristor, and R (x) is the memristor value of the memristor; r is R ON 、R OFF Two different stable memristances for memristors, and is absentIn any other intermediate resistance state;
a binary memristor LTspice model is provided, and comprises a controlled current source G m 、G x And with a controlled current source G x Parallel 1F capacitor C x Wherein the current source G is controlled m Is the output current i of (1) Gm I.e. the output current of the binary memristor, is equal to that defined in the mathematical modelControlled current source G x And capacitor C x The built circuit obtains a system internal state variable x, and TE and BE are set to BE two ends of a binary memristor LTspice model respectively, wherein TE is a voltage input end and is connected with an input signal; BE is the public terminal, the ground;
based on the mathematical model and the designed binary memristor LTspice model, the resistance characteristic of the binary memristor LTspice model is realized:
when inputting voltage v (t)>In the case of 1.2 a, the process is carried out,the value of x increases to x>At 0, memristance R (x) =r ON ；
When the input voltage is-1.2<v(t)<In the case of 1.2 a, the process is carried out,x will remain unchanged, memristance R (x) will remain unchanged;
when inputting voltage v (t)<At the time of-1.2,the value of x is reduced to x<At 0, memristance R (x) =r OFF ；
Memristance R (x) is changed through typeControl such that the current source G is controlled m Generating currents i of different values Gm Thereby making a binary memoryThe resistance characteristics of the resistor LTspice model are represented.
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| US9019030B1 (en) * | 2014-09-18 | 2015-04-28 | King Fahd University Of Petroleum And Minerals | Memristor-based emulator for use in digital modulation |
| CN109214048A (en) * | 2018-07-27 | 2019-01-15 | 西南大学 | Utilize mixing CMOS- memristor fuzzy logic gate circuit and its design method |
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| US8773167B2 (en) * | 2012-07-30 | 2014-07-08 | Hewlett-Packard Development Company, L.P. | Implementing logic circuits with memristors |
| US9685954B2 (en) * | 2014-03-09 | 2017-06-20 | Technion Research & Development Foundation Ltd. | Pure memristive logic gate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9019030B1 (en) * | 2014-09-18 | 2015-04-28 | King Fahd University Of Petroleum And Minerals | Memristor-based emulator for use in digital modulation |
| CN109214048A (en) * | 2018-07-27 | 2019-01-15 | 西南大学 | Utilize mixing CMOS- memristor fuzzy logic gate circuit and its design method |
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| Design and Analysis of Memristor-based Combinational Circuits;Anuradha Singh;IETE Journal of Research;第66卷(第2期);第182-191页 * |
| 阈值型忆阻器串联电路研究;王祥等;杭州电子科技大学学报(自然科学版);第38卷(第06期);第12-15,27页 * |
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