CN110797299A - Through hole structure and manufacturing method thereof - Google Patents
Through hole structure and manufacturing method thereof Download PDFInfo
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- CN110797299A CN110797299A CN201910937839.0A CN201910937839A CN110797299A CN 110797299 A CN110797299 A CN 110797299A CN 201910937839 A CN201910937839 A CN 201910937839A CN 110797299 A CN110797299 A CN 110797299A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a through hole structure and a manufacturing method thereof. Through the deposition of the first nitride layer, the butt joint of the hole etched on the back side and the hole etched on the front side is realized, and meanwhile, the verticality of the whole side wall is also ensured. When electroplating metal, the thickness of the deposited metal layer is in direct proportion to the electroplating time and the current density, and a thicker deposited layer is formed to seal the front hole. The wax is prevented from flowing into the deep hole, and the wax removal and the sapphire removal in the subsequent process are avoided. The thickness of the coated photoresist is ensured by combining the front hole and the back hole, so that the problems of developing profile, abnormal surface of the wafer and the like are avoided, the manufacturing difficulty of yellow lithography is reduced, and the precision and the yield of the through hole are improved. The process efficiency is improved, the photoresist consumption is reduced, the profile and the wafer surface abnormality during development are avoided, the process difficulty of yellow lithography is reduced, and the precision and the yield of through holes are improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a through hole structure and a manufacturing method thereof.
Background
In the field of semiconductor fabrication, metal and photoresist or photoresist alone are used to fabricate vias. Deeper etch depths can be achieved at the same time in the photoresist alone. However, if the through holes with a thickness of more than 150 μm are to be obtained, the thickness of the photoresist needs to be increased, but if the photoresist is coated too thick, the problems of developing profile and wafer surface abnormality occur, which further affects the appearance of the through holes. Meanwhile, when fabricating deep holes with a depth of more than 150 μm, the method of increasing the thickness of the photoresist will increase the difficulty of the photolithography process and the yield will be low. The conventional CVD (chemical vapor deposition) equipment cannot deposit silicon nitride on the back surface, so that silicon nitride and photoresist cannot be used as a mask. Therefore, the industry is seeking a via structure and a method for fabricating the same.
Disclosure of Invention
Therefore, it is desirable to provide a via structure and a method for fabricating the same to solve the problems of abnormal surface of the wafer and low yield of the via.
In order to achieve the above object, the inventors provide a method for manufacturing a through hole, comprising the steps of:
covering a first photoresist layer on the semiconductor substrate and developing at the through hole to be formed;
etching the semiconductor substrate by using the first photoresist layer as a mask to obtain a front hole;
removing the first photoresist layer and depositing a first nitride layer;
sputtering a seed crystal layer and depositing metal to the front hole;
covering the front surface of the semiconductor substrate with wax and sapphire, and then carrying out a back surface process;
and coating a second photoresist layer on the back of the semiconductor substrate, developing at the position of the through hole, and etching the semiconductor substrate and the first nitride layer by using the second photoresist layer as a mask to obtain a back hole communicated with the front hole so as to form a through hole structure.
Further, the diameter of the front hole is larger than that of the back hole.
Further, the step of depositing metal to the front side holes comprises the following steps:
covering the third photoresist layer and developing at the front hole;
and removing the third photoresist layer after depositing the metal.
Further, before covering the first photoresist layer, the method further comprises the steps of: covering the second nitride layer.
Further, the method also comprises the following steps:
and carrying out electroplating hole filling or metal coating on the side wall of the back hole to form a metal layer.
Further, the second nitride layer has a thickness of
The thickness of the first photoresist layer is 28 μm, and the thickness of the second photoresist layer is 28 μm.
Further, the metal of the deposition seed crystal layer is chromium, nickel or titanium-tungsten alloy.
Further, the semiconductor substrate is a gallium arsenide substrate.
The invention provides a through hole structure, which is manufactured by the manufacturing method of the through hole.
Different from the prior art, the through hole is manufactured by combining the front hole and the back hole in the technical scheme. Through depositing the first nitride layer, realize the butt joint of the hole of back etching and the hole of front etching, also guaranteed the straightness that hangs down of whole lateral wall simultaneously. The thickness of the deposited metal layer when electroplating metal is performed is proportional to the time and current density of the electroplating. And a higher current density is formed at the raised portions or corners, thereby forming a thicker deposition layer to seal the front opening. The purpose of sealing the front metal hole is to prevent wax from flowing into the deep hole and causing vacuum to be directly adsorbed on the wax and the sapphire when the back hole is connected with the front hole, so that the wax removal and the sapphire in the subsequent process are difficult. The thickness of the coated photoresist is ensured by combining the front hole and the back hole, so that the problems of developing profile, abnormal surface of the wafer and the like are avoided, the manufacturing difficulty of yellow lithography is reduced, and the precision and the yield of the through hole are improved.
Drawings
FIG. 1 is a diagram illustrating the fabrication of a first photoresist layer according to an embodiment;
FIG. 2 is a diagram illustrating the fabrication of a first nitride layer according to one embodiment;
FIG. 3 is a block diagram of a deposited seed layer according to one embodiment;
FIG. 4 is a block diagram of a deposited electroplated layer according to one embodiment;
FIG. 5 is a structural diagram of the coating wax and sapphire according to an embodiment;
fig. 6 is a structural diagram of the fabrication of the back hole according to the embodiment.
Description of reference numerals:
1. a semiconductor substrate;
2. a first photoresist layer;
3. a front hole;
4. a first nitride layer;
5. a seed crystal layer;
6. electroplating layer;
7. wax and sapphire;
8. a second photoresist layer;
9. a back hole;
10. a third photoresist layer;
11. a second nitride layer;
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to fig. 6, the present embodiment provides a method for fabricating a through hole on a semiconductor substrate 1, such as a gallium arsenide substrate. The manufacturing method comprises the following steps: a first photoresist layer 2 with a thickness of 28 μm is coated on a semiconductor substrate 1, and a photoresist lithography is performed at a via hole to be formed. Forming front holes 3 by ICP (inductively coupled plasma) etching with the first photoresist layer 2 as a mask, and depositing to a thickness greater than
A first nitride layer 4 of (angstrom). And sputtering a seed crystal layer 5 on the first nitride layer 4, wherein the sputtered metal is any one of Cr (chromium), Ni (nickel) and Tiw (titanium-tungsten alloy), the thickness of the sputtered metal is larger at the flat part and the opening of the front hole 3 due to the step coverage capability, and the inside of the hole is sputtered with little or no metal according to the depth of the hole. Then, metal is electroplated to the front hole 3 to form a plating layer 6. The thickness of the deposited metal layer when the metal is electroplated is proportional to the time and current density of the electroplating. And a higher current density is formed at the raised portions or corners, thereby forming a thicker deposition layer to seal the front opening 3. The front surface of the semiconductor substrate 1 is waxed and sapphire 7 is prepared for a back surface via process. The purpose of sealing the front metal hole is to prevent wax from flowing into the deep hole and causing vacuum to be directly adsorbed on the wax and the sapphire 7 when the back hole 9 is connected with the front hole 3, so that the subsequent process dewaxing and sapphire are difficult to bring. Coating a second photoresist layer 8 on the back surface of the semiconductor substrate 1, developing at the through hole, etching the semiconductor substrate and the first nitride layer 4 by using the second photoresist layer 8 as a mask to obtain a back hole 9 communicated with the front hole 3, and forming a through hole structure. The present invention uses a combination of front holes 3 and back holes 9 to form through holes. By depositing the first nitride layer 4, the butt joint of the back etched hole and the front etched hole is realized, and meanwhile, the verticality of the whole side wall is also ensured. The thickness of the coated photoresist is ensured by combining the front hole 3 and the back hole 9, thereby avoidingThe problems of developing contour and wafer surface abnormality are avoided, the process difficulty of photolithography is reduced, and the precision and yield of through holes are improved.
Referring to fig. 6, the diameter of the front hole 3 is larger than that of the back hole 9. When etching the back hole 9, the back alignment tolerance is between 2-3 μm, when etching the front hole 3, the diameter is larger than the diameter of the back hole 9, and the first nitride layer 4 is added after the front through hole to reduce the diameter of the front hole 3 by 2-3 μm and facilitate the subsequent filling of the front hole 3 surface. The method also enables the diameters of the front deep hole and the back deep hole to be consistent, and ensures the perpendicularity of the side wall.
Referring to fig. 4, in some embodiments, depositing metal into the front side hole includes: coating the third photoresist layer 10 and performing photolithography on the front hole 3 to form an opening. At the same time, after sealing the front hole 3, the third photoresist layer 10 is removed. The third photoresist layer 10 covers the seed crystal layer 5 around the front hole 3, so that the current density around the deep hole is further improved, the deposition rate on the surface of the deep hole is higher than that in the hole, and the efficiency and the precision of sealing the front hole 3 are further improved.
Referring to FIG. 1, in some embodiments, before covering the first photoresist layer 2, the method further includes the steps of: coating thickness of
And a second nitride layer 11. The second nitride layer 11 and the first photoresist layer 2 together serve as a mask for ICP etching, further protecting the integrity of the edges of the front side holes 3 on the semiconductor substrate 1.
Referring to fig. 6, in some embodiments, the method for forming a via further includes the following steps: and (3) carrying out electroplating hole filling or metal coating on the side wall of the back hole 9 to form a metal layer. And forming the electric connection of the front and the rear through holes and providing a foundation for the subsequent process steps of the semiconductor.
Referring to FIG. 1, in some embodiments, the second nitride thickness is
The thickness of the first photoresist layer 2 is 28 μm, and the thickness of the second photoresist layer 8 is 28 μm. The thickness of the photoresist is prevented from increasing due to the increase of the hole depth, the increase of the thickness of the photoresist to be coated is avoided, the developing profile and the surface of the wafer are ensured to be normal, and the appearance of the through hole is further optimized. Meanwhile, the manufacturing process difficulty of the yellow lithography is reduced, and the precision and the yield of the through hole are improved.
Referring to fig. 6, the present invention provides a via structure, which is manufactured by the method for manufacturing a via according to any one of the embodiments of the present invention. The through hole structure manufactured by the invention ensures the consistency of the apertures of the front hole 3 and the back hole 9, realizes the butt joint of the back etched hole and the front etched hole, and simultaneously ensures the verticality of the whole side wall. The thickness of the coated photoresist is ensured by combining the front hole 3 and the back hole 9, so that the problems of developing profile, abnormal surface of the wafer and the like are avoided, the process difficulty of yellow lithography is reduced, and the precision and yield of the through hole are improved.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (9)
1. A manufacturing method of a through hole is characterized by comprising the following steps:
covering a first photoresist layer on the semiconductor substrate and developing at the through hole to be formed;
etching the semiconductor substrate by using the first photoresist layer as a mask to obtain a front hole;
removing the first photoresist layer and depositing a first nitride layer;
sputtering a seed crystal layer and depositing metal to the front hole;
covering the front surface of the semiconductor substrate with wax and sapphire, and then carrying out a back surface process;
and coating a second photoresist layer on the back of the semiconductor substrate, developing at the position of the through hole, and etching the semiconductor substrate and the first nitride layer by using the second photoresist layer as a mask to obtain a back hole communicated with the front hole so as to form a through hole structure.
2. The method of claim 1, wherein the diameter of the front hole is larger than the diameter of the back hole.
3. The method of claim 1, wherein depositing metal into the front hole comprises:
covering the third photoresist layer and developing at the front hole;
and removing the third photoresist layer after depositing the metal.
4. The method of claim 1, further comprising the step of, before covering the first photoresist layer: covering the second nitride layer.
5. The method of claim 1, further comprising the steps of:
and carrying out electroplating hole filling or metal coating on the side wall of the back hole to form a metal layer.
6. The method of claim 1, wherein the second nitride layer has a thickness of
The thickness of the first photoresist layer is 28 μm, and the thickness of the second photoresist layer is 28 μm.
7. The method of claim 1, wherein the metal of the seed layer is chromium, nickel or titanium-tungsten alloy.
8. The method of any one of claims 1-7, wherein the semiconductor substrate is a gallium arsenide substrate.
9. A via structure, characterized in that said via structure is made by a via making method according to any of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910937839.0A CN110797299B (en) | 2019-09-30 | 2019-09-30 | Through hole structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910937839.0A CN110797299B (en) | 2019-09-30 | 2019-09-30 | Through hole structure and manufacturing method thereof |
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| CN110797299A true CN110797299A (en) | 2020-02-14 |
| CN110797299B CN110797299B (en) | 2022-08-12 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030003724A1 (en) * | 2001-06-27 | 2003-01-02 | Hitachi, Ltd. | Manufacturing method of the semiconductor device |
| US20040018712A1 (en) * | 2002-07-29 | 2004-01-29 | Plas Hubert Vander | Method of forming a through-substrate interconnect |
| US20110097846A1 (en) * | 2009-10-28 | 2011-04-28 | Son-Kwan Hwang | Semiconductor chip, wafer stack package using the same, and methods of manufacturing the same |
| CN103210486A (en) * | 2010-09-17 | 2013-07-17 | 德塞拉股份有限公司 | Staged via formation from both sides of chip |
| US20130209672A1 (en) * | 2012-02-10 | 2013-08-15 | Jochen Reinmuth | Component having a through-connection |
| CN104347492A (en) * | 2013-08-09 | 2015-02-11 | 上海微电子装备有限公司 | Manufacturing methods for through hole structure with high depth-to-width ratio and multi-chip interconnection |
| CN106057757A (en) * | 2016-07-08 | 2016-10-26 | 桂林电子科技大学 | Silicon through hole structure and manufacturing method thereeof |
-
2019
- 2019-09-30 CN CN201910937839.0A patent/CN110797299B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030003724A1 (en) * | 2001-06-27 | 2003-01-02 | Hitachi, Ltd. | Manufacturing method of the semiconductor device |
| US20040018712A1 (en) * | 2002-07-29 | 2004-01-29 | Plas Hubert Vander | Method of forming a through-substrate interconnect |
| US20110097846A1 (en) * | 2009-10-28 | 2011-04-28 | Son-Kwan Hwang | Semiconductor chip, wafer stack package using the same, and methods of manufacturing the same |
| CN103210486A (en) * | 2010-09-17 | 2013-07-17 | 德塞拉股份有限公司 | Staged via formation from both sides of chip |
| US20130209672A1 (en) * | 2012-02-10 | 2013-08-15 | Jochen Reinmuth | Component having a through-connection |
| CN104347492A (en) * | 2013-08-09 | 2015-02-11 | 上海微电子装备有限公司 | Manufacturing methods for through hole structure with high depth-to-width ratio and multi-chip interconnection |
| CN106057757A (en) * | 2016-07-08 | 2016-10-26 | 桂林电子科技大学 | Silicon through hole structure and manufacturing method thereeof |
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| CN110797299B (en) | 2022-08-12 |
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