CN116364649A - Method for improving edge breakage in gallium arsenide through hole etching process - Google Patents
Method for improving edge breakage in gallium arsenide through hole etching process Download PDFInfo
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- CN116364649A CN116364649A CN202310063614.3A CN202310063614A CN116364649A CN 116364649 A CN116364649 A CN 116364649A CN 202310063614 A CN202310063614 A CN 202310063614A CN 116364649 A CN116364649 A CN 116364649A
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- hole
- metal layer
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- gallium arsenide
- etching process
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 238000005530 etching Methods 0.000 title claims abstract description 57
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title claims abstract description 23
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 88
- 239000002184 metal Substances 0.000 claims abstract description 88
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 77
- 239000004642 Polyimide Substances 0.000 claims abstract description 34
- 229920001721 polyimide Polymers 0.000 claims abstract description 34
- 239000011248 coating agent Substances 0.000 claims abstract description 14
- 238000000576 coating method Methods 0.000 claims abstract description 14
- 238000004544 sputter deposition Methods 0.000 claims abstract description 14
- 238000011161 development Methods 0.000 claims abstract description 12
- 239000013078 crystal Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 4
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 28
- 238000009616 inductively coupled plasma Methods 0.000 description 18
- 238000009713 electroplating Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- NLKNQRATVPKPDG-UHFFFAOYSA-M potassium iodide Chemical compound [K+].[I-] NLKNQRATVPKPDG-UHFFFAOYSA-M 0.000 description 3
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a method for improving edge collapse in a gallium arsenide through hole etching process, which comprises the following steps: s1, sputtering a metal layer on the surface of the crystal back with the front surface process completed; s2, attaching a first photoresist layer on the metal layer, and removing the first photoresist layer at the position of the through hole to be etched through alignment development; s3, etching the metal layer at the through hole to be etched; s4, performing ICP etching on the through hole to generate edge breakage; s5, removing the first photoresist layer and the metal layer; and S6, coating polyimide on the surface of the back of the crystal for filling holes formed by edge collapse. The invention adopts the combination of the photoresist layer and the metal layer as the mask, avoids the appearance problem caused by insufficient thickness of the photoresist or excessive thickness of the photoresist, fills the hole formed by the edge collapse by polyimide, and can avoid the abnormal appearance caused by the edge collapse hole during metal wiring.
Description
Technical Field
The invention relates to the technical field of semiconductor device production, in particular to a method for improving edge breakage in gallium arsenide through hole etching process.
Background
In the prior art, a photoresist layer is used as a mask, a layer of photoresist is attached on the surface of a wafer, the thickness is about 14 mu m, and the depth of 75 mu m-100 mu m can be etched. But when gallium arsenide (GaAs) vias are etched beyond 100 μm depth, the photoresist layer thickness is insufficient to withstand Inductively Coupled Plasma (ICP) etching. To solve this problem, there are two main approaches in the prior art, one is to increase the photoresist thickness, and this approach can generate potential photoresist deformation, making the etched profile undesirable; the other is to use the combination of the photoresist layer and the metal layer as a mask, the method can cause edge collapse of the etched through hole edge, the appearance is shown in figure 1, the edge collapse can be filled in the subsequent metal wiring procedure for sputtering and electroplating, the appearance is shown in figure 2, the high-frequency performance of the device is not ideal, and the service life is influenced.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the method for improving the edge collapse in the gallium arsenide through hole etching process is provided, so that the technical problem of how to avoid abnormal morphology caused by the edge collapse hole during metal wiring is solved.
In order to solve the technical problems, the invention adopts the following technical scheme:
a method for improving edge breakage in gallium arsenide through hole etching process comprises the following steps: s1, sputtering a metal layer on the surface of the crystal back with the front surface process completed; s2, attaching a first photoresist layer on the metal layer, and removing the first photoresist layer at the position of the through hole to be etched through alignment development; s3, etching the metal layer at the through hole to be etched; s4, performing ICP etching on the through hole to generate edge breakage; s5, removing the first photoresist layer and the metal layer; and S6, coating polyimide on the surface of the crystal back for filling holes formed by edge collapse.
The invention has the beneficial effects that: the photoresist layer and the metal layer are combined to be used as a mask, so that the appearance problem caused by insufficient thickness of the photoresist or excessive thickness of the photoresist is avoided, the holes formed by edge collapse are filled with polyimide, and the abnormal appearance caused by the edge collapse holes during metal wiring can be avoided.
Drawings
FIG. 1 is a broken edge topography of an ICP etched via;
FIG. 2 is a topography of a metal filled tipping hole;
FIG. 3 is a general flow chart of a method for improving edge chipping in a GaAs via etch process in accordance with one embodiment of the present invention;
FIG. 4 is a schematic diagram showing a process of edge chipping during GaAs via etching in accordance with one embodiment of the present invention;
fig. 5 is a schematic diagram of a process of filling a broken edge hole in a GaAs via etching process with PI in an embodiment of the present invention.
Description of the drawings: 1. a wafer; 2. a metal layer; 3. a first photoresist layer; 4. metal on the front side of the wafer; 5. polyimide; 6. a second photoresist layer; 7. sputtered and electroplated metal.
Detailed Description
In order to describe the technical contents, the achieved objects and effects of the present invention in detail, the following description will be made with reference to the embodiments in conjunction with the accompanying drawings.
Referring to fig. 3, the invention provides a method for improving edge chipping in a gallium arsenide via etching process, comprising the following steps:
s1, sputtering a metal layer on the surface of the crystal back with the front surface process completed;
s2, attaching a first photoresist layer on the metal layer, and removing the first photoresist layer at the position of the through hole to be etched through alignment development;
s3, etching the metal layer at the through hole to be etched;
s4, performing ICP etching on the through hole to generate edge breakage;
s5, removing the first photoresist layer and the metal layer;
and S6, coating polyimide on the surface of the crystal back for filling holes formed by edge collapse.
From the above description, the beneficial effects of the invention are as follows: the photoresist layer and the metal layer are combined to be used as a mask, so that the appearance problem caused by insufficient thickness of the photoresist or excessive thickness of the photoresist is avoided, the holes formed by edge collapse are filled with polyimide, and the abnormal appearance caused by the edge collapse holes during metal wiring can be avoided.
Further, the method comprises the steps of:
s7, attaching a second photoresist layer on the surface of the wafer back, and removing the second photoresist layer at the through hole through alignment development;
s8, removing polyimide flowing into the bottoms of the through holes in the step S6 by adopting an ICP microetching mode, so as to ensure that polyimide is removed cleanly;
s9, removing the second photoresist layer, and performing subsequent procedures.
From the above description, the polyimide at the bottom of the through hole is removed, so that the metal to be sputtered and electroplated later and the metal on the front surface of the wafer are prevented from being interconnected.
Further, in the step S2, the material of the metal layer is one or more selected from tungsten, titanium, gold, and tungsten-titanium alloy.
As can be seen from the above description, these materials are capable of withstanding ICP etching in combination with the first photoresist layer, such that the etched via profile is satisfactory.
Further, the thickness of the metal layer is 2000A-5000A.
From the above description, it is clear that the metal layer is too thin to function as a barrier to ICP, i.e., to protect GaAs from ICP etching. If the metal layer is too thick, it takes a long time for the metal etching process to ensure that the ICP etching area is free of metal residues.
Further, in the step S3, the metal layer at the through hole to be etched is etched by wet etching.
As can be seen from the above description, the wet etching process is simple and the time of the metal etching process can be shortened.
Further, the etching time is 40s-80s.
From the above description, it is apparent that the etching time is optimized to reduce the side etching of the metal and reduce the edge chipping.
Further, in the step S2, the thickness of the first photoresist layer is 14 μm to 28 μm;
from the above description, the present invention can perform IPC via etching process using conventional photoresist thickness due to the metal layer.
Further, in the step S4, the depth of the through hole is 120 μm to 250 μm.
As can be seen from the above description, ICP etching of the through holes of the range of values and depths on the wafer surface will produce edge chipping.
Further, in the step S6, a coating thickness of polyimide on the surface of the back of the wafer is not less than 5 μm.
From the above description, it is possible to prevent polyimide at the edge from being lost in the subsequent steps, thereby affecting the filling effect.
Further, the second photoresist layer uses a dry film photoresist.
As can be seen from the above description, the use of the dry film photoresist can avoid photoresist flow into the through hole by coating, and can shorten the time of the subsequent ICP microetching process.
The above method for improving edge collapse in gallium arsenide via etching process is illustrated by the following specific examples:
example 1
The method of the embodiment comprises the following steps:
s1, please refer to FIG. 4 (a), which is a schematic diagram of the back side of the wafer, a metal layer is sputtered on the back side (back side) of the wafer after the front side process is completed.
In this embodiment, the material of the metal layer is gold (Au). The thickness of the metal layer was 4500A.
S2, referring to fig. 4 (b), a first photoresist layer is coated on the metal layer, wherein the thickness of the first photoresist layer is 14 μm. And removing the first photoresist layer at the position of the through hole to be etched through alignment development, and exposing the metal layer at the position.
In other embodiments, dry film resists may also be used for the first resist layer.
And S3, etching the metal layer at the position of the through hole to be etched to expose the surface of the back of the wafer.
The method adopted is wet etching, and the etching time is 60s. The wet etching is isotropic etching, and the etching morphology is shown in fig. 4 (c).
TABLE 1 comparison of the effects of different processing times for Metal etching procedures
By optimizing the parameters, the undercut of the metal can be reduced, and the edge chipping degree generated in the step S4 is reduced.
S4, referring to fig. 4 (d), the metal on the front side of the wafer is below, ICP etching is performed from the back of the wafer to etch the through holes, the etching depth is 150 μm, and edge breakage occurs.
S5, removing the first photoresist layer and the metal layer, wherein the edge collapse morphology is shown in the accompanying drawings (4 e) and (5 a).
The photoresist was removed by soaking in NMP (n-methylpyrrolidone) solution. The metal layer is removed by immersion in an etchant, in this example, a potassium iodide solution.
And S6, coating Polyimide (PI) on the surface of the back of the crystal, and filling the edge-collapse holes, so that the problem that the high-frequency performance of the device is not ideal and the service life is influenced due to the fact that sputtering and electroplating metals fill the holes in the subsequent metal wiring process is avoided. The coating thickness of PI on the surface of the back of the wafer was 5 μm.
At this time, some PI flows to the bottom of the through hole, and no processing will affect the interconnection between the metal sputtered and electroplated later and the metal on the front surface of the wafer, as shown in fig. 5 (b).
S7, referring to fig. 5 (c), a second photoresist layer is attached to the surface of the back of the wafer, and the second photoresist layer at the through hole is removed through alignment development to expose the through hole. The photoresist material of the second photoresist layer may be a liquid photoresist or a dry film photoresist. Because the via is etched, the liquid photoresist is coated to cause a large amount of photoresist to flow into the via. In order to shorten the time for the subsequent ICP microetching, a dry film resist is preferable. The thickness of the dry film photoresist is generally thicker, and can meet the requirements within the range of 14-150 mu m.
S8, referring to fig. 5 (d), polyimide at the bottom of the through hole is removed by adopting an ICP microetching mode, and the step is overetching, so that the polyimide is ensured to be removed cleanly.
S9, referring to fig. 5 (e), the second photoresist layer is removed, and the subsequent metal sputtering and electroplating processes are performed. In this embodiment, sputtering is seed gold and electroplating is growing a thickness on the seed gold.
Example two
The method of the embodiment comprises the following steps:
s1, sputtering a metal layer on the surface of the crystal back with the front surface process completed.
In this embodiment, the material of the metal layer is tungsten-titanium alloy (TiW). The thickness of the metal layer was 2000A.
S2, coating a first photoresist layer on the metal layer, wherein the thickness of the first photoresist layer is 28 mu m. And removing the first photoresist layer at the position of the through hole to be etched through alignment development, and exposing the metal layer at the position.
And S3, etching the metal layer at the position of the through hole to be etched to expose the surface of the back of the wafer.
The method adopted is wet etching, and the etching time is 40s.
And S4, performing ICP etching on the through hole from the back of the wafer, wherein the etching depth is 120 mu m, and edge breakage is generated.
S5, removing the first photoresist layer and the metal layer.
S6, coating PI on the surface of the back of the wafer, and filling the edge-collapse holes, so that the problem that the high-frequency performance of the device is not ideal and the service life is influenced due to the fact that sputtering and electroplating metals fill the holes in the subsequent metal wiring working procedure is avoided. The coating thickness of PI on the surface of the back of the wafer was 7 μm.
At this time, some PI flows to the bottom of the via hole, and no processing will affect the interconnection between the metal sputtered and electroplated subsequently and the metal on the front surface of the wafer.
And S7, attaching a dry film photoresist layer on the surface of the wafer back, and removing the dry film photoresist layer at the through hole through alignment development to expose the through hole.
And S8, removing polyimide at the bottom of the through hole by adopting an ICP microetching mode, wherein the step is overetching, and the polyimide is ensured to be removed cleanly.
S9, removing the second photoresist layer, and performing subsequent metal sputtering and electroplating processes.
Example III
The method of the embodiment comprises the following steps:
s1, sputtering a metal layer on the surface of the crystal back with the front surface process completed.
In this embodiment, the material of the metal layer is a metal combination layer of tungsten (W) and titanium (Ti). The thickness of the metal combined layer was 5000A.
S2, coating a first photoresist layer on the metal layer, wherein the thickness of the first photoresist layer is 20 mu m. And removing the first photoresist layer at the position of the through hole to be etched through alignment development, and exposing the metal combination layer at the position.
And S3, etching the metal combination at the through hole to be etched to expose the surface of the back of the wafer.
The method adopted is wet etching, and the etching time is 80s.
And S4, performing ICP etching on the through hole from the back of the wafer, wherein the etching depth is 250 mu m, and edge breakage is generated.
S5, removing the first photoresist layer and the metal layer.
S6, coating PI on the surface of the back of the wafer, and filling the edge-collapse holes, so that the problem that the high-frequency performance of the device is not ideal and the service life is influenced due to the fact that sputtering and electroplating metals fill the holes in the subsequent metal wiring working procedure is avoided. The coating thickness of PI on the surface of the back of the wafer was 5 μm.
At this time, some PI flows to the bottom of the via hole, and no processing will affect the interconnection between the metal sputtered and electroplated subsequently and the metal on the front surface of the wafer.
And S7, attaching a dry film photoresist layer on the surface of the wafer back, and removing the dry film photoresist layer at the through hole through alignment development to expose the through hole.
And S8, removing polyimide at the bottom of the through hole by adopting an ICP microetching mode, wherein the step is overetching, and the polyimide is ensured to be removed cleanly.
S9, removing the second photoresist layer, and performing subsequent metal sputtering and electroplating processes.
After testing, the wafers obtained by using the methods described in embodiments one to three have no abnormal morphology, and the high-frequency performance and the service life of the devices obtained by further processing meet the product standards.
The invention has the following advantages:
1. the photoresist layer and the metal layer are combined to be used as a mask, so that the appearance problem caused by insufficient thickness of the photoresist or excessive thickness of the photoresist is avoided, the metal etching time is optimized, the side etching is reduced, and the edge breakage is improved.
2. The PI is used for filling the holes formed by the edge breakage, so that abnormal appearance caused by the edge breakage holes during metal wiring can be avoided.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent changes made by the specification and drawings of the present invention, or direct or indirect application in the relevant art, are included in the scope of the present invention.
Claims (10)
1. The method for improving edge breakage in gallium arsenide through hole etching process is characterized by comprising the following steps:
s1, sputtering a metal layer on the surface of the crystal back with the front surface process completed;
s2, attaching a first photoresist layer on the metal layer, and removing the first photoresist layer at the position of the through hole to be etched through alignment development;
s3, etching the metal layer at the through hole to be etched;
s4, performing ICP etching on the through hole to generate edge breakage;
s5, removing the first photoresist layer and the metal layer;
and S6, coating polyimide on the surface of the crystal back for filling holes formed by edge collapse.
2. The method for improving edge chipping in a gallium arsenide via etching process of claim 1, wherein: the method also comprises the steps of:
s7, attaching a second photoresist layer on the surface of the wafer back, and removing the second photoresist layer at the through hole through alignment development;
s8, removing polyimide flowing into the bottoms of the through holes in the step S6 by adopting an ICP microetching mode, so as to ensure that polyimide is removed cleanly;
s9, removing the second photoresist layer, and performing subsequent procedures.
3. The method for improving edge chipping in a gallium arsenide via etching process of claim 1, wherein: in the step S2, the material of the metal layer is one or more selected from tungsten, titanium, gold, and tungsten-titanium alloy.
4. The method for improving edge chipping in a gallium arsenide via etching process according to claim 3 wherein: the thickness of the metal layer is 2000A-5000A.
5. The method for improving edge chipping in a gallium arsenide via etching process of claim 1, wherein: in the step S3, the metal layer at the position of the through hole to be etched is etched by wet etching.
6. The method for improving edge chipping in a gallium arsenide via etching process of claim 5, wherein: the etching time is 40s-80s.
7. The method for improving edge chipping in a gallium arsenide via etching process of claim 1, wherein: in the step S2, the thickness of the first photoresist layer is 14 μm to 28 μm.
8. The method for improving edge chipping in a gallium arsenide via etching process of claim 1, wherein: in the step S4, the depth of the through hole is 120-250 μm.
9. The method for improving edge chipping in a gallium arsenide via etching process of claim 1, wherein: in the step S6, the polyimide is coated on the surface of the back of the wafer to a thickness of not less than 5 μm.
10. The method for improving edge chipping in a gallium arsenide via etching process of claim 1, wherein: the second photoresist layer uses a dry film photoresist.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310063614.3A CN116364649A (en) | 2023-01-12 | 2023-01-12 | Method for improving edge breakage in gallium arsenide through hole etching process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310063614.3A CN116364649A (en) | 2023-01-12 | 2023-01-12 | Method for improving edge breakage in gallium arsenide through hole etching process |
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| CN202310063614.3A Pending CN116364649A (en) | 2023-01-12 | 2023-01-12 | Method for improving edge breakage in gallium arsenide through hole etching process |
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