CN110797257A - Graph transmission method - Google Patents
Graph transmission method Download PDFInfo
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- CN110797257A CN110797257A CN201911120598.7A CN201911120598A CN110797257A CN 110797257 A CN110797257 A CN 110797257A CN 201911120598 A CN201911120598 A CN 201911120598A CN 110797257 A CN110797257 A CN 110797257A
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- hard mask
- mask layer
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- semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Abstract
The invention provides a graph transmission method, which comprises the following steps: providing a semiconductor substrate, and sequentially forming a hard mask layer and a graphical extreme ultraviolet photoresist layer on the semiconductor substrate; etching the hard mask layer by taking the graphical extreme ultraviolet photoresist layer as a mask, and transferring a graph in the graphical extreme ultraviolet photoresist layer into the hard mask layer to form a graphical hard mask layer, wherein the graphical hard mask layer is provided with an opening; forming a filling layer in the opening; and removing the hard mask layer to expose the semiconductor substrate, wherein the filling layer in the opening is reserved on the semiconductor substrate to realize negative transmission of the low-density pattern in the patterned extreme ultraviolet photoresist layer.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a pattern transfer method.
Background
The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in one generation of ICs, each of which has smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per unit of chip area) has generally increased while geometry (i.e., the smallest element or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling down also increases the complexity of IC processing and manufacturing. To achieve these advances, similar developments in IC processing and fabrication are required. For example, there is an increasing demand for implementing higher resolution photolithography processes. One Lithography technique is Extreme Ultraviolet Lithography (EUV), and other techniques include X-ray Lithography, ion beam projection Lithography, electron beam projection Lithography, and multi-electron beam maskless Lithography.
EUV is a next generation lithography technique using extreme ultraviolet wavelengths, e.g. 13.5nm, and in particular, for many critical levels, lithographic patterning to pattern smaller technology nodes would require EUV. However, due to the random effect of the EUV photoresist, that is, the fluctuation of the number of illuminating photons, in the EUV process, when the trench line width design requirement is too small, the defect of EUV photoresist bridging is likely to occur, and when the trench line width design requirement is too large, the defect of EUV photoresist fracture is likely to occur. Due to the technical limitation of defects caused by random effects, the conventional extreme ultraviolet lithography process is generally only applied to low-density patterning processes, such as various cutting processes, a channel process of a back-end metal wire and the like, the developing area is small, the yield is high, but the negative transfer of the low-density pattern (namely, the retention of the low-density pattern extreme ultraviolet photoresist and the removal of the extreme ultraviolet photoresist in other areas) cannot be realized.
Disclosure of Invention
The invention aims to provide a pattern transfer method to solve the problem that negative transfer of a low-density pattern cannot be realized in an extreme ultraviolet lithography process.
In order to solve the above problems, the present invention provides a graphics transfer method, comprising the steps of:
providing a semiconductor substrate, and sequentially forming a hard mask layer and a graphical extreme ultraviolet photoresist layer on the semiconductor substrate;
etching the hard mask layer by taking the graphical extreme ultraviolet photoresist layer as a mask, and transferring a graph in the graphical extreme ultraviolet photoresist layer into the hard mask layer to form a graphical hard mask layer, wherein the graphical hard mask layer is provided with an opening;
forming a filling layer in the opening; and
and removing the hard mask layer to expose the semiconductor substrate, wherein the filling layer in the opening is reserved on the semiconductor substrate.
Optionally, the hard mask layer includes a first hard mask layer and a second hard mask layer sequentially formed on the semiconductor substrate.
Further, with the patterned extreme ultraviolet photoresist layer as a mask, etching the hard mask layer, and transferring the pattern in the patterned extreme ultraviolet photoresist layer into the hard mask layer to form a patterned hard mask layer, wherein the patterned hard mask layer has an opening, and the method comprises the following steps:
sequentially carrying out dry etching on the second hard mask layer by taking the patterned extreme ultraviolet photoresist layer as a mask, and transferring the pattern in the patterned extreme ultraviolet photoresist layer into the second hard mask layer to form a patterned second hard mask layer;
and taking the graphical extreme ultraviolet photoresist layer and the graphical second hard mask layer as masks, carrying out dry etching on the first hard mask layer, and transferring the graph into the first hard mask layer to form a graphical first hard mask layer.
Further, the step of forming a filling layer in the opening comprises the following steps:
forming a filling layer on the semiconductor substrate, wherein the filling layer fills the opening and covers the upper surface of the second hard mask layer; and
and sequentially carrying out dry etching on the filling layer and the second hard mask layer to expose the first hard mask layer, wherein the filling layer only fills the opening.
Further, the filling layer includes low temperature silicon oxide.
Further, the thickness of the filling layer covering the upper surface of the second hard mask layer is within
In the meantime.
Further, removing the hard mask layer to expose the semiconductor substrate, wherein the step of leaving the filling layer in the opening on the semiconductor substrate comprises:
and ashing by using an ashing process to remove the first hard mask layer so as to expose the semiconductor substrate, wherein the filling layer in the opening is reserved on the semiconductor substrate.
Further, the first hard mask layer includes an amorphous carbon layer, and the second hard mask layer includes a silicide layer.
Further, the first hard mask layer has a thickness ofWherein the second hard mask layer has a thickness of
In the meantime.
Furthermore, the thickness of the patterned extreme ultraviolet photoresist layer is within
In the meantime.
Compared with the prior art, the method has the following beneficial effects:
the invention provides a graph transmission method, which comprises the following steps: providing a semiconductor substrate, and sequentially forming a hard mask layer and a graphical extreme ultraviolet photoresist layer on the semiconductor substrate; etching the hard mask layer by taking the graphical extreme ultraviolet photoresist layer as a mask, and transferring a graph in the graphical extreme ultraviolet photoresist layer into the hard mask layer to form a graphical hard mask layer, wherein the graphical hard mask layer is provided with an opening; forming a filling layer in the opening; and removing the hard mask layer to expose the semiconductor substrate, wherein the filling layer in the opening is reserved on the semiconductor substrate to realize negative transmission of the low-density pattern in the patterned extreme ultraviolet photoresist layer.
Furthermore, the hard mask layer comprises a first hard mask layer and a second hard mask layer which are sequentially formed on the semiconductor substrate, the first hard mask layer comprises an amorphous carbon layer, and the first hard mask layer and the second hard mask layer are jointly used as the hard mask layers which have better compactness and can improve the roughness of the line width of the pattern in the subsequent pattern transfer process, so that the quality of the pattern is improved.
Drawings
FIG. 1 is a flowchart illustrating a method for delivering graphics according to an embodiment of the present invention;
fig. 2a-2f are schematic structural diagrams of steps of a graphics transfer method according to an embodiment of the invention.
Description of reference numerals:
100-a semiconductor substrate;
200-a hard mask layer; 200 a-patterning an opening of the hard mask layer; 210-a first hard mask layer; 220-a second hard mask layer; 220 a-patterning an opening of the second hard mask layer;
300-patterning the extreme ultraviolet photoresist layer; 300 a-patterning an opening of the extreme ultraviolet photoresist layer;
400-a filling layer.
Detailed Description
The core idea provided by the invention is to provide a pattern transfer method, and the forming method of the semiconductor device comprises the following steps: providing a semiconductor substrate, and sequentially forming a hard mask layer and a graphical extreme ultraviolet photoresist layer on the semiconductor substrate; etching the hard mask layer by taking the graphical extreme ultraviolet photoresist layer as a mask, and transferring a graph in the graphical extreme ultraviolet photoresist layer into the hard mask layer to form a graphical hard mask layer, wherein the graphical hard mask layer is provided with an opening; forming a filling layer in the opening; and removing the hard mask layer to expose the semiconductor substrate, wherein the filling layer in the opening is reserved on the semiconductor substrate to realize negative transmission of the low-density pattern in the patterned extreme ultraviolet photoresist layer.
Furthermore, the hard mask layer comprises a first hard mask layer and a second hard mask layer which are sequentially formed on the semiconductor substrate, the first hard mask layer comprises an amorphous carbon layer, and the first hard mask layer and the second hard mask layer are jointly used as the hard mask layers which have better compactness and can improve the roughness of the line width of the pattern in the subsequent pattern transfer process, so that the quality of the pattern is improved.
A method of delivering graphics of the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
The embodiment provides a graph transmission method. Fig. 1 is a flowchart illustrating a graphics transfer method according to this embodiment. As shown in fig. 1, the graphic delivery method includes the steps of:
step S10: providing a semiconductor substrate, and sequentially forming a hard mask layer and a graphical extreme ultraviolet photoresist layer on the semiconductor substrate;
step S20: etching the hard mask layer by taking the graphical extreme ultraviolet photoresist layer as a mask, and transferring a graph in the graphical extreme ultraviolet photoresist layer into the hard mask layer to form a graphical hard mask layer, wherein the graphical hard mask layer is provided with an opening;
step S30: forming a filling layer in the opening; and
step S40: and removing the hard mask layer to expose the semiconductor substrate, wherein the filling layer in the opening is reserved on the semiconductor substrate.
The method of pattern transfer according to the present invention is described in detail below with reference to specific embodiments and figures 2a-2 f.
Fig. 2a is a schematic structural diagram of the semiconductor device provided in this embodiment. As shown in fig. 2a, step S10 is first performed to provide a semiconductor substrate 100, and a hard mask layer 200 and a patterned euv photoresist layer 300 are sequentially formed on the semiconductor substrate 100.
The method specifically comprises the following steps:
first, a semiconductor substrate 100 is provided, and a hard mask layer 200 is formed on the semiconductor substrate 100. The hard mask layer 200 includes, for example, a first hard mask layer 210 and a second hard mask layer 220 sequentially formed on the semiconductor substrate 100.
In the present embodiment, the semiconductor substrate 100 may provide an operation platform for a subsequent process, and may be any substrate known to those skilled in the art for carrying components of a semiconductor integrated circuit, such as a bare chip, or a wafer processed by an epitaxial growth process, and in detail, the substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator (ge) substrate. The first hard mask layer 210 is, for example, an amorphous carbon layer that can be used as a hard mask layer for etching the semiconductor substrate 100 to form very small and closely spaced patterns. The thickness of the first hard mask layer 210 is, for example, as
The second hard mask layer 220 is, for example, a silicide layer, specifically, a silicon oxide layer, a silicon carbide layer, nitrogenA silicon oxide layer, or a stack thereof, or a silicon oxide-silicon nitride-silicon oxide stack, and the thickness of the second hard mask layer 220 is, for example
The dense masks of the first hard mask layer 210 and the second hard mask layer 220 are used as hard mask layers together, and the compactness of the hard mask layers is good, so that the line width roughness of a pattern in the subsequent pattern transmission process can be improved, and the quality of the pattern is improved.
Next, a patterned euv photoresist layer 300 is formed on the hard mask layer 200 through an euv lithography process such as coating, exposure, and development. The thickness of the patterned EUV photoresist layer 300 is, for example
The pattern of the patterned euv photoresist layer 300 has an opening 300 a.
Other structural layers (not shown) are formed between the hard mask layer 200 and the patterned euv photoresist layer 300, such as a silicon oxide layer having a thickness of, for example
FIG. 2b is a schematic structural diagram after etching the second hard mask layer. FIG. 2c is a schematic diagram of the structure after forming a patterned hard mask layer. As shown in fig. 2b and 2c, next, step S20 is performed, the hard mask layer 200 is etched using the patterned euv photoresist layer 300 as a mask, and the pattern in the patterned euv photoresist layer 300 is transferred into the hard mask layer 200 to form the patterned hard mask layer 200, so that the forward transfer of the low-density pattern in the patterned euv photoresist layer 300 is realized. Wherein the patterned hard mask layer 200 has an opening 200a, and the opening 200a is located directly below the opening 300 a.
The method specifically comprises the following steps:
as shown in fig. 2b, first, the patterned euv photoresist layer 300 is used as a mask, the second hard mask layer 220 is sequentially etched, and the pattern in the patterned euv photoresist layer 300 is transferred into the second hard mask layer 220 to form the patterned second hard mask layer 220, wherein the patterned second hard mask layer 220 has an opening 220a, the opening 220a is located right below the opening 300a, and the opening 220a exposes the first hard mask layer 210. This step is to etch the second hard mask layer 220 by, for example, a dry etching process.
As shown in fig. 2c, next, using the patterned euv photoresist layer 300 and the patterned second hard mask layer 220 as masks, etching the first hard mask layer 210, and transferring the pattern into the first hard mask layer 210 to form a patterned first hard mask layer 210, where the patterned first hard mask layer 210 has an opening 210a, the opening 210a is located right below the opening 220a, and the opening 210a exposes the semiconductor substrate 100, and at this time, the patterned euv photoresist layer 300 is consumed. The opening 210a and the opening 220a together form an opening 200a of the patterned hard mask layer 200. This step is to etch the first hard mask layer 210, for example, still by a dry etching process.
Fig. 2d is a schematic structural diagram after forming a filling layer. Fig. 2e is a schematic structural diagram after the filling layer is etched. As shown in fig. 2d and 2e, step S30 is performed next, and a filling layer is formed in the opening 200a, specifically, in the opening 210 a.
The method specifically comprises the following steps:
as shown in fig. 2d, first, a filling layer 400 is formed on the semiconductor substrate 100, and the filling layer 400 fills the opening 200a, and at the same time, the filling layer 400 also covers the surface of the second hard mask layer 220 on the side away from the semiconductor substrate 100, that is, the filling layer 400 also covers the upper surface of the second hard mask layer 220. The thickness of the filling layer 400 covering the upper surface of the second hard mask layer 220 is, for example, such that
Wherein the filling layer 400 is, for example, low temperature silicon oxide (LTO, low te)mperature Oxide)。
As shown in fig. 2e, the filling layer 400 and the second hard mask layer 220 are sequentially etched to expose the first hard mask layer 210, and at this time, the filling layer 400 only fills the opening 210 a. This step is, for example, to etch the filling layer 400 and the second hard mask layer 220 also by a dry etching process.
Fig. 2f is a schematic structural diagram after forming a filling layer. As shown in fig. 2f, step S40 is performed to remove the hard mask layer to expose the semiconductor substrate 100, and the filling layer 400 in the opening 200a (specifically, the opening 210a) is remained on the semiconductor substrate 100 to realize the negative transfer of the low-density pattern in the patterned euv photoresist layer 300.
This step is, for example, to remove the first hard mask layer 210 by ashing process (ashing) to expose the semiconductor substrate 100, wherein only the filling layer 400 at the opening 210a remains on the semiconductor substrate 100, and the filling layer 400 at the opening 210a is used as a mask for the subsequent processes.
In summary, the present invention provides a method for transferring a graphic, including the following steps: providing a semiconductor substrate, and sequentially forming a hard mask layer and a graphical extreme ultraviolet photoresist layer on the semiconductor substrate; etching the hard mask layer by taking the graphical extreme ultraviolet photoresist layer as a mask, and transferring a graph in the graphical extreme ultraviolet photoresist layer into the hard mask layer to form a graphical hard mask layer, wherein the graphical hard mask layer is provided with an opening; forming a filling layer in the opening; and removing the hard mask layer to expose the semiconductor substrate, wherein the filling layer in the opening is reserved on the semiconductor substrate to realize negative transmission of the low-density pattern in the patterned extreme ultraviolet photoresist layer.
Furthermore, the hard mask layer comprises a first hard mask layer and a second hard mask layer which are sequentially formed on the semiconductor substrate, the first hard mask layer comprises an amorphous carbon layer, and the first hard mask layer and the second hard mask layer are jointly used as the hard mask layers which have better compactness and can improve the roughness of the line width of the pattern in the subsequent pattern transfer process, so that the quality of the pattern is improved.
In addition, it should be noted that the description of the terms "first", "second", and the like in the specification is only used for distinguishing each component, element, step, and the like in the specification, and is not used for representing a logical relationship or a sequential relationship between each component, element, step, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. A method of graphical delivery, comprising the steps of:
providing a semiconductor substrate, and sequentially forming a hard mask layer and a graphical extreme ultraviolet photoresist layer on the semiconductor substrate;
etching the hard mask layer by taking the graphical extreme ultraviolet photoresist layer as a mask, and transferring a graph in the graphical extreme ultraviolet photoresist layer into the hard mask layer to form a graphical hard mask layer, wherein the graphical hard mask layer is provided with an opening;
forming a filling layer in the opening; and
and removing the hard mask layer to expose the semiconductor substrate, wherein the filling layer in the opening is reserved on the semiconductor substrate.
2. The pattern transfer method according to claim 1, wherein the hard mask layer comprises a first hard mask layer and a second hard mask layer which are sequentially formed on the semiconductor substrate.
3. The pattern transfer method according to claim 2, wherein the step of etching the hard mask layer using the patterned euv photoresist layer as a mask and transferring the pattern in the patterned euv photoresist layer into the hard mask layer to form a patterned hard mask layer, the patterned hard mask layer having an opening comprises the steps of:
sequentially carrying out dry etching on the second hard mask layer by taking the patterned extreme ultraviolet photoresist layer as a mask, and transferring the pattern in the patterned extreme ultraviolet photoresist layer into the second hard mask layer to form a patterned second hard mask layer;
and taking the graphical extreme ultraviolet photoresist layer and the graphical second hard mask layer as masks, carrying out dry etching on the first hard mask layer, and transferring the graph into the first hard mask layer to form a graphical first hard mask layer.
4. The pattern transfer method according to claim 3, wherein forming a filling layer in the opening comprises the steps of:
forming a filling layer on the semiconductor substrate, wherein the filling layer fills the opening and covers the upper surface of the second hard mask layer; and
and sequentially carrying out dry etching on the filling layer and the second hard mask layer to expose the first hard mask layer, wherein the filling layer only fills the opening.
5. The pattern transfer method according to claim 4, wherein the filling layer comprises low temperature silicon oxide.
6. The pattern transfer method according to claim 5, wherein the thickness of the filling layer covering the upper surface of the second hard mask layer is set to be equal toIn the meantime.
7. The pattern transfer method of claim 6, wherein removing the hard mask layer to expose the semiconductor substrate, the leaving the fill layer in the opening on the semiconductor substrate comprises:
and ashing by using an ashing process to remove the first hard mask layer so as to expose the semiconductor substrate, wherein the filling layer in the opening is reserved on the semiconductor substrate.
8. The pattern transfer method according to claim 7, wherein the first hard mask layer comprises an amorphous carbon layer and the second hard mask layer comprises a silicide layer.
9. The pattern transfer method of claim 8, wherein the first hard mask layer has a thickness in the range of
Wherein the second hard mask layer has a thickness of
In the meantime.
10. The pattern transfer method of claim 9, wherein the patterned euv photoresist layer has a thickness of
In the meantime.
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| CN201911120598.7A CN110797257A (en) | 2019-11-15 | 2019-11-15 | Graph transmission method |
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| CN201911120598.7A CN110797257A (en) | 2019-11-15 | 2019-11-15 | Graph transmission method |
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| CN106486343A (en) * | 2015-08-31 | 2017-03-08 | 台湾积体电路制造股份有限公司 | Method for integrated circuit patterns |
| US20170194195A1 (en) * | 2015-12-31 | 2017-07-06 | International Business Machines Corporation | Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch |
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| CN1750234A (en) * | 2004-06-22 | 2006-03-22 | 三星电子株式会社 | Form the method for fine pattern of semiconductor device and form the method for contact with it |
| CN102201365A (en) * | 2010-03-22 | 2011-09-28 | 中芯国际集成电路制造(上海)有限公司 | Method for producing semiconductor device |
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Application publication date: 20200214 |