CN111293039A - Method for forming self-aligned double patterning semiconductor device - Google Patents

Method for forming self-aligned double patterning semiconductor device Download PDF

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Publication number
CN111293039A
CN111293039A CN202010251531.3A CN202010251531A CN111293039A CN 111293039 A CN111293039 A CN 111293039A CN 202010251531 A CN202010251531 A CN 202010251531A CN 111293039 A CN111293039 A CN 111293039A
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China
Prior art keywords
layer
graphic
forming
pattern
self
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CN202010251531.3A
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Chinese (zh)
Inventor
叶滋婧
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202010251531.3A priority Critical patent/CN111293039A/en
Publication of CN111293039A publication Critical patent/CN111293039A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask

Abstract

The invention provides a method for forming a self-aligned double-patterning semiconductor device, which comprises the steps of forming a patterned photoresist layer on an anti-reflection layer, wherein the patterned photoresist layer defines a first pattern and a second pattern; and etching the anti-reflection layer and the core layer by taking the patterned photoresist layer as a mask to form a first graph layer and a second graph layer, wherein the first graph layer comprises part of the core layer. The second graphic layer comprises a partial core layer and a partial anti-reflection layer covering the partial core layer; forming side walls on two sides of the first graphic layer and the second graphic layer respectively; removing the first graphic layer; etching the film layer to be etched by taking the side wall and the second pattern layer as masks; and removing the side wall and the second graphic layer to form a self-aligned dual graphic. Thus, a self-aligned double pattern is formed by a patterned photoresist layer.

Description

Method for forming self-aligned double patterning semiconductor device
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a self-aligned double-patterning semiconductor device.
Background
As semiconductor integrated circuit technology continues to develop, requiring more circuit devices to be integrated onto a smaller chip area, semiconductor circuit device sizes are becoming smaller, i.e., requiring photolithographic processes to produce smaller line width feature sizes. However, since the wavelength of the light source in the photolithography process for determining the device size is approaching the technological limit that it can be reduced, the device size is approaching the limit resolution of the exposure tool and cannot be reduced without limit. As the feature size of semiconductor processes is continuously reduced, in order to improve the integration of semiconductor devices, various dual layer Patterning processes have been proposed, wherein a Self-Aligned Double Patterning (SADP) process is one of the processes.
The resolution limit problem of the photoetching process can be solved by utilizing a double patterning technical method to form a smaller pattern size. The method is to increase the integration level of the circuit by two times by using the limit of the resolution of the photoetching process, namely, to divide the design pattern exceeding the limit resolution of the photoetching machine into two layers of patterns with the resolution which can be reached by the photoetching machine, and to increase the pattern density by one time by using two photoetching plates and sequentially carrying out photoetching processes twice on the same substrate. In the prior art, when two core pattern layers with different sizes are formed on the same core layer in a semiconductor device, a small-size core pattern and a large-size core pattern are subjected to two exposure processes, that is, two masks are required to be successively and separately formed when the small-size core pattern and the large-size core pattern are formed.
Disclosure of Invention
The invention aims to provide a method for forming a self-aligned double patterning semiconductor device, which solves the problem that two photomasks are needed in a self-aligned double patterning process.
To solve the above technical problem, the present invention provides a method for forming a self-aligned double patterning semiconductor device, comprising:
providing a semiconductor substrate, and forming a film layer to be etched, a core layer and an anti-reflection layer which are stacked in sequence on the semiconductor substrate;
forming a patterned photoresist layer on the anti-reflective layer, the patterned photoresist layer defining a first pattern and a second pattern;
etching the anti-reflection layer and the core layer by taking the patterned photoresist layer as a mask to form a first graphic layer and a second graphic layer, wherein the first graphic layer comprises a part of the core layer, and the second graphic layer comprises a part of the core layer and a part of the anti-reflection layer covering the part of the core layer;
forming side walls on two sides of the first graphic layer and the second graphic layer respectively;
removing the first graphic layer;
etching the film layer to be etched by taking the side wall and the second pattern layer as masks; and the number of the first and second groups,
and removing the side wall and the second graphic layer to form a self-aligned dual graphic.
In the method for forming the self-aligned double patterning semiconductor device, the size of the first pattern is smaller than that of the second pattern.
Optionally, in the method for forming a self-aligned dual-patterning semiconductor device, the anti-reflection layer is formed on the core layer by a deposition method.
Optionally, in the method for forming a self-aligned dual patterning semiconductor device, the material of the anti-reflection layer is an inorganic oxynitride or an inorganic oxycarbide.
Optionally, in the method for forming a self-aligned double-patterning semiconductor device, the core layer is formed on the film layer to be etched by a deposition method.
Optionally, in the method for forming a self-aligned double-patterned semiconductor device, the material of the core layer is any one or a combination of any more of amorphous carbon, a dielectric film and a metal film.
Optionally, in the method for forming a self-aligned dual-patterned semiconductor device, the first patterned layer includes a partial core layer and the second patterned layer includes a partial core layer and a partial anti-reflection layer covering the partial core layer by a loading effect generated when the core layer is etched.
Optionally, in the method for forming a self-aligned double patterning semiconductor device, the first pattern layer is removed by an ashing process.
Optionally, in the method for forming a self-aligned double patterning semiconductor device, the forming of the sidewall includes:
forming side wall dielectric layers on the top surface and two side surfaces of the first graphic layer and the second graphic layer respectively;
and removing the side wall dielectric layer on the top surfaces of the first graphic layer and the second graphic layer to form the side wall.
Optionally, in the method for forming a self-aligned double patterning semiconductor device, the material of the spacer dielectric layer is silicon nitride.
In the method for forming the self-aligned double-patterning semiconductor device, a film layer to be etched, a core layer and an anti-reflection layer which are sequentially stacked are formed on a semiconductor substrate; forming a patterned photoresist layer on the anti-reflective layer, the patterned photoresist layer defining a first pattern and a second pattern; enabling the first graph and the second graph to be located on the same photoresist layer, and etching the anti-reflection layer and the core layer by taking the patterned photoresist layer as a mask to form a first graph layer and a second graph layer, wherein the first graph layer comprises a part of the core layer, and the second graph layer comprises a part of the core layer and a part of the anti-reflection layer covering the part of the core layer; forming side walls on two sides of the first graphic layer and the second graphic layer respectively; removing the first graphic layer; and etching the film layer to be etched by taking the side wall and the second pattern layer as masks, and removing the side wall and the second pattern layer to form a self-aligned double pattern. That is, the self-aligned double pattern is formed through a patterned photoresist layer, and further, since only a patterned photoresist layer is used, the self-aligned double pattern is formed through one photomask. Therefore, the self-aligned double patterning process is simplified, the material is saved, and the efficiency is improved.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for forming a self-aligned dual-pattern semiconductor device according to an embodiment of the present invention;
fig. 2 to 7 are schematic structural diagrams formed in a method for forming a self-aligned dual pattern semiconductor device according to an embodiment of the present invention;
wherein the reference numerals are as follows:
100-a semiconductor substrate; 110-a film layer to be etched; 120-a core layer; 130-an anti-reflection layer; 140-a patterned photoresist layer; 150-a first graphics layer; 160-a second graphics layer; 170-side walls; 170 a-first graphic layer side wall; 170 b-second pattern layer sidewall.
Detailed Description
The method for forming a self-aligned double-patterned semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The core of the invention is to provide a method for forming a self-aligned double-patterning semiconductor device, wherein a film layer to be etched, a core layer and an anti-reflection layer which are sequentially stacked are formed on a semiconductor substrate; forming a patterned photoresist layer on the anti-reflective layer, the patterned photoresist layer defining a first pattern and a second pattern; enabling the first graph and the second graph to be located on the same photoresist layer, and etching the anti-reflection layer and the core layer by taking the patterned photoresist layer as a mask to form a first graph layer and a second graph layer, wherein the first graph layer comprises a part of the core layer, and the second graph layer comprises a part of the core layer and a part of the anti-reflection layer covering the part of the core layer; forming side walls on two sides of the first graphic layer and the second graphic layer respectively; removing the first graphic layer; and etching the film layer to be etched by taking the side wall and the second pattern layer as masks, and removing the side wall and the second pattern layer to form a self-aligned double pattern. That is, the self-aligned double pattern is formed through a patterned photoresist layer, and further, since only a patterned photoresist layer is used, the self-aligned double pattern is formed through one photomask. Therefore, the self-aligned double patterning process is simplified, the material is saved, and the efficiency is improved.
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a schematic flow chart illustrating a method for forming a self-aligned dual-pattern semiconductor device according to an embodiment of the invention. As shown in fig. 1, the present invention provides a method for forming a self-aligned dual pattern semiconductor device, which specifically includes:
step S1: providing a semiconductor substrate, and forming a film layer to be etched, a core layer and an anti-reflection layer which are stacked in sequence on the semiconductor substrate;
step S2: forming a patterned photoresist layer on the anti-reflection layer, the patterned photoresist layer defining a first pattern and a second pattern;
step S3: etching the core layer by taking the photoresist layer as a mask to form a first graphic layer and a second graphic layer, wherein the first graphic layer comprises a part of the core layer, and the second graphic layer comprises a part of the core layer and a part of anti-reflection layer covering the part of the core layer;
step S4: forming side walls on two sides of the first graphic layer and the second graphic layer respectively;
step S5: removing the first graphic layer;
step S6: etching the film layer to be etched by taking the side wall and the second pattern layer as masks;
step S7: and removing the side wall, the second pattern layer and the anti-reflection layer to form a self-aligned double pattern.
Next, referring to fig. 2, in step S1, providing a semiconductor substrate 100, and forming a film layer to be etched 110, a core layer 120, and an anti-reflection layer 130 stacked in sequence on the semiconductor substrate 100; the material of the semiconductor substrate 100 may be silicon, germanium, silicon carbide, or the like, or may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), but is not limited thereto. The material of the film layer to be etched 110 may be polysilicon or a metal material or an oxide (oxide). The material of the core layer 120 may be any one or a combination of any more of amorphous carbon, a dielectric thin film, and a metal thin film. In the present invention, the material of the core layer 120 is preferably amorphous carbon. The anti-reflection layer 130 may be formed on the core layer 120 by a deposition method. Preferably, an anti-reflection layer 130 is formed on the core layer 120 by a chemical vapor deposition method to control the density of the anti-reflection layer 130, thereby improving the precision of the processing process. The material of the anti-reflection layer 130 may be an inorganic oxynitride or an inorganic oxycarbide.
With continued reference to fig. 2, in step S2, a patterned photoresist layer 140 is formed on the anti-reflective layer 130, wherein the patterned photoresist layer 140 defines a first pattern and a second pattern. Wherein a photoresist layer 140 including a first pattern and a second pattern may be formed on the anti-reflection layer 130 through a photolithography process. Specifically, the method for forming the photoresist layer comprises the following steps: a photomask is provided, the photomask comprises a first pattern and a second pattern, and the first pattern and the second pattern are transferred onto a photoresist film through a photolithography process by taking the photomask as a mask to form the patterned photoresist layer 140.
Referring to fig. 3, in step S3, the anti-reflection layer 130 and the core layer 120 are etched using the patterned photoresist layer 140 as a mask to form a first graphic layer 150 and a second graphic layer 160, wherein the first graphic layer 150 includes a portion of the core layer 120, and the second graphic layer 160 includes a portion of the core layer 120 and a portion of the anti-reflection layer 130 covering the portion of the core layer 120. That is, after etching, a part of the core layer of the first graphic layer 150 is exposed, and a part of the core layer of the second graphic layer 160 is covered by a part of the anti-reflection layer 130, that is, after etching, the remaining anti-reflection layer 130 covers a part of the core layer of the second graphic layer 160, that is, here, the etched anti-reflection layer only covers a part of the etched core layer. Specifically, only the second pattern layer 160 includes a partial anti-reflection layer (anti-reflection layer after etching); the first pattern layer 150 includes only a portion of the core layer (i.e., only a portion of the core layer after etching), and does not include the anti-reflection layer. Wherein the size of the first graphic is smaller than that of the second graphic, that is, the size of the cross section of the first graphic layer 150 is smaller than that of the cross section of the second graphic layer 160. The size of the first pattern and the size of the second pattern refer to the actual size, i.e., the feature size, of the first pattern layer 150 and the second pattern layer 160 formed on the semiconductor substrate. Specifically, the first graphic layer 150 includes a partial core layer and the second graphic layer 160 includes a partial core layer and a partial anti-reflection layer 130 covering the partial core layer by a loading effect generated when the core layer 120 is etched. To protect the core layer in a subsequent process through the partial anti-reflection layer 130.
Referring to fig. 4, in step S4, side walls 170 are respectively formed on two sides of the first graphic layer 150 and the second graphic layer 160, where the side walls include first graphic layer side walls 170a located on two sides of the first graphic layer and second graphic layer side walls 170b located on two sides of the second graphic layer. Specifically, the method for forming the sidewall spacers 170 includes depositing a sidewall spacer dielectric layer (not shown) on the surface of the semiconductor substrate 100. The sidewall dielectric layer covers the top surfaces and two side surfaces of the first graphic layer 150 and the second graphic layer 160, and the sidewall dielectric layer on the top surfaces of the first graphic layer 150 and the second graphic layer 160 is removed to form the sidewall 170. The sidewall dielectric layer on the top surfaces of the first pattern layer 150 and the second pattern layer 160 may be removed by dry etching, preferably, the sidewall dielectric layer is made of silicon nitride, and the sidewall dielectric layer is formed by an atomic layer deposition process. Two adjacent side walls 170 are separated from each other.
Referring to fig. 5, in step S5, the first pattern layer 150 is removed, and preferably, the first pattern layer 150 is removed by an ashing process, i.e., a portion of the core layer is removed. Wherein, since part of the dielectric anti-reflection layer 130 covers part of the core layer, the second graphic layer 160 can be prevented from being removed when the first graphic layer 150 is removed.
Referring to fig. 6, in step S6, the film layer to be etched 110 is etched by using the sidewall spacers 170 and the second pattern layer 160 as masks, so as to form a patterned film layer to be etched 110.
Referring to fig. 7, in step S7, the sidewall spacers 170 and the second pattern layer 160 are removed to form a self-aligned dual pattern.
In summary, in the method for forming a self-aligned double-patterned semiconductor device according to the embodiment of the invention, a self-aligned double pattern can be formed through a patterned photoresist layer, and only one photomask is required to form the patterned photoresist layer due to the fact that only one patterned photoresist layer is used, so that the self-aligned double pattern can be formed through one photomask. Therefore, the process of self-aligned double patterning can be simplified, materials can be saved, and efficiency can be improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A method for forming a self-aligned double patterning semiconductor device, comprising:
providing a semiconductor substrate, and forming a film layer to be etched, a core layer and an anti-reflection layer which are stacked in sequence on the semiconductor substrate;
forming a patterned photoresist layer on the anti-reflective layer, the patterned photoresist layer defining a first pattern and a second pattern;
etching the anti-reflection layer and the core layer by taking the patterned photoresist layer as a mask to form a first graphic layer and a second graphic layer, wherein the first graphic layer comprises a part of the core layer, and the second graphic layer comprises a part of the core layer and a part of the anti-reflection layer covering the part of the core layer;
forming side walls on two sides of the first graphic layer and the second graphic layer respectively;
removing the first graphic layer;
etching the film layer to be etched by taking the side wall and the second pattern layer as masks; and the number of the first and second groups,
and removing the side wall and the second graphic layer to form a self-aligned dual graphic.
2. The method of forming a self-aligned double patterned semiconductor device of claim 1 wherein the size of the first pattern is smaller than the size of the second pattern.
3. The method of forming a self-aligned double patterned semiconductor device according to claim 1, wherein the anti-reflection layer is formed on the core layer by a deposition method.
4. The method of forming a self-aligned double patterned semiconductor device according to claim 3, wherein the material of the anti-reflection layer is an inorganic oxynitride or an inorganic oxycarbide.
5. The method of claim 1, wherein the core layer is formed on the film layer to be etched by a deposition method.
6. The method of forming a self-aligned double patterned semiconductor device according to claim 1, wherein the material of the core layer is any one or a combination of any more of amorphous carbon, a dielectric film and a metal film.
7. The method as claimed in claim 1, wherein the first patterned layer includes a portion of the core layer and the second patterned layer includes a portion of the core layer and a portion of the anti-reflection layer covering the portion of the core layer by a loading effect generated when the core layer is etched.
8. The method of forming a self-aligned double patterned semiconductor device according to claim 1, wherein the first pattern layer is removed by an ashing process.
9. The method for forming a self-aligned double patterned semiconductor device according to claim 1, wherein the method for forming the sidewall spacers comprises:
forming side wall dielectric layers on the top surface and two side surfaces of the first graphic layer and the second graphic layer respectively;
and removing the side wall dielectric layer on the top surfaces of the first graphic layer and the second graphic layer to form the side wall.
10. The method of claim 9, wherein the spacer dielectric layer is formed of silicon nitride.
CN202010251531.3A 2020-04-01 2020-04-01 Method for forming self-aligned double patterning semiconductor device Pending CN111293039A (en)

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Citations (7)

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US20080220600A1 (en) * 2007-03-05 2008-09-11 Micron Technology, Inc. Semiconductor constructions, methods of forming multiple lines, and methods of forming high density structures and low density structures with a single photomask
CN101562125A (en) * 2008-04-17 2009-10-21 三星电子株式会社 Method of forming fine patterns of semiconductor device
US20100096719A1 (en) * 2008-10-22 2010-04-22 Samsung Electronics Co., Ltd. Methods of forming fine patterns in integrated circuit devices
JP2012169390A (en) * 2011-02-14 2012-09-06 Hitachi High-Technologies Corp Plasma processing method
CN103579124A (en) * 2012-08-08 2014-02-12 爱思开海力士有限公司 Method of manufacturing patterns in a semiconductor device
CN104425220A (en) * 2013-08-20 2015-03-18 中芯国际集成电路制造(上海)有限公司 Method for forming pattern
CN105762070A (en) * 2015-01-07 2016-07-13 爱思开海力士有限公司 Method of fabricating semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080220600A1 (en) * 2007-03-05 2008-09-11 Micron Technology, Inc. Semiconductor constructions, methods of forming multiple lines, and methods of forming high density structures and low density structures with a single photomask
CN101562125A (en) * 2008-04-17 2009-10-21 三星电子株式会社 Method of forming fine patterns of semiconductor device
US20100096719A1 (en) * 2008-10-22 2010-04-22 Samsung Electronics Co., Ltd. Methods of forming fine patterns in integrated circuit devices
JP2012169390A (en) * 2011-02-14 2012-09-06 Hitachi High-Technologies Corp Plasma processing method
CN103579124A (en) * 2012-08-08 2014-02-12 爱思开海力士有限公司 Method of manufacturing patterns in a semiconductor device
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Application publication date: 20200616