CN110795350A - Controllable trace debugging method and system for RISC-V processor - Google Patents
Controllable trace debugging method and system for RISC-V processor Download PDFInfo
- Publication number
- CN110795350A CN110795350A CN201911030980.9A CN201911030980A CN110795350A CN 110795350 A CN110795350 A CN 110795350A CN 201911030980 A CN201911030980 A CN 201911030980A CN 110795350 A CN110795350 A CN 110795350A
- Authority
- CN
- China
- Prior art keywords
- instruction
- debugging
- trace
- module
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3644—Software debugging by instrumenting at runtime
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a controllable trace debugging method and a system of a RISC-V processor, belonging to the field of processor debugging, aiming at solving the technical problem of how to realize the problem encountered in rapid positioning debugging and reducing the debugging period, and the technical scheme is as follows: the method comprises the following steps: s1, the upper computer generates a trace debugging instruction, an enable signal for acquiring the data of the general register and a general register address to be acquired, packs the trace debugging instruction and sends the trace debugging instruction to a PL (programmable logic device) end through a gigabit Ethernet interface; s2, the PL terminal receives a debugging trace instruction sent by the upper computer through the gigabit Ethernet module and forwards the whole debugging trace instruction to the trace instruction acquisition module; s3, the trace instruction acquisition module analyzes the debugging trace instruction; s4, judging whether an enabling signal is acquired; and S5, acquiring the instruction and the general register data and sending the instruction and the general register data back to the upper computer for analysis. The system comprises an upper computer, a gigabit Ethernet module, a tracking instruction acquisition module, an FIFO module and an IP core of a RISC-V processor.
Description
Technical Field
The invention relates to the field of processor debugging, in particular to a controllable trace debugging method and a controllable trace debugging system for a RISC-V processor.
Background
RISC-V (fifth generation reduced instruction set computer) is an open instruction set architecture established based on the reduced instruction set computing principle, and has the characteristics of complete open source, simple architecture, easy transplantation, modular design, and the like. Based on the open source characteristic, a non-profit organization RISC-V fund is established, and by 1 month in 2019, more than 200 members are added into the non-profit organization RISC-V fund. The Chinese RISC-V industry alliance also has more than fifty related enterprises in the RISC-V field and more than ten universities and research institutions.
In RISC-V processor IP design, the debug unit is often an important ring in it. The IP debugging mode of the processor is mainly interactive debugging and trace debugging, the former has the defects of disturbing performance on the operation of the processor and needing to set an interruption breakpoint, and the latter has large data volume needing to be acquired, and has larger transmission, storage and processing pressure of data when debugging for a long time. At present, an interactive debugging method is mainly adopted when a RISC-V processor on an FPGA development board is tested. Therefore, how to realize the problems encountered in the rapid positioning and debugging, the debugging period is shortened, and the debugging difficulty is reduced is a technical problem which is urgently needed to be solved in the prior art.
Patent No. CN109684147A discloses a RISC-V controller debugging method and device based on I2C, which includes: in a RISC-V controller, an instr value is obtained from an instruction fetching module by using an I2C debugging module; transmitting the instr value from the I2C debug module of the RISC-V controller to the I2C controller of the BMC over the I2C bus; in the BMC, an I2C controller is used for informing an ARM processor to read an instr value and sending the instr value to the terminal; the instr value is parsed into instructions at the terminal and the instructions are displayed for user debugging. However, the technical scheme can not flexibly acquire the RISC-V processor operation instruction and the register data in a specific time period, can quickly locate the problems encountered in debugging, reduces the debugging period and reduces the debugging difficulty.
Disclosure of Invention
The technical task of the invention is to provide a controllable trace debugging method and a controllable trace debugging system for a RISC-V processor, which solve the problems of how to realize rapid positioning debugging, reduce the debugging period and reduce the debugging difficulty.
The technical task of the invention is realized in the following way, a controllable trace debugging method of RISC-V processor, the steps of the method are as follows:
s1, the upper computer generates a trace debugging instruction, an enable signal for acquiring the data of the general register and a general register address to be acquired, packs the trace debugging instruction and sends the trace debugging instruction to a PL (programmable logic device) end through a gigabit Ethernet interface;
s2, the PL terminal receives a debugging trace instruction sent by the upper computer through the gigabit Ethernet module and forwards the whole debugging trace instruction to the trace instruction acquisition module;
s3, the trace instruction acquisition module analyzes the debugging trace instruction;
s4, judging whether an enable signal is acquired:
①, if yes, go to step S5;
②, if not, jumping to step S2;
s5, the trace instruction acquisition module starts to acquire a debugging trace instruction and general register data;
s6, storing the instruction obtained by the tracking instruction obtaining module and the corresponding general register data into a double FIFO cache mode FIFO module;
s7, the gigabit Ethernet module at the PL terminal receives the data in the FIFO module and sends the data to the upper computer;
s8, the upper computer receives and analyzes the instruction of the processor IP core operation and the general register data;
and S9, displaying the analysis result by the upper computer.
Preferably, the debugging trace instruction comprises an enable signal and a close signal of the acquisition instruction and a register code number of the acquisition general register data, and the enable signal and the close signal of the debugging trace instruction can effectively control the time point of the acquisition instruction and reduce the later instruction analysis data volume;
the production and sending time of the debugging trace instruction is controllable, and the debugging trace instruction can be set by a debugging person, including real-time trace debugging and breakpoint marker bit trace debugging.
Preferably, the trace instruction acquisition module analyzes the debugging trace instruction sent by the upper computer, enables/shuts down the signal and the corresponding general register data acquisition process, and acquires the instruction operated by the RISC-V processor and the corresponding general register data when the debugging trace instruction is enabled.
Preferably, the double-FIFO cache mode FIFO module comprises a first FIFO module and a second FIFO module, and the instruction obtained by the tracking instruction obtaining module and the corresponding general register data are firstly stored in the first FIFO module; when the first FIFO module is full, the full zone bit is sent to the PL end gigabit Ethernet module, meanwhile, the next data storage address is changed into the second FIFO module, and the data storage process of the first FIFO module and the second FIFO module is repeated.
Preferably, the upper computer analyzes the acquired debugging trace instructions one by one in a software mode and provides an assembly language descriptor of the instructions.
Preferably, the transmission speed of the PL terminal gigabit Ethernet module is greater than the data storage speed.
Preferably, the enable signal in the debugging trace instruction directly acquires the enable or interrupt flag bit, namely when the IP core of the RISC-V processor runs any interrupt, the instruction and the general register data are acquired.
Preferably, after the trace instruction obtaining module analyzes the close signal, the trace instruction obtaining module stops obtaining the instruction and the general register data, and sends a stop mark to the currently stored FIFO module and the PL-side gigabit ethernet module, the currently stored FIFO module stops storing data after receiving the stop mark, and sends the current amount of stored data to the gigabit ethernet module, the gigabit ethernet module continues to send data after receiving the stop mark, and stops sending data after all data stored in the two FIFOs are sent.
Preferably, the step S6 is executed while the step S1 continues to execute, the read address of the general register is reselected, and a 32-bit all-1 data is inserted between two times of reading the register data of the general register to distinguish the two times of reading the general register data.
A controllable tracking and debugging system of a RISC-V processor comprises an upper computer, a gigabit Ethernet module, a tracking instruction acquisition module, an FIFO module and an IP core of the RISC-V processor, wherein the upper computer is communicated with the gigabit Ethernet module, the gigabit Ethernet module is communicated with the tracking instruction acquisition module, the tracking instruction acquisition module is communicated with the IP core of the RISC-V processor, the tracking instruction acquisition module stores data to the FIFO module, and the FIFO module sends the data to the gigabit Ethernet module;
the upper computer is used for generating a trace debugging instruction, an enabling signal for acquiring data of the general register and a general register address needing to be acquired, packing the trace debugging instruction, and sending the trace debugging instruction to the PL terminal through the gigabit Ethernet interface;
the gigabit Ethernet module is used for receiving a debugging and tracking instruction sent by the upper computer and forwarding the whole debugging and tracking instruction to the tracking instruction acquisition module; meanwhile, the FIFO module is used for receiving data in the FIFO module and sending the data to the upper computer;
the trace instruction acquisition module is used for analyzing the debugging trace instruction and acquiring the debugging trace instruction and the data of the general register;
the FIFO module is used for storing the instruction obtained by the tracking instruction obtaining module and the corresponding general register data;
the IP core of the RISC-V processor is used for operating debugging trace instructions and register data, can quickly locate the problems encountered in debugging, reduces the debugging period and reduces the debugging difficulty.
The controllable trace debugging method and the system of the RISC-V processor have the following advantages:
the method can flexibly acquire the RISC-V processor operation instruction and the register data in a specific time period, can quickly locate the problems encountered in debugging, reduces the debugging period and reduces the debugging difficulty;
the debugging trace instruction comprises an enable signal and a close signal of the instruction, a register code number of general register data is obtained, the time point of obtaining the instruction can be effectively controlled through enabling and closing the debugging trace instruction, and the later instruction analysis data volume is reduced;
the invention is based on FPGA, does not need to run interrupt processing in the processor IP, and reduces the requirement of long-time trace debugging;
the invention adopts a network port communication debugging mode, has high universality and has the function of remote debugging; meanwhile, a controllable tracking debugging mode is adopted, the debugging time and the time point are controllable, the address of a read register is controllable, the data volume can be effectively controlled, and the flexibility is higher.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a flow diagram of a method for controlled trace debugging of a RISC-V processor;
FIG. 2 is a block diagram of a controllable trace debug system for a RISC-V processor.
Detailed Description
The present invention relates to a method and system for performing a controlled trace debug of a RISC-V processor, and more particularly to a method and system for performing a trace debug of a RISC-V processor.
Example 1:
as shown in FIG. 1, the controllable trace debugging method of RISC-V processor of the present invention comprises the following steps:
s1, the upper computer generates a trace debugging instruction, an enable signal for acquiring the data of the general register and a general register address to be acquired, packs the trace debugging instruction and sends the trace debugging instruction to a PL (programmable logic device) end through a gigabit Ethernet interface; the debugging trace instruction comprises an enable signal and a close signal of the acquisition instruction and a register code number of the acquisition general register data, the time point of the acquisition instruction can be effectively controlled through the enable signal and the close signal of the debugging trace instruction, and the later instruction analysis data volume is reduced; the production and sending time of the debugging trace instruction is controllable, and the debugging trace instruction can be set by a debugging person, including real-time trace debugging and breakpoint marker bit trace debugging. The enabling signal in the debugging trace instruction directly acquires the enabling or interrupting zone bit, namely when the IP core of the RISC-V processor runs to any interrupt, the instruction and the general register data are acquired.
S2, the PL terminal receives a debugging trace instruction sent by the upper computer through the gigabit Ethernet module and forwards the whole debugging trace instruction to the trace instruction acquisition module; the sending speed of the PL terminal gigabit Ethernet module is greater than the data storage speed.
S3, the trace instruction acquisition module analyzes the debugging trace instruction;
s4, judging whether an enable signal is acquired:
①, if yes, go to step S5;
②, if not, jumping to step S2;
s5, the trace instruction acquisition module starts to acquire a debugging trace instruction and general register data; the trace instruction acquisition module analyzes a debugging trace instruction sent by the upper computer, enables/closes a signal and a corresponding general register data acquisition process, and acquires an instruction operated by the RISC-V processor and corresponding general register data when the debugging trace instruction is enabled. After the trace instruction acquisition module analyzes the closing signal, the trace instruction acquisition module stops acquiring instructions and general register data and sends stop marks to the currently stored FIFO module and the PL terminal gigabit Ethernet module, the currently stored data is stopped and sent to the gigabit Ethernet module after the FIFO module receives the stop marks, the gigabit Ethernet module continues to send data after receiving the stop marks, and the data sending is stopped after all data stored in the two FIFOs are sent.
S6, storing the instruction obtained by the tracking instruction obtaining module and the corresponding general register data into a double FIFO cache mode FIFO module; the double FIFO cache mode FIFO module comprises a first FIFO module and a second FIFO module, and the instruction obtained by the tracking instruction obtaining module and the corresponding general register data are firstly stored in the first FIFO module; when the first FIFO module is full, the full zone bit is sent to the PL end gigabit Ethernet module, meanwhile, the next data storage address is changed into the second FIFO module, and the data storage process of the first FIFO module and the second FIFO module is repeated.
S7, the gigabit Ethernet module at the PL terminal receives the data in the FIFO module and sends the data to the upper computer;
s8, the upper computer receives and analyzes the instruction of the processor IP core operation and the general register data; and the upper computer analyzes the acquired debugging trace instructions one by one in a software mode and provides an assembly language descriptor of the instructions.
And S9, displaying the analysis result by the upper computer.
Wherein, the step S6 is executed and the step S1 continues to be executed, the read address of the general register is reselected, and a 32-bit all 1 data is inserted between two times of reading the register data of the general register for distinguishing the two times of reading the general register data.
The invention adopts a controllable tracking debugging mode to carry out the IP design debugging of RISC-V.
Example 2:
as shown in fig. 2, the controllable trace debugging system of RISC-V processor of the present invention comprises an upper computer, a gigabit ethernet module, a trace instruction acquisition module, an FIFO module and an IP core of RISC-V processor, the upper computer communicates with the gigabit ethernet module, the gigabit ethernet module communicates with the trace instruction acquisition module, the trace instruction acquisition module communicates with the IP core of RISC-V processor and the trace instruction acquisition module stores data to the FIFO module, the FIFO module sends data to the gigabit ethernet module;
the upper computer is used for generating a trace debugging instruction, an enabling signal for acquiring data of the general register and a general register address needing to be acquired, packing the trace debugging instruction, and sending the trace debugging instruction to the PL terminal through the gigabit Ethernet interface;
the gigabit Ethernet module is used for receiving a debugging and tracking instruction sent by the upper computer and forwarding the whole debugging and tracking instruction to the tracking instruction acquisition module; meanwhile, the FIFO module is used for receiving data in the FIFO module and sending the data to the upper computer;
the trace instruction acquisition module is used for analyzing the debugging trace instruction and acquiring the debugging trace instruction and the data of the general register;
the FIFO module is used for storing the instruction obtained by the tracking instruction obtaining module and the corresponding general register data;
the IP core of the RISC-V processor is used for operating debugging trace instructions and register data, can quickly locate the problems encountered in debugging, reduces the debugging period and reduces the debugging difficulty.
The working process of the system is as follows:
(1) the upper computer generates an instruction, obtains an enabling signal of the data of the general register and an address of the general register to be obtained, packages the enabling signal into a debugging tracking instruction, and sends the debugging tracking instruction to a PL (programmable logic device) end through a gigabit Ethernet interface;
the enabling signal in the debugging trace instruction can be direct obtaining enabling or an interruption zone bit, namely when the IP core of the RISC-V processor runs to a certain interruption, the instruction and the data of the general register are obtained;
(2) the PL end receives a debugging tracking instruction sent by an upper computer through a gigabit Ethernet module and forwards the whole instruction to a tracking instruction acquisition module;
(3) the trace instruction acquisition module analyzes the debugging trace instruction and judges the time for starting to acquire the instruction and the data of the general register and the address of the general register;
(4) the tracking instruction acquisition module starts to acquire instructions and general register data and stores the data into the first FIFO module; when the FIFO is full, sending a full zone bit to the PL end gigabit Ethernet module, and simultaneously changing the next data storage address into a second FIFO module; repeating the data storage process;
(5) when the PL end gigabit Ethernet module receives the full mark signal of the FIFO module, the data in the FIFO module is read and sent to the upper computer;
(6) the upper computer generates a closing signal for acquiring the instruction and the general register data and sends the closing signal to the PL terminal, and the PL terminal gigabit Ethernet module sends the closing instruction to the PL terminal gigabit Ethernet module
(7) After the trace instruction acquisition module analyzes the closing signal, the trace instruction acquisition module stops acquiring instructions and general register data and sends stop marks to the currently stored FIFO module and the PL terminal gigabit Ethernet module;
step (1) can be performed after step (4) is started, the read address of the general register is reselected, and 32-bit all-1 data is inserted between two times of reading the register data of the general register, so as to distinguish the two times of reading the general register data.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for controllable trace debugging of RISC-V processor is characterized by the following steps:
s1, the upper computer generates a trace debugging instruction, an enable signal for acquiring the data of the general register and a general register address to be acquired, packs the trace debugging instruction and sends the trace debugging instruction to a PL (programmable logic device) end through a gigabit Ethernet interface;
s2, the PL terminal receives a debugging trace instruction sent by the upper computer through the gigabit Ethernet module and forwards the whole debugging trace instruction to the trace instruction acquisition module;
s3, the trace instruction acquisition module analyzes the debugging trace instruction;
s4, judging whether an enable signal is acquired:
①, if yes, go to step S5;
②, if not, jumping to step S2;
s5, the trace instruction acquisition module starts to acquire a debugging trace instruction and general register data;
s6, storing the instruction obtained by the tracking instruction obtaining module and the corresponding general register data into a double FIFO cache mode FIFO module;
s7, the gigabit Ethernet module at the PL terminal receives the data in the FIFO module and sends the data to the upper computer;
s8, the upper computer receives and analyzes the instruction of the processor IP core operation and the general register data;
and S9, displaying the analysis result by the upper computer.
2. The method of claim 1, wherein the debug trace instruction comprises an enable and disable signal for a get instruction and a register code number for a get general register data;
the production and sending time of the debugging trace instruction is controllable, and the debugging trace instruction can be set by a debugging person, including real-time trace debugging and breakpoint marker bit trace debugging.
3. A method as claimed in claim 1 or 2, wherein the trace instruction obtaining module parses a debug trace instruction sent by the host computer, enables/disables the signal and corresponding general register data obtaining process, and obtains the instruction run by the RISC-V processor and the corresponding general register data when enabled.
4. The method of claim 1, wherein the FIFO modules include a first FIFO module and a second FIFO module, and the instruction and the corresponding general-purpose register data obtained by the trace instruction obtaining module are first stored in the first FIFO module; when the first FIFO module is full, the full zone bit is sent to the PL end gigabit Ethernet module, meanwhile, the next data storage address is changed into the second FIFO module, and the data storage process of the first FIFO module and the second FIFO module is repeated.
5. The RISC-V processor controllable trace debug method according to claim 1, wherein said upper computer parses the obtained debug trace instructions piece by piece in a software manner and gives an assembly language descriptor of the instructions.
6. The method of claim 1, wherein the transmission speed of the PL-side gigabit ethernet module is faster than the data storage speed.
7. A RISC-V processor controlled trace debug system as claimed in claim 2, wherein said enable signal in said debug trace instruction directly fetches the enable or interrupt flag bit, i.e. when the RISC-V processor IP core runs any interrupt, it starts fetching instruction and general register data.
8. The RISC-V processor controllable trace debugging method of claim 3, wherein the trace instruction obtaining module stops obtaining the instruction and the general register data after analyzing the close signal, and sends a stop flag to the currently stored FIFO module and the PL-side gigabit ethernet module, the currently stored FIFO module stops storing the data after receiving the stop flag, and sends the current amount of the stored data to the gigabit ethernet module, the gigabit ethernet module continues sending the data after receiving the stop flag, and stops sending the data after all the data stored in the two FIFOs are sent.
9. A RISC-V processor controlled trace debug method as claimed in claim 1, wherein said step S6 is executed while step S1 continues to execute, the read address of the general purpose register is re-selected, and a 32-bit all 1 data is inserted between the two reads of the register data of the general purpose register for distinguishing between the two reads of the general purpose register data.
10. A controllable tracking and debugging system of a RISC-V processor is characterized by comprising an upper computer, a gigabit Ethernet module, a tracking instruction acquisition module, an FIFO module and an IP core of the RISC-V processor, wherein the upper computer is communicated with the gigabit Ethernet module, the gigabit Ethernet module is communicated with the tracking instruction acquisition module, the tracking instruction acquisition module is communicated with the IP core of the RISC-V processor, the tracking instruction acquisition module stores data to the FIFO module, and the FIFO module sends the data to the gigabit Ethernet module;
the upper computer is used for generating a trace debugging instruction, an enabling signal for acquiring data of the general register and a general register address needing to be acquired, packing the trace debugging instruction, and sending the trace debugging instruction to the PL terminal through the gigabit Ethernet interface;
the gigabit Ethernet module is used for receiving a debugging and tracking instruction sent by the upper computer and forwarding the whole debugging and tracking instruction to the tracking instruction acquisition module; meanwhile, the FIFO module is used for receiving data in the FIFO module and sending the data to the upper computer;
the trace instruction acquisition module is used for analyzing the debugging trace instruction and acquiring the debugging trace instruction and the data of the general register;
the FIFO module is used for storing the instruction obtained by the tracking instruction obtaining module and the corresponding general register data;
the IP core of the RISC-V processor is used for operating debugging trace instructions and register data, can quickly locate the problems encountered in debugging, reduces the debugging period and reduces the debugging difficulty.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911030980.9A CN110795350B (en) | 2019-10-28 | 2019-10-28 | Controllable tracking and debugging method and system for RISC-V processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911030980.9A CN110795350B (en) | 2019-10-28 | 2019-10-28 | Controllable tracking and debugging method and system for RISC-V processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110795350A true CN110795350A (en) | 2020-02-14 |
| CN110795350B CN110795350B (en) | 2023-05-05 |
Family
ID=69441679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911030980.9A Active CN110795350B (en) | 2019-10-28 | 2019-10-28 | Controllable tracking and debugging method and system for RISC-V processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110795350B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112285542A (en) * | 2020-10-14 | 2021-01-29 | 天津津航计算技术研究所 | Debugging and testing method for FPGA external interface logic |
| CN117008972A (en) * | 2023-09-27 | 2023-11-07 | 武汉深之度科技有限公司 | Instruction analysis method, device, computing equipment and storage medium |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1398703A2 (en) * | 2002-09-10 | 2004-03-17 | Accurate Technologies Inc. | Method of rapidly prototyping software |
| US20060117224A1 (en) * | 2004-11-15 | 2006-06-01 | Sunplus Technology Co., Ltd. | Trace and debug method and system for a processor |
| CN101251819A (en) * | 2007-12-11 | 2008-08-27 | 浙江大学 | Debug method suitable for multi-processor core system chip |
| US8874883B2 (en) * | 2010-09-24 | 2014-10-28 | Arm Limited | Debugging of a data processing apparatus |
| CN109684147A (en) * | 2019-01-09 | 2019-04-26 | 郑州云海信息技术有限公司 | A kind of RISC-V controller adjustment method and device based on I2C |
| CN109710312A (en) * | 2018-12-13 | 2019-05-03 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | RISC-V instruction set based real-time interrupt processing method and device and industrial control processor |
| CN110069443A (en) * | 2019-05-05 | 2019-07-30 | 山东浪潮人工智能研究院有限公司 | A kind of UFS memory array system and data transmission method based on FPGA control |
-
2019
- 2019-10-28 CN CN201911030980.9A patent/CN110795350B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1398703A2 (en) * | 2002-09-10 | 2004-03-17 | Accurate Technologies Inc. | Method of rapidly prototyping software |
| US20060117224A1 (en) * | 2004-11-15 | 2006-06-01 | Sunplus Technology Co., Ltd. | Trace and debug method and system for a processor |
| CN101251819A (en) * | 2007-12-11 | 2008-08-27 | 浙江大学 | Debug method suitable for multi-processor core system chip |
| US8874883B2 (en) * | 2010-09-24 | 2014-10-28 | Arm Limited | Debugging of a data processing apparatus |
| CN109710312A (en) * | 2018-12-13 | 2019-05-03 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | RISC-V instruction set based real-time interrupt processing method and device and industrial control processor |
| CN109684147A (en) * | 2019-01-09 | 2019-04-26 | 郑州云海信息技术有限公司 | A kind of RISC-V controller adjustment method and device based on I2C |
| CN110069443A (en) * | 2019-05-05 | 2019-07-30 | 山东浪潮人工智能研究院有限公司 | A kind of UFS memory array system and data transmission method based on FPGA control |
Non-Patent Citations (2)
| Title |
|---|
| 姚放吾;金鑫;: "基于Monitor的C语言源代码调试器的设计与实现" * |
| 李正军;周志权;赵占锋;: "基于FPGA的高速数据传输系统设计与实现" * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112285542A (en) * | 2020-10-14 | 2021-01-29 | 天津津航计算技术研究所 | Debugging and testing method for FPGA external interface logic |
| CN112285542B (en) * | 2020-10-14 | 2023-02-03 | 天津津航计算技术研究所 | Debugging and testing method for FPGA external interface logic |
| CN117008972A (en) * | 2023-09-27 | 2023-11-07 | 武汉深之度科技有限公司 | Instruction analysis method, device, computing equipment and storage medium |
| CN117008972B (en) * | 2023-09-27 | 2023-12-05 | 武汉深之度科技有限公司 | Instruction analysis method, device, computing equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110795350B (en) | 2023-05-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10235272B2 (en) | Debugging system and method | |
| CN107273280B (en) | Log processing method and device, electronic equipment and storage medium | |
| US9176848B2 (en) | Program debugger and program debugging | |
| US8438547B2 (en) | Address translation trace message generation for debug | |
| US20100281304A1 (en) | Debug messaging with selective timestamp control | |
| US20160321159A1 (en) | Integrating a Protocol Analysis Device with Features of a Software Development Program | |
| CN110795350A (en) | Controllable trace debugging method and system for RISC-V processor | |
| CN104102160B (en) | Controller area network (CAN) bus signal transceiving analysis tool | |
| CN104503898A (en) | Method and system for checking embedded software debugging parameter in real time | |
| TW200615746A (en) | Trace, debug method and system for a processor | |
| US8751744B2 (en) | Integrated circuit comprising trace logic and method for providing trace information | |
| CN106201790B (en) | A kind of adjustment method and debugging system based on DSDT table | |
| CN106776285B (en) | Webpage front end debugging method and device | |
| CN106294132B (en) | A kind of method and device managing log | |
| EP1125200B1 (en) | Maintaining object size information concurrent with data optimization for debugging | |
| CN116541277A (en) | Interface testing method, device, equipment and medium | |
| CN106933577B (en) | Python-based method and system for querying software platform control block | |
| CN115758963A (en) | Device, method and system for processing printing information in chip EDA simulation | |
| CN202424939U (en) | Complementary metal oxide semiconductor (CMOS) image sensor debugger | |
| CN105183954A (en) | PXI based serial bus health monitoring platform | |
| EP2634693A1 (en) | Method and apparatus for interacting with runnung software | |
| US9678852B2 (en) | Tracing the operations of a data processing apparatus using trace data source identifiers to respond to flush requests | |
| US20150106792A1 (en) | Method of presenting trace data with improved efficiency by using hosted formatted output commands | |
| CN103517307B (en) | A kind of remote debugging system based on TD-SCDMA | |
| CN104200033A (en) | High-speed circuit board serial port debugging method based on FPGA and DSP |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20230417 Address after: 250000 building S02, No. 1036, Langchao Road, high tech Zone, Jinan City, Shandong Province Applicant after: Shandong Inspur Scientific Research Institute Co.,Ltd. Address before: North 6th floor, S05 building, Langchao Science Park, 1036 Langchao Road, hi tech Zone, Jinan City, Shandong Province, 250100 Applicant before: SHANDONG INSPUR ARTIFICIAL INTELLIGENCE RESEARCH INSTITUTE Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |