CN116107873A - Simulation test platform and automatic generation method thereof - Google Patents
Simulation test platform and automatic generation method thereof Download PDFInfo
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- CN116107873A CN116107873A CN202211599213.1A CN202211599213A CN116107873A CN 116107873 A CN116107873 A CN 116107873A CN 202211599213 A CN202211599213 A CN 202211599213A CN 116107873 A CN116107873 A CN 116107873A
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- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3688—Test management for test execution, e.g. scheduling of test suites
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- G06F11/00—Error detection; Error correction; Monitoring
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- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3452—Performance evaluation by statistical analysis
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- G06F11/3457—Performance evaluation by simulation
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- G06F11/00—Error detection; Error correction; Monitoring
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Abstract
The invention provides an automatic generation method of a simulation test platform, which is characterized in that an XML file is utilized to configure and store attribute data based on a modularization technology, the configured data is executed to automatically generate the test platform, and finally the test platform is loaded into a full-digital simulation system VTest for operation. The modular driving mechanism is adopted to realize the matching method of the requirements and the modules, and the automatic generation capacity of the simulation test platform based on the modules is solved.
Description
Technical Field
The invention relates to a method for automatically generating a simulation test platform, and belongs to the field of simulation.
Background
The embedded simulation system is a physical environment which uses software to simulate the operation of the embedded software realistically under the condition of not having target hardware, and the embedded software which is originally operated on the real hardware can be operated in the simulation system without any modification, and the operation dynamic characteristics of the embedded software are consistent with those of the real hardware. An embedded software runs on the emulation system, and more than the emulation of the processor, the emulation of the peripheral device, the communication data processing, which is in communication with the embedded software. Because the peripheral equipment and the communication data used by each embedded software are different under different requirements and different environments, when the simulation test platform is built, the function simulation of the peripheral equipment, the function processing of the communication data and the like need to be independently developed, and the simulation test platform corresponding to each embedded software needs to be independently developed, so that the developed simulation test platform is only applicable to one embedded software, the general effect is not achieved, the development process is time-consuming and labor-consuming, and the technical capability requirement of the developer is high. However, as software progresses toward the sophistication and sophistication, it is difficult for the current model of building a simulation test platform to meet the design requirements of the simulation test platform for high efficiency, high reuse, and automation.
In order to reduce code change or secondary development caused by inconsistent design due to different functions of software and different data communication of the simulation test platform, ensure the function universality of the simulation test platform, meet the high efficiency, high quality and high reusability of platform generation, reduce the threshold generated by the simulation test platform, ensure the correctness of the software detected by the simulation test platform, and need to research a new solution for automatic generation of the simulation test platform.
Disclosure of Invention
The invention solves the technical problems that: aiming at the defects of the existing simulation test platform building technology, the requirements of high efficiency, high reusability and high quality are not met, the simulation test platform and the automatic generation method thereof are provided, and the conversion from the development of a platform with customized requirements to the generation of a platform with configured requirements is realized.
The technical scheme adopted by the invention is as follows: a simulation test platform, comprising: the system comprises an instruction execution system module, a memory address operation module, a performance statistics module, a chip simulation module, a data control module, an interrupt triggering module, a log information recording module and a data analysis module;
the instruction execution system module loads, analyzes, sends, receives and forwards instructions in the running process of the simulation test platform, receives externally sent instruction data streams, loads instruction files, outputs converted instruction data to a designated module, and drives the corresponding module to perform instruction analysis and execution functions;
the memory address operation module controls and processes the read-write operation of the memory address, and carries out real-time log record on the operated address and data; the memory address operation module receives instruction data from the instruction execution system module and outputs a data stream generated by address operation to the log information recording module;
the performance statistics module performs interval statistics on the execution time of the functional item and supports point-to-point time statistics and same point time statistics; when the operation of the simulation test platform is finished, recording performance related data into a log file;
the chip simulation module carries out soft simulation on logic functions, characteristics and time sequences in the chip, develops different independent chip simulation libraries aiming at different chips, and receives and transmits protocol data streams through the data control module;
the data control module integrates and controls all data protocol transmission time, protocol structure judgment, protocol correctness judgment, protocol checksum processing, protocol response control and instruction analysis and execution;
the interrupt triggering module gathers all interrupt triggering control and triggering modes, and the interrupt triggering module receives instruction data for triggering the interrupt from the instruction execution system module, analyzes and executes the instruction;
the log information recording module records the input and output data information of other modules in the running process to form log information;
the data analysis module analyzes the whole package of data of the protocol and displays the whole package of data in a graphic visualization mode, and the data analysis result supports pure data display and display of characters after data translation; the data analysis module carries out real-time file recording on the result data of the analysis data packet and sends the log data to the log information recording module.
Furthermore, the memory address operation module monitors single or multiple addresses within a certain range, and when software operates on the addresses, the data on the operation addresses are recorded into the file in real time.
Further, the performance statistics module configures performance statistics attributes according to the instructions of the instruction execution system module, wherein the performance statistics attributes comprise a start address, an end address, an address operation mode, a data start value, a data end value and a performance time effective range; when the starting address and the ending address are the same, counting the time interval of the same address operation data;
after the software operation is finished, the performance statistics module automatically counts the maximum value and the minimum value of the performance data and outputs the starting time of the maximum value and the minimum value; automatically judging whether the statistical time is in the effective range or not, giving out an out-of-range warning prompt, and storing the data into a designated txt file.
Further, the chip simulation module receives the data stream sent by the data control module through the port, analyzes and identifies the data stream, and processes the data through the chip control logic; the chip simulation module sends data to the data control module through the port, the data control module analyzes and processes the data stream, and the structure, the transmission process and the input data of the sent data are the same.
Further, the data control module receives instruction data and protocol data stream through the instruction execution system module and outputs the processed data to the corresponding chip simulation module; and the protocol data received by the chip simulation module is processed and output to the log information recording module.
The data control module receives the instruction data of the instruction execution system module and the output data of the chip simulation module, the instruction execution system module determines a data transmission structure, the chip simulation module determines an output data transmission structure, and the data control module sequentially receives, analyzes and processes the data;
the data control module sends input stream data to the chip simulation module, unpacking source data to the data analysis module and input and output data to the log information recording module for recording.
Furthermore, the data analysis rules in the data analysis module are configured through XML files, and the configuration is performed through configuration files aiming at different protocols and different analysis modes.
A generation method of a simulation test platform comprises the following steps:
loading a configuration file: the configuration file adopts an XML file structure;
acquiring engineering information: according to the loaded configuration file XML, acquiring basic information, processor information, general function library information and chip simulation library module of corresponding engineering information, storing and managing the data, and providing an interface function for acquiring configuration file information data;
acquiring functional module relation data: acquiring information data such as attributes, pins, data interfaces, association relation among the function libraries, a link mode and the like of the function libraries according to the loaded function library configuration information XML, and storing and managing the data;
data processing is carried out according to the configuration file: analyzing the input demand item according to the information data obtained by the configuration file, obtaining the processor information, the project name, the memory use condition, the interrupt use condition, the function interface and other function interfaces, and generating a corresponding platform file;
generating basic engineering and processor information: automatically generating engineering information, memory data, processor information data and a tested file according to the configuration file and the data acquired by the requirement items;
generating a basic engineering file: creating an engineering file according to the generated engineering information data, wherein the file comprises a processor, a memory, a tested source file, a target code file and engineering attribute data;
obtaining a function library from a container: according to analysis and matching of configuration file information and requirement items, a required function library is obtained, the required function library and corresponding files are automatically extracted from a container, and the function library and the corresponding files are stored under an engineering file designated directory;
generating a function library: the function library obtained from the container is placed under the appointed directory of the engineering file, and function library information comprising library file paths, names, attribute data, communication ports and support pin information is added into the engineering file; the association relation between the corresponding library and other libraries is obtained through configuration data of the configuration file, and link data is automatically generated, wherein the link data comprises port communication links between function libraries, pin links, interrupt pin links between the function libraries and a processor and attribute configuration data values;
generating a test instruction: the test instruction program generating program loads and generates a finished engineering file, and generates an instruction description file and a test instruction and ID corresponding relation file by utilizing a function library ID in the engineering file and instruction ID and name information in the instruction file;
engineering file loading operation: after the test platform engineering file is generated, loading and executing are carried out through the all-digital simulation system VTest, and the instruction driving mechanism is notified to carry out software test work.
Furthermore, the configuration file content comprises engineering information, processor information, general function library information, a chip simulation library and a data control module, and the XML file supports configuration of attributes, pins, data interfaces and association relations and link modes of the function libraries.
Furthermore, the function library module simulates corresponding chip logic and time sequence, and the types of the function library module comprise an instruction execution system module, a memory address operation module, a performance statistics module, a chip simulation module, a data control module, an interrupt trigger module, a log information recording module and a data analysis module.
Further, the engineering file loading operation further includes: the instruction driver supports the loading of instruction files and scripts, and simultaneously supports the test instructions sent by the universal automatic dynamic test platform DTP.
Compared with the prior art, the invention has the advantages that:
the invention provides a simulation test platform and an automatic generation method thereof, wherein the method is based on a modularization technology, a test instruction is packaged in a modularization mode through matching of a demand item and a module, configuration and storage of attribute data are carried out by utilizing an XML file, the configured data are automatically generated into the test platform, and finally the test platform is loaded into a full-digital simulation system VTest for operation, so that the platform generation transition from the development of a demand customized platform to the demand configuration is realized.
Drawings
FIG. 1 is a diagram of a simulation test platform framework of the present invention;
FIG. 2 is a flow chart of a simulation test platform generation process of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
1. Platform assembly module
On the basis of the platform construction based on the modularized drive, an execution mechanism between modules is designed and realized, and the simulation test platform comprises: the system comprises an instruction execution system module, a memory address operation module, a performance statistics module, a chip simulation module, a data control module, an interrupt trigger module, a log information recording module and a data analysis module.
(1) Instruction execution system module
The module is used for uniformly managing functions of loading, analyzing, transmitting, receiving, forwarding and the like of instructions in the running process of the simulation test platform, and each project is needed to exist; attribute information and structure information of the library are described through configuration files; when the engineering creates other function libraries, the engineering executes automatic checking to judge whether to communicate with the instruction system library, and when the communication exists, the engineering automatically performs communication connection, and the specific connection mode is obtained through a configuration file.
The instruction execution system module receives an externally transmitted instruction data stream (network or port) and loads an instruction file.
The instruction file format is as follows:
the time is as follows: an instruction file keyword;
test end time: a run end time key;
EndTime: setting operation ending time;
the instruction file content is a plurality of instruction sets, and each instruction format is as follows: time #; an instruction name; parameter 1; parameter 2; parameter 3., wherein time is the moment of execution of the instruction, the parameter is the data content of the instruction, supporting multiple parameters; the instruction is to execute the function of setting single AD result data when the software runs for 33.2 seconds, and four parameters are attached, wherein the parameter values are respectively 0,12 and 0x00;0xFFF.
The instruction execution system module receives instruction data through a network interface or other ports, and the data format is as follows: an instruction name; parameter 1; parameter 2; parameter 3..lack of time compared to the format of the instructions in the data file. The instruction execution system module executes the instruction immediately after receiving the instruction data.
The instruction execution system module outputs instruction data after conversion according to the input data. And in the running process of the platform, the converted instruction data is sent to a designated module, and the module is driven to perform instruction analysis and execution functions.
The converted instruction data structure is as follows:
nTbye: the instruction data type is currently a script instruction;
nID: the instruction module generates a corresponding instruction ID according to the execution name, each module carries out instruction identification by the instruction ID number, and an ID identification formula is as follows: (instruction ID-module ID 10000) <10000;
szPara: parameters of the instruction data;
(2) Memory address operation module
The memory address operation is a function of controlling processing of read-write operation of the memory address, and simultaneously carries out real-time log record on the address and data of the operation.
The memory address operation module receives instruction data from the instruction execution system module and outputs an address operation generation data stream to the log information recording module.
The memory address operation module controls the input time and content of data through instructions, and the support instructions comprise:
1> setting address data
Parameter 1: start address, hexadecimal system
Parameter 2: data or files, the file types including txt and bin, txt formats
Description: supporting 8-bit, 16-bit, 32-bit address type settings
2> set address bit data
Parameter 1: address 0x represents hexadecimal, otherwise decimal
Parameter 2: data, 0x represents hexadecimal, otherwise decimal
Parameter 3: mask, 0x represents hexadecimal, otherwise decimal
Description: supporting 8-bit, 16-bit and 32-bit address type setting, and setting single or multiple bit values through masks;
the memory address operation module monitors single or multiple addresses within a certain range, and when software operates on the addresses, data on the operation addresses are recorded into the file in real time.
Address monitoring mode: setWatchOnMemory (DWORD dwBeginAddr, DWORD dwEndAddr, DWORD dwMemType, VTTACCESS vtAccess, vttmestrorallbac kttcall back), parameters including start address, end address, address type, callback function (which is performed when operating on addresses in the monitoring range);
file type: recording the file supporting TXT;
file format: time address operation mode address data values, such as: 10.5 read 0x50000x12, data read 0x5000 when software runs for 10.5 seconds is 0x12;
(3) Performance statistics module
The performance statistics are interval statistics of execution time of a certain functional item, and support point-to-point time statistics and same point time statistics; and when the operation of the simulation test platform is finished, recording the performance related data into a log file.
The performance statistics module configures performance statistics attributes according to the instructions of the instruction execution system module, wherein the performance statistics attributes comprise a start address, an end address, an address operation mode (read/write), a data start value, a data end value and a performance time effective range (alarm prompt or other operations are carried out when the range is exceeded); when the starting address and the ending address are the same, the time interval for counting the same address operation data condition is represented.
After the software operation is finished, the performance statistics module automatically counts the maximum value and the minimum value of the performance data and outputs the starting time of the maximum value and the minimum value; automatically judging whether the statistical time is in the effective range and giving out an out-of-range warning prompt, and storing the data into a designated txt file, wherein the file content is as follows:
(4) Chip simulation module
The chip simulation module is mainly used for carrying out soft simulation on logic functions, characteristics and time sequences in the chip, and develops different independent chip simulation libraries aiming at different chips.
The chip simulation module receives and transmits protocol data streams through the data control module.
The chip simulation module receives the data stream sent by the data control module through the port, analyzes and identifies the data stream, and processes the data through the chip control logic.
The data transmission structure is as follows:
lpbuf: a data stream storage buffer;
nLen: data stream length, unit bytes;
nresense: preserving parameters;
dReceiveBeginTime: start time of data transmission, unit second;
the chip simulation module sends data to the data control module through the port, the data control module analyzes and processes the data stream, and the structure, the transmission process and the input data of the sent data are the same.
(5) Data control module
The data control module integrates and controls all the functions of data protocol transmission time, protocol structure judgment, protocol correctness judgment, protocol checksum processing, protocol response control, instruction analysis, execution and the like.
The data control module receives instruction data and protocol data stream through the instruction execution system module and outputs the processed data to the corresponding chip simulation module; and the protocol data received by the chip simulation module is processed and output to the log information recording module.
The data control module receives the instruction data of the instruction execution system module and the output data of the chip simulation module, the instruction execution system module determines the transmission structure of the data, the chip simulation module determines the output data transmission structure, and the data control module sequentially receives, analyzes and processes the data. The data transmission structure and the mode are shown in the instruction module and the chip simulation module.
The data control module sends input stream data to the chip simulation module, unpacking source data to the data analysis module and input and output data to the log information recording module for recording. The data transmission structure and the data transmission mode are shown in a chip simulation module, a data analysis module and a log information recording module.
(6) Interrupt trigger module
The interrupt trigger module integrates all interrupt trigger control and trigger modes, and realizes the unified control and management of interrupt trigger.
The interrupt triggering module receives the instruction data triggering the interrupt from the instruction execution system module, analyzes and executes the instruction.
The interrupt triggering module receives the data of triggering interrupt instructions, and the supporting instructions comprise:
1> triggering external interrupts
Parameter 1: interrupt number: 0 to 15
Parameter 2: triggering level mode: HIGH rising edge; LOW falling edge
Parameter 3: the cycle time is controlled to be 0 or less in seconds, and the trigger is triggered once or stopped
Description: the number of the external interrupt numbers supported currently is 16, and the triggering can be performed in a cyclic mode;
2> triggering internal interrupts
Parameter 1: interrupt number: 0 to 9
Parameter 2: triggering level mode: HIGH rising edge; LOW falling edge
Parameter 3: the cycle time is controlled to be 0 or less in seconds, and the trigger is triggered once or stopped
Description: the number of the internal interrupt numbers supported currently is 10, and the internal interrupt numbers can be triggered in a circulating mode;
(7) Log information recording module
The log information recording module records the input and output data information of all modules to form a set of complete and unified log information mode, and the log files support txt texts, bin files and databases, so that unified management of log data recording is realized, and the high efficiency of data information recording is improved.
The log information recording module receives data sent by other modules through interfaces, and the data format and type are as follows:
nTbye: the data type, currently the file name;
nID: a file corresponding ID number, each file corresponding ID in the system being unique;
szPara: storing specific content of file names;
nTbye: the data type is currently printed and saved for the data file;
nID: printing a corresponding ID number of the file;
szPara: printing specific content of the data;
(8) Data analysis module
The data analysis module analyzes the whole package of data of the protocol and displays the whole package of data in a graphic visualization mode, and the data analysis result supports pure data display and display of characters after data translation; the data analysis rule is configured through an XML file, and the configuration is completed through the configuration file aiming at different protocols and different analysis modes, so that the flexible application and the rapid adaptation of the data analysis are realized.
a) XML file structure:
GRID: for a set of data start flags, attribute Name: data protocol name, row: interface display form line number, col: the interface displays the number of columns, flag: a data ID identifier for protocol matching ID;
DATA: data item under GRID, offset: data item offset, length: data length, name: data name, valueType: data type, order: data sequence, vector: equivalent value, codeType: coding mode, floatType: floating point number data types;
DATASELECT: data item configuration and conversion configuration;
BIT: bit mode configuration in DATA supports offset position, length and name equivalent configuration;
BITSELECT: bit data item conversion configuration;
the data analysis module receives the data of the data control module, and the data transmission structure is as follows:
nFlag: the data packet identification is matched with the analysis cabinet configuration file flag, and corresponding rule data analysis is carried out after the matching is successful;
pBuf: a packet storage area;
nBufLen: the number of bytes of the data packet;
the data analysis module performs real-time file recording on the result data of the analysis data packet and sends the log data to the log information recording module, and the support file type comprises txt and excel.
2. Platform generation method
Corresponding functional modules are added according to the configuration information and the test requirement items, and simulation test platform engineering and test platform files are automatically generated through the configuration information and the association relation of the functional modules, wherein the platform files comprise an operation VTE file, a software target code file, a software source code file, a functional library module file, a test instruction set and an instruction file.
The platform generation process is as follows:
1) Loading configuration file XML
The configuration file is designed by an XML file structure, the configuration file content comprises engineering information, processor information, general function library information, a chip simulation library, a data control module and the like, and the XML file supports configuration of attributes, pins, data interfaces and association relations and link modes among the function libraries.
2) Obtaining engineering information
According to the loaded configuration file XML, obtaining the basic information, the processor information, the general function library information, the chip simulation library module and other data of the corresponding engineering information, storing and managing the data, and providing an interface function for obtaining the configuration file information data.
3) Acquiring functional module relationship data
And acquiring information data such as attributes, pins, data interfaces, association relations among the function libraries, link modes and the like of the function libraries according to the loaded function library configuration information XML, and carrying out storage management on the data.
4) Data processing according to configuration file
And analyzing the input demand items according to the information data acquired by the configuration files, acquiring processor information (processor type and main frequency), project names, memory use conditions, interrupt use conditions, function interfaces (acquiring function libraries) and other function interfaces from the demands, and finally generating corresponding platform files.
5) Base engineering and processor information generation
And automatically generating engineering information (engineering name, version and attribute configuration), memory data, processor information data (processor type, main frequency data and interrupt condition), measured files (file storage path and target code file) and other data according to the data acquired by the configuration file and the requirement item.
6) Basic engineering file generation
And creating an engineering file according to the generated engineering information data, wherein the file comprises a processor, a memory, a tested source file, a target code file and engineering attribute data.
7) Obtaining function libraries from containers
The function library module simulates the functions of corresponding chip logic, time sequence and the like, has unified standard interfaces and communication protocols, integrates all the function libraries into one container for unified management, and comprises an instruction execution system module, a memory address operation module, a performance statistics module, a chip simulation module, a data control module, an interrupt triggering module, a log information recording module and a data analysis module.
And according to analysis and matching of the configuration file information and the requirement items, obtaining a required function library, automatically extracting the required function library and corresponding files from the container, and storing the function library and the corresponding files under an engineering file designated directory.
8) Function library generation
The function library obtained from the container is placed under the appointed directory of the engineering file, and the function library information comprising library file path, name, attribute data, communication port and support pin information is added in the engineering file.
And obtaining association relations between the corresponding libraries and other libraries through configuration data of the configuration file, and automatically generating link data, wherein the link data comprises port communication links between function libraries, pin links, function library and processor interrupt pin links and attribute configuration data values.
9) Test instruction generation
And the test instruction is to finally execute a test instruction generating program after the engineering information and the function library are generated, and the program automatically generates supported test instructions and a use instruction file according to the information of the currently selected processor, the function library and the like, wherein the test instruction file format supports txt files and json.
The test instruction program generating program loads the generated engineering file, and generates an instruction description file and a test instruction and ID corresponding relation file by utilizing the function library ID in the engineering file and the instruction ID and name information in the instruction file, wherein the generated instruction ID calculation formula is as follows: function library ID 10000+ instruction file instruction ID.
10 Engineering file loading operation)
After the test platform engineering file is generated, loading and executing are carried out through the all-digital simulation system VTest, and the instruction driving mechanism is notified to carry out software test work. The instruction driver supports the loading of instruction files and scripts, and simultaneously supports the test instructions sent by the universal automatic dynamic test platform DTP.
Examples:
the invention defines an automatic generation method of a simulation test platform, which is characterized in that based on a modularization technology, an XML file is utilized to configure and store attribute data, the configured data is executed to automatically generate the test platform, and finally the test platform is loaded into a full-digital simulation system VTest for operation. The modular driving mechanism is adopted to realize the matching method of the requirements and the modules, and the automatic generation capacity of the simulation test platform based on the modules is solved.
As shown in fig. 1, the simulation test platform includes:
(1) Instruction execution system module
The module is mainly responsible for the functions of loading, analyzing, transmitting, receiving, forwarding and the like of instructions in the running process of the simulation test platform.
Instruction loading: loading an instruction file to be executed through an interface or a port, and reading and storing instruction contents in the file;
instruction analysis: the read instruction is subjected to format analysis, including execution time, instruction name and instruction parameters; the instruction name supports the transmission of an instruction ID mode;
and (3) sending an instruction: according to the instruction time, when the simulation platform operates to the moment, transmitting the instruction in a broadcast form through a communication port, wherein the transmission content comprises an instruction name and parameters;
and (3) receiving an instruction: receiving instructions sent by other modules, analyzing and sending out;
instruction forwarding: receiving instructions of other modules, and directly sending the instructions without analysis;
(2) Memory address operation module
The module is used for controlling the read-write operation of the memory address and comprises a single address, a plurality of addresses and a continuous address; the memory address control mode comprises an implementation monitoring mode, a periodic operation mode and a condition control mode, and simultaneously carries out real-time data recording on the monitored address operation. Configurable settings have been implemented for address type, monitoring mode and data record file name,
(3) Performance statistics module
The module is used for counting the execution time interval of the functional item, mainly in a point-to-point time counting mode and a same point time counting mode, and a specific counting function supports address read-write operation counting, signal change time counting and code segment execution time counting, and meanwhile meets the counting function of conditional judgment, such as: a time interval in which the consecutive write address 0x1000 is 0; after the operation of the simulation test platform is finished, the module automatically counts the maximum value and the minimum value of the performance data and records the maximum value and the minimum value to a log file.
(4) Chip simulation module
The module mainly develops a soft simulation function according to a chip manual for logic functions, characteristics and time sequences in a chip, and comprises a register function, memory processing, interrupt control, time sequence control and logic judgment function simulation; in the running process, the operation of the register and the memory is monitored in real time, different input data are obtained, and the logic processing of the chip simulation function is driven according to the input data, so that the operations of data transmission, interrupt triggering and the like are further triggered; providing an independent instruction set for each chip simulation, and controlling functions of data transmission, reception, fault setting and the like through the instruction set; and after the chip library operation is received, storing all data generated in the operation process into the file and exiting.
(5) Data control module
Data protocol transmission timing: the data transmission time is controlled, the accuracy of the data time sequence and the transmission process is guaranteed, and data overflow and data loss are prevented.
And (3) judging a protocol structure: and carrying out correctness identification on the overall structure of the transmission data, if the wrong data is stopped from being transmitted, and judging whether the file configuration is carried out according to the passing rule.
Judging the correctness of the protocol: and judging the correctness of the transmitted data content, including frame header, frame count and the like, and if the wrong data is stopped to be transmitted, configuring the file property configuration according to the passing rule.
Protocol checksum processing: and (3) checking and automatically calculating transmission data, and if the calculation is completed, closing an automatic calculation function.
And (3) response control of the protocol: automatically identifying the protocol with response data, acquiring response data content and transmitting data; the data identification rules, data content and response time control may be configured via a configuration file.
(6) Interrupt trigger module
The module integrates all interrupt trigger control and trigger modes, supports single trigger, random trigger, periodic trigger, low level trigger, high level trigger and level edge change trigger, and can set level recovery time and level retention time; corresponding instructions are formulated and provided, through which the triggering of the interrupt is driven.
(7) Log information recording module
The module takes txt files as a storage form, and uniformly records the data information communicated by all the modules. The time, format and file name of the file record are controlled by each module, and the module provides the file writing function and the data receiving port; each module sends data to the log information recording module through the receiving data port.
Data transmission communication type of log information record:
(8) Data analysis module
The module receives a data packet through a port or a network, finds an analysis rule for analyzing the data packet according to an ID in the data packet, unpacks the data of the data packet, displays the converted data in a graphic visualization mode according to the analysis rule, and the display result supports pure data display and display of characters after data translation.
The data analysis rule is configured through an XML file and is automatically loaded during initialization. The method is completed by configuring configuration files according to different analysis modes without protocol understanding, so that flexible application and rapid adaptation of data analysis are realized.
The XML file configuration structure elements are as follows:
the platform generation flow is as follows:
the platform generation mainly comprises four parts of functions: the flow chart of the function library configuration file XML, the engineering file generation, the function library generation and the instruction set generation is shown in figure 2.
The function library configuration file XML is mainly used for configuring relevant library information data such as engineering basic information, processor information, instruction system library information, chip simulation library information, memory address operation library information and the like, and simultaneously supporting instruction templates, default data setting and default association setting of a configuration function library.
The engineering basic information XML configuration elements are as follows:
| sequence number | Element(s) | Description of the invention |
| 1 | DefaultVal | Default setting item |
| 2 | Name | Name setting |
| 3 | Value | Data value, support list configuration |
| 4 | KeyID | The ID value of an element being fixed and unchangeable |
| 5 | ELE | Element configuration start flag |
The processor information XML configuration elements are as follows:
the function module library information XML configuration elements are as follows:
the engineering file generating function mainly comprises the steps of obtaining basic configuration data, function module configuration information and parameters of platform demand items, and then generating an engineering file according to the function module configuration file XML, wherein the content of the file comprises an engineering name, a processor type, a memory use range, a function module name, an association relation among function modules, interrupt trigger setting, and setting of a target code file and a source code file.
The function generated by the function library is mainly to automatically search the function library meeting the requirements through the acquired function library configuration data of the platform requirement items and the information of the function module configuration file XML, generate the library under the designated engineering directory, save the attribute data configuration parameters of the library, and automatically set the association between the function libraries.
The instruction set generation is mainly to automatically search an instruction template supported by the function library according to the generated function library, and automatically generate a corresponding instruction description file and an instruction ID association table according to the instruction template and the function library ID; the instruction names are associated with function library configuration names, and different function library names may generate different instruction names.
The instruction template content format is as follows:
the content of the association relation of the instruction names is as follows:
the invention, in part not described in detail, is within the skill of those skilled in the art.
Claims (10)
1. A simulation test platform, comprising: the system comprises an instruction execution system module, a memory address operation module, a performance statistics module, a chip simulation module, a data control module, an interrupt triggering module, a log information recording module and a data analysis module;
the instruction execution system module loads, analyzes, sends, receives and forwards instructions in the running process of the simulation test platform, receives externally sent instruction data streams, loads instruction files, outputs converted instruction data to a designated module, and drives the corresponding module to perform instruction analysis and execution functions;
the memory address operation module controls and processes the read-write operation of the memory address, and carries out real-time log record on the operated address and data; the memory address operation module receives instruction data from the instruction execution system module and outputs a data stream generated by address operation to the log information recording module;
the performance statistics module performs interval statistics on the execution time of the functional item and supports point-to-point time statistics and same point time statistics; when the operation of the simulation test platform is finished, recording performance related data into a log file;
the chip simulation module carries out soft simulation on logic functions, characteristics and time sequences in the chip, develops different independent chip simulation libraries aiming at different chips, and receives and transmits protocol data streams through the data control module;
the data control module integrates and controls all data protocol transmission time, protocol structure judgment, protocol correctness judgment, protocol checksum processing, protocol response control and instruction analysis and execution;
the interrupt triggering module gathers all interrupt triggering control and triggering modes, and the interrupt triggering module receives instruction data for triggering the interrupt from the instruction execution system module, analyzes and executes the instruction;
the log information recording module records the input and output data information of other modules in the running process to form log information;
the data analysis module analyzes the whole package of data of the protocol and displays the whole package of data in a graphic visualization mode, and the data analysis result supports pure data display and display of characters after data translation; the data analysis module carries out real-time file recording on the result data of the analysis data packet and sends the log data to the log information recording module.
2. The simulation test platform of claim 1, wherein the memory address operation module monitors single or multiple addresses within a certain range, and when software operates on the addresses, the software records data on the operation addresses to the file in real time.
3. The simulation test platform of claim 1, wherein the performance statistics module configures performance statistics attributes according to instructions of the instruction execution system module, including a start address, an end address, an address operation mode, a data start value, a data end value, a performance time effective range; when the starting address and the ending address are the same, counting the time interval of the same address operation data;
after the software operation is finished, the performance statistics module automatically counts the maximum value and the minimum value of the performance data and outputs the starting time of the maximum value and the minimum value; automatically judging whether the statistical time is in the effective range or not, giving out an out-of-range warning prompt, and storing the data into a designated txt file.
4. The simulation test platform of claim 1, wherein the chip simulation module receives the data stream sent by the data control module through the port, analyzes and identifies the data stream, and processes the data through the chip control logic; the chip simulation module sends data to the data control module through the port, the data control module analyzes and processes the data stream, and the structure, the transmission process and the input data of the sent data are the same.
5. The simulation test platform of claim 1, wherein the data control module receives instruction data and protocol data streams through the instruction execution system module and outputs the processed data to the corresponding chip simulation module; and the protocol data received by the chip simulation module is processed and output to the log information recording module.
The data control module receives the instruction data of the instruction execution system module and the output data of the chip simulation module, the instruction execution system module determines a data transmission structure, the chip simulation module determines an output data transmission structure, and the data control module sequentially receives, analyzes and processes the data;
the data control module sends input stream data to the chip simulation module, unpacking source data to the data analysis module and input and output data to the log information recording module for recording.
6. The simulation test platform of claim 1, wherein the data parsing rules in the data parsing module are configured by XML files, and are configured by configuration files for different protocols and parsing modes.
7. A method of generating a simulation test platform according to any one of claims 1 to 6, comprising:
loading a configuration file: the configuration file adopts an XML file structure;
acquiring engineering information: according to the loaded configuration file XML, acquiring basic information, processor information, general function library information and chip simulation library module of corresponding engineering information, storing and managing the data, and providing an interface function for acquiring configuration file information data;
acquiring functional module relation data: acquiring information data such as attributes, pins, data interfaces, association relation among the function libraries, a link mode and the like of the function libraries according to the loaded function library configuration information XML, and storing and managing the data;
data processing is carried out according to the configuration file: analyzing the input demand item according to the information data obtained by the configuration file, obtaining the processor information, the project name, the memory use condition, the interrupt use condition, the function interface and other function interfaces, and generating a corresponding platform file;
generating basic engineering and processor information: automatically generating engineering information, memory data, processor information data and a tested file according to the configuration file and the data acquired by the requirement items;
generating a basic engineering file: creating an engineering file according to the generated engineering information data, wherein the file comprises a processor, a memory, a tested source file, a target code file and engineering attribute data;
obtaining a function library from a container: according to analysis and matching of configuration file information and requirement items, a required function library is obtained, the required function library and corresponding files are automatically extracted from a container, and the function library and the corresponding files are stored under an engineering file designated directory;
generating a function library: the function library obtained from the container is placed under the appointed directory of the engineering file, and function library information comprising library file paths, names, attribute data, communication ports and support pin information is added into the engineering file; the association relation between the corresponding library and other libraries is obtained through configuration data of the configuration file, and link data is automatically generated, wherein the link data comprises port communication links between function libraries, pin links, interrupt pin links between the function libraries and a processor and attribute configuration data values;
generating a test instruction: the test instruction program generating program loads and generates a finished engineering file, and generates an instruction description file and a test instruction and ID corresponding relation file by utilizing a function library ID in the engineering file and instruction ID and name information in the instruction file;
engineering file loading operation: after the test platform engineering file is generated, loading and executing are carried out through the all-digital simulation system VTest, and the instruction driving mechanism is notified to carry out software test work.
8. The method of claim 7, wherein the configuration file includes engineering information, processor information, general function library information, chip simulation library and data control module, and the XML file supports configuration of attributes, pins, data interfaces, association relationships between libraries and links of each function library.
9. The method for generating a simulation test platform according to claim 7, wherein the function library module simulates corresponding chip logic and time sequence, and the types include an instruction execution system module, a memory address operation module, a performance statistics module, a chip simulation module, a data control module, an interrupt trigger module, a log information recording module and a data analysis module.
10. The method for generating a simulation test platform according to claim 7, wherein the engineering file loading operation further comprises: the instruction driver supports the loading of instruction files and scripts, and simultaneously supports the test instructions sent by the universal automatic dynamic test platform DTP.
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