CN110794673A - All-digital bionic circuit and system applied to neurons - Google Patents
All-digital bionic circuit and system applied to neurons Download PDFInfo
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Abstract
The utility model discloses a be applied to bionical circuit of full-digital of neuron and system, wherein, the circuit includes neuron input module, clock selection module, the count module, zero setting time delay module and neuron output module, the count module has pulse signal input end, clock signal input end, zero clearing end and count signal output end, neuron input module is connected with pulse signal input end, clock selection module is connected with clock signal input end, zero setting time delay module is connected with zero clearing end, neuron output module is connected with count signal output end. Based on the embodiment of the application, the neuron signals can be dynamically counted up or down in the neural network, the zero setting signal and the counting signal can be widened through the zero setting delay module, the refractory period of the neuron is simulated, and the data in the counting module is cleared. The bionic circuit adopts a full digital design, not only can simplify the complexity of the circuit, but also can reduce the power consumption of the circuit, and is convenient for realizing large-scale circuit integration.
Description
Technical Field
The invention relates to the field of artificial intelligence, in particular to a full-digital bionic circuit and a full-digital bionic circuit system applied to neurons.
Background
Since the 80 s of the 20 th century, the impulse neuron network becomes a new hot spot for artificial intelligence research due to the strong computing power and the characteristics close to those of biological neurons.
At present, the modeling model of the neuron circuit mainly includes: a Hodgkin-Huxley circuit, a Leaky integration-and-Fire circuit, and an Izhikevich circuit. Although the Hodgkin-Huxley modeling circuit has good dynamic characteristics to be suitable for various pulse modes, as shown in fig. 1, the Hodgkin-Huxley modeling circuit includes a large number of field effect transistors, and the use of a large number of field effect transistors directly increases the complexity of the circuit, which severely restricts the application of the Hodgkin-Huxley modeling circuit in a large-scale neural network or engineering. As shown in fig. 2, which is a simplified schematic diagram of a leak integration-and-Fire modeling circuit, although the leak integration-and-Fire modeling circuit is simpler than the Hodgkin-Huxley modeling circuit, when the integration-and-Fire modeling circuit is used to realize analog characteristics, the bleeder resistance and the cumulative capacitance of the circuit are both large, and the circuit cannot be applied to a large-scale neural network or engineering. Based on the limitations of the two circuits, the Izhikevich modeling circuit is improved, the computational complexity of the Izhikevich modeling circuit is controlled between the Hodgkin-Huxle modeling circuit and the Leaky integral-and-Fire modeling circuit, and the correctness of the biological performance of the Izhikevich modeling circuit is controlled to meet the simulation requirement of a large-scale neural network. But it is only a mathematical fit and lacks information inside the neuron, making neural network coding, dynamics, and hardware difficult to implement.
Disclosure of Invention
The embodiment of the application provides a be applied to complete digital bionic circuit of neuron, includes: the device comprises a neuron input module, a clock selection module, a counting module, a zero setting delay module and a neuron output module;
the counting module is provided with a pulse signal input end, a clock signal input end, a zero clearing end and a counting signal output end;
the neuron input module is connected with the pulse signal input end;
the clock selection module is connected with the clock signal input end;
the zero setting delay module is connected with the zero setting end;
the neuron output module is connected with the counting signal output end.
Further, the neuron input module comprises a first input module, a first not gate and a second not gate;
the first not gate has a first input terminal and a first output terminal;
the second not gate has a second input terminal and a second output terminal;
the first input module is connected with the first input end, the first output end is connected with the second input end, and the second output end is connected with the pulse signal input end.
Furthermore, the clock selection module comprises a gating control end, a first gating signal input end, a second gating signal input end and a gating output end;
the gating control end is connected with the first output end;
the first gating signal input end is used for inputting a first clock signal, and the second gating signal input end is used for inputting a second clock signal;
the gating output end is connected with the clock signal input end.
Furthermore, the neuron output module comprises a latch module and a signal output module;
the latch module comprises a first latch input end and a latch output end;
the signal output module comprises a first signal output end and a second signal output end;
the first latch input end is connected with the counting signal output end;
the latch output end is connected with the first signal output end and the second signal output end.
Furthermore, the zero setting delay module comprises an AND gate and a delay module;
the AND gate comprises a first AND gate input end, a second AND gate input end and an AND gate output end;
the delay module comprises a delay input end and a delay output end;
the delay input end is connected with the output end of the AND gate, and the delay output end is connected with the zero clearing end;
the input end of the first AND gate is used for inputting a zero setting signal, and the input end of the second AND gate is used for inputting a counting signal.
Furthermore, the latch module further comprises a second latch input end;
the second latch input end is connected with the delay output end.
Further, the neuron output module further comprises a third not gate;
the third not gate has a third input terminal and a third output terminal;
the third input end is connected with the latch output end, and the third output end is connected with the second signal output end.
Correspondingly, the embodiment of the application also provides an all-digital bionic system applied to the neurons, and the all-digital bionic system comprises any one of the all-digital bionic circuits applied to the neurons.
The embodiment of the invention has the following beneficial effects:
the invention discloses a full-digital bionic circuit and a system applied to neurons, wherein the circuit comprises a neuron input module, a clock selection module, a counting module, a zero setting delay module and a neuron output module, the counting module is provided with a pulse signal input end, a clock signal input end, a zero setting end and a counting signal output end, the neuron input module is connected with the pulse signal input end, the clock selection module is connected with the clock signal input end, the zero setting delay module is connected with the zero setting end, and the neuron output module is connected with the counting signal output end. Based on the embodiment of the application, the dynamic characteristic of the neuron is simulated by adopting a digital circuit, the neuron input module, the clock selection module, the counting module, the zero setting delay module and the neuron output module can dynamically count the neuron signals upwards or downwards in the neural network, the zero setting delay module can widen the zero setting signal and the counting signal, and the refractory period of the neuron is simulated, so that the data in the counting module is cleared. The bionic circuit adopts a full digital design, not only can simplify the complexity of the circuit, but also can reduce the power consumption of the circuit, and is convenient for realizing large-scale circuit integration.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions and advantages of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a simplified schematic diagram of a prior art Hodgkin-Huxley circuit provided by an embodiment of the present application;
FIG. 2 is a simplified schematic diagram of a prior art Leaky Integrated-and-Fire circuit provided by an embodiment of the present application;
FIG. 3 is a schematic structural diagram of a bionic circuit applied to a neuron according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a neuron input module according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an all-digital bionic circuit applied to a neuron according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of an all-digital bionic circuit applied to a neuron according to an embodiment of the present disclosure;
FIG. 7 is a partial waveform diagram of a timing waveform diagram of an all-digital bionic circuit after being stimulated by an excitation pulse according to an embodiment of the present application;
FIG. 8 is a partial waveform diagram of a timing waveform diagram of an all-digital bionic circuit after being stimulated by a suppression pulse according to an embodiment of the present application;
fig. 9 is a timing waveform diagram of a count signal in a delay bionic circuit according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in further detail with reference to the accompanying drawings. It should be apparent that the described embodiment is only one embodiment of the embodiments of the application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that "embodiment" as referred to herein refers to a particular feature, structure, or characteristic that may be included in at least one implementation of an embodiment of the present application. In the description of the embodiments of the present application, the terms "first", "second", "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to indicate the number of technical features indicated, whereby the features defined as "first", "second", "third" may explicitly or implicitly include one or more such features. Also, the terms "first," "second," and "third" are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order, it being understood that such usage data may be interchanged where appropriate. Furthermore, the terms "comprising," "having," and "being," as well as any variations thereof, are intended to cover non-exclusive inclusions, such as, for example, inclusion of a list of blocks and logic circuits, not necessarily limited to those blocks and logic circuits explicitly listed, but may include blocks and logic circuits not explicitly listed or inherent to the circuits and systems herein.
In the present invention, unless otherwise expressly stated or limited, the terms "connected" and the like are to be construed broadly, e.g., as meaning fixedly attached, detachably attached, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Please refer to fig. 3, which is a schematic structural diagram of an all-digital bionic circuit applied to a neuron according to an embodiment of the present application, including: the neuron-based counting module comprises a neuron input module 100, a clock selection module 200, a counting module 300, a zero delay module 400 and a neuron output module 500, wherein the counting module 300 is provided with a pulse signal input end 310, a clock signal input end 320, a clear end 330 and a counting signal output end 340, the neuron input module 100 is connected with the pulse signal input end 310, the clock selection module 200 is connected with the clock signal input end 320, the zero delay module 400 is connected with the clear end 330, and the neuron output module 500 is connected with the counting signal output end 340.
By adopting the all-digital bionic circuit applied to the neurons, the neuron input module, the clock selection module, the counting module, the zero setting delay module and the neuron output module can dynamically count up or down neuron signals in a neural network, the zero setting delay module can widen the zero setting signals and the counting signals, the refractory period of the neurons is simulated, and data in the counting module is cleared. The bionic circuit adopts a full digital design, not only can simplify the complexity of the circuit, but also can reduce the power consumption of the circuit, and is convenient for realizing large-scale circuit integration.
In this embodiment, the clock selection module 200 includes a gate control terminal 210, a first gate signal input terminal 220, a second gate signal input terminal 230, and a gate output terminal 240; the first strobe signal input terminal 220 is used for inputting a first clock signal, and the second strobe signal input terminal 230 is used for inputting a second clock signal.
In the embodiment of the present application, the neuron input module 100 has various components, and an alternative embodiment is described in detail below.
In an alternative embodiment, as shown in fig. 4, fig. 4 is a schematic structural diagram of a neuron input module provided in an example of the present application, including: a first input module 110, a first not gate 120 and a second not gate 130, wherein the first not gate 120 has a first input terminal 121 and a first output terminal 122, and the second not gate 130 has a second input terminal 131 and a second output terminal 132; the first input module 110 is connected to the first input terminal 121, the first output terminal 122 is connected to the second input terminal 131, the second output terminal 132 is connected to the pulse signal input terminal 310, the gate control terminal 210 is connected to the first output terminal 122, and the gate output terminal 240 is connected to the clock signal input terminal 320.
Based on the schematic structural diagram of an all-digital bionic circuit applied to a neuron shown in fig. 3, a specific implementation of the all-digital bionic circuit applied to the neuron is described below, as shown in fig. 5, fig. 5 is a schematic structural diagram of an all-digital bionic circuit applied to a neuron provided in the embodiment of the present application, including: the neuron-based counting module comprises a neuron input module 100, a clock selection module 200, a counting module 300, a zero delay module 400 and a neuron output module 500, wherein the counting module 300 is provided with a pulse signal input end 310, a clock signal input end 320, a clear end 330 and a counting signal output end 340, the neuron input module 100 is connected with the pulse signal input end 310, the clock selection module 200 is connected with the clock signal input end 320, the zero delay module 400 is connected with the clear end 330, and the neuron output module 500 is connected with the counting signal output end 340.
In a specific embodiment, the clock selection module 200 includes a gate control terminal 210, a first gate signal input terminal 220, a second gate signal input terminal 230, and a gate output terminal 240; the first strobe signal input terminal 220 is used for inputting a first clock signal, the second strobe signal input terminal 230 is used for inputting a second clock signal, the strobe control terminal 210 is connected with the neuron input module 100, and the strobe output terminal 240 is connected with the clock signal input terminal 320.
In a specific embodiment, the neuron output module 500 comprises a latch module 510 and a signal output module 520, wherein the latch module 510 comprises a first latch input 511, a latch output 512 and a second latch input 513; the zero-setting delay module 400 includes an and gate 410 and a delay module 420, wherein the and gate 410 includes a first and gate input terminal 411, a second and gate input terminal 412 and an and gate output terminal 413, and the delay module 420 includes a delay input terminal 421 and a delay output terminal 422; the first latch input terminal 511 is connected to the count signal output terminal 340, the latch output terminal 512 is connected to the first signal output terminal 521 and the second signal output terminal 522, and the second latch input terminal 513 is connected to the delay output terminal 422; the first and gate input terminal 411 is used for inputting a zero setting signal, the second and gate input terminal 412 is used for inputting a counting signal, the and gate output terminal 413 is connected with the delay input terminal 421, and the delay output terminal 422 is connected with the clear terminal 330.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an all-digital bionic circuit applied to a neuron according to an embodiment of the present disclosure. The figure includes: the counting module is provided with a pulse signal input end, a clock signal input end, a zero clearing end and a counting signal output end, the neuron input module is connected with the pulse signal input end, the clock selection module is connected with the clock signal input end, the zero clearing delay module is connected with the zero clearing end, and the neuron output module is connected with the counting signal output end.
The figure also includes a pulse signal inSpike, a first strobe signal input terminal 220 and an input first Clock signal inSpikeA, a second strobe signal input terminal 230 and an input second Clock signal Clock, a zero setting signal Reset, and a count signal OutSpike.
Based on the above all-digital bionic circuit applied to the neuron, a specific bionic counting mode is introduced below.
Fig. 7 is a partial waveform diagram of a timing waveform diagram of an all-digital bionic circuit after stimulation by an excitation pulse according to an embodiment of the present application. When the counting module 300 counts up, the neuron input module 100 outputs a neuron signal, the pulse signal input terminal 310 receives the pulse signal inSpike shown in fig. 7, and after a certain time delay, the pulse signal inSpike is divided into two paths of signals, one path of signal is used as an enable signal of the clock selection module 200, and is transmitted to the gating output terminal 240 through an inverter or a not gate, and is input to the clock selection module 200 as an enable signal, and the first clock signal inSpike a input by the first gating signal input terminal 220 is selected; the other path is input to the counting module 300 through the pulse signal input terminal 310, and at the rising edge of the first clock signal inSpikeA, the excitation pulse "1" in the neuron signal is counted up, i.e., +1 counting, so as to obtain an up-count signal outSpike.
Fig. 8 is a partial waveform diagram of a timing waveform diagram of an all-digital bionic circuit after being stimulated by a suppressed pulse according to an embodiment of the present application. When the counting module 300 counts down, the neuron input module 100 outputs a neuron signal, the pulse signal input end 310 receives the pulse signal inSpike 'shown in fig. 8, and after a certain time delay, the pulse signal inSpike' is divided into two paths of signals, one path of signals is used as an enable signal of the clock selection module 200, is transmitted to the strobe output end 240 through the inverter or the not gate, and is input to the clock selection module 200 as an enable signal, and the second clock signal clock input by the second strobe signal input end 230 is selected; the other path is input to the counting module 300 through the pulse signal input terminal 310, and at the rising edge of the clock signal clock, the count-down signal outSpike' is obtained by counting down the inhibitory pulse "0" in the neuron signal, i.e., -1, and when the output of the neuron output module 500 is all 0, it indicates that the neuron is in a quiet state.
Fig. 9 is a timing waveform diagram of a count signal in a delay bionic circuit according to an embodiment of the present disclosure. When the counting module 300 is set to zero, the first and gate input terminal 411 inputs a zero signal, which is an externally provided signal, the second and gate input terminal 412 inputs a counting signal, outputs a zero signal a before delay after the and operation, and then enters the counting module through the delay module 420The zero-setting delay signal b is output after line widening, that is, the zero-setting signal a before delay is prolonged by t as a time sequence pulsedA length of time to ensure that the neural network is at this tdIn the refractory period within the time length, no matter the pulse signal input end of the counting module 300 receives excitation pulse "1" or inhibition pulse "0", the bionic circuit does not react, so that the counting signal in the counting module 300 is cleared, meanwhile, the zero-setting delay signal b is input into the second latch input end 513 through the delay output end 422, and is latched in the latch module 510, so that the output of the zero-setting delay signal b in advance is prevented.
The embodiment of the present application further provides an all-digital bionic system applied to a neuron, which includes the all-digital bionic circuit applied to the neuron described in any of the above embodiments.
In the embodiment of the present application, the neuron input module 100 of the all-digital bionic circuit is connected to an output end of a front-end signal in the bionic system, and the neuron output module 500 is connected to an input end of a back-end signal in the bionic system.
As can be seen from the above full-digital bionic circuit or system applied to neurons, the bionic circuit in the present application includes a neuron input module 100, a clock selection module 200, a counting module 300, a zero delay module 400 and a neuron output module 500, wherein the counting module 300 has a pulse signal input terminal 310, a clock signal input terminal 320, a clear terminal 330 and a count signal output terminal 340, the neuron input module 100 is connected to the pulse signal input terminal 310, the clock selection module 200 is connected to the clock signal input terminal 320, the zero delay module 400 is connected to the clear terminal 330, and the neuron output module 500 is connected to the count signal output terminal 340. Based on the embodiment of the application, the dynamic characteristic of the neuron is simulated by adopting a digital circuit, the neuron input module, the clock selection module, the counting module, the zero setting delay module and the neuron output module can dynamically count the neuron signals upwards or downwards in the neural network, the zero setting delay module can widen the zero setting signal and the counting signal, and the refractory period of the neuron is simulated, so that the data in the counting module is cleared. The bionic circuit adopts a full digital design, not only can simplify the complexity of the circuit, but also can reduce the power consumption of the circuit, and is convenient for realizing large-scale circuit integration.
It should be noted that: the foregoing descriptions of the embodiments of the present application are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be implemented.
All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment is described with emphasis on differences from other embodiments. In particular, as for the embodiment of the apparatus, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
Those skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing associated hardware, and the program may be stored in a computer readable medium.
The foregoing is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the embodiment of the present application, and these modifications and decorations are also considered to be the protection scope of the embodiment of the present application.
Claims (8)
1. An all-digital biomimetic circuit for application to a neuron, comprising: the device comprises a neuron input module, a clock selection module, a counting module, a zero setting delay module and a neuron output module;
the counting module is provided with a pulse signal input end, a clock signal input end, a zero clearing end and a counting signal output end;
the neuron input module is connected with the pulse signal input end;
the clock selection module is connected with the clock signal input end;
the zero setting delay module is connected with the zero clearing end;
the neuron output module is connected with the counting signal output end.
2. The circuit of claim 1, wherein the neuron input module 100 comprises a first input module, a first not gate, and a second not gate;
the first not gate has a first input and a first output;
the second not gate has a second input and a second output;
the first input module is connected with the first input end, the first output end is connected with the second input end, and the second output end is connected with the pulse signal input end.
3. The circuit of claim 2, wherein the clock selection module 200 comprises a strobe control terminal, a first strobe signal input terminal, a second strobe signal input terminal, and a strobe output terminal;
the gating control end is connected with the first output end;
the first gating signal input end is used for inputting a first clock signal, and the second gating signal input end is used for inputting a second clock signal;
the gating output end is connected with the clock signal input end.
4. The circuit of claim 1, wherein the neuron output module comprises a latch module and a signal output module;
the latch module comprises a first latch input end and a latch output end;
the signal output module comprises a first signal output end and a second signal output end;
the first latch input end is connected with the counting signal output end;
the latch output is connected with the first signal output end and the second signal output end.
5. The circuit of claim 4, wherein the zero-setting delay module comprises an AND gate and a delay module;
the AND gate comprises a first AND gate input end, a second AND gate input end and an AND gate output end;
the delay module comprises a delay input end and a delay output end;
the delay input end is connected with the output end of the AND gate, and the delay output end is connected with the zero clearing end;
the input end of the first AND gate is used for inputting a zero setting signal, and the input end of the second AND gate is used for inputting a counting signal.
6. The circuit of claim 5, wherein the latch module further comprises a second latch input;
the second latch input end is connected with the delay output end.
7. The circuit of claim 5, wherein the neuron output module further comprises a third not gate;
the third not gate has a third input and a third output;
the third input end is connected with the latch output end, and the third output end is connected with the second signal output end.
8. An all-digital biomimetic system for application to neurons, comprising the all-digital biomimetic circuit for application to neurons of any of claims 1-7.
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