CN110794234B - On-line monitoring method for residual life of direct-current supporting capacitor of PWM converter - Google Patents
On-line monitoring method for residual life of direct-current supporting capacitor of PWM converter Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
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Abstract
The invention relates to an online monitoring system and method for the residual life of a direct-current supporting capacitor of a PWM converter. The system comprises a control hardware framework and a software framework, wherein the main functions of the hardware system framework comprise: voltage and current signal acquisition, control system PWM output, system protection action, core algorithm operation and the like; the software architecture comprises a program calculation flow, a capacitance parameter core algorithm and an upper computer communication interface design. The online monitoring system is suitable for monitoring the residual life of the intermediate direct current side supporting capacitor of most AC-DC-AC converter systems, a new sensor is not needed, the normal running state of the system is not changed, and the actual measurement precision error is less than 5%.
Description
Technical Field
The invention relates to the technical field of monitoring, in particular to an online monitoring method for the residual life of a direct-current support capacitor of a PWM converter.
Background
The existing direct current side supporting capacitor residual life monitoring scheme is mainly divided into a data driving scheme and a model basic scheme. The data driving scheme mostly adopts an artificial intelligence algorithm, such as a genetic network algorithm, a fuzzy algorithm and the like to fit a capacitor life model, and the residual life of the actual capacitor is estimated by using a model result of offline training of a large amount of data. The scheme depends on the accuracy of a life model and the effectiveness of data training, is only suitable for the same batch of products with the same manufacturing process, and has no universality. Model base schemes are broadly divided into two types, offline and online, wherein the offline scheme requires the capacitor to be removed from the circuit and is therefore limited to many application scenarios; while the online monitoring schemes provided in the current literature all have some drawbacks: some schemes require the converter to work in abnormal operation states, such as shutdown and startup; some schemes require changing the topology of the circuit or adding new hardware circuits, increasing manufacturing costs. In the actual converter system, a plurality of application occasions, such as an uninterruptible power supply system and the like, are provided, and the converter is not allowed to stop operation under normal conditions.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to provide the online monitoring method for the residual life of the direct-current supporting capacitor of the PWM converter, and the online monitoring system can monitor the residual life of the direct-current side supporting capacitor under the condition of normal operation of the PWM converter without changing circuit topology or adding hardware equipment newly. The system truly realizes the real-time online monitoring of the residual life of the capacitor; the system realizes accurate measurement of capacitance equivalent parameters by only using the existing sensors for the system control strategy in the PWM converter system; the system calculates parameters for predicting the residual life of the capacitor, wherein the parameters comprise equivalent capacitance values and equivalent series resistance values, so that the system is suitable for different types of supporting capacitors, such as electrolytic capacitors, film capacitors and the like.
In order to achieve the above purpose, the invention adopts the following technical scheme:
The on-line monitoring method for the residual life of the direct-current supporting capacitor of the PWM converter is applied to an on-line monitoring system which adopts a DSP+FPGA architecture and comprises the following steps: the device comprises a core board, a bottom board, an AD7656 sampling module, a W5300 communication module and an upper computer; the core board comprises a DSP system and an FPGA minimum system; the DSP system includes: the system comprises a DSP minimum system and a plug-in storage unit; the plug-in storage unit includes: the AD7656 sampling module comprises 3 AD7656 chips and a low-pass filter, the W5300 communication module comprises WIZnet W5300 chips and an Ethernet transformer,
The data address bus, the PWM output signal line, the BOOT guide signal line and the general input/output signal line of the DSP chip are all connected with the FPGA chip; the EM1CS2 pin of the DSP chip is connected with the FLASH chip and is used for chip selection of the FLASH chip; the EM1CS3 pin of the DSP chip is connected with the RAM chip and is used for selecting the RAM chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the FLASH chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the RAM chip; the 19-bit address bus and the 16-bit data bus of the DSP chip are respectively connected with the address pin and the data pin of the FLASH chip; the 19-bit address bus and the 16-bit data bus of the DSP chip are respectively connected with the address pin and the data pin of the RAM chip;
An EM1CS4 pin of the DSP chip is connected with a pin CS of the WIZnet W5300 chip, an EM1OE pin and an EM1WE pin of the DSP chip are respectively connected with a read pin and a write pin of the WIZnet W5300 chip, an 8-bit address bus of the DSP chip is connected with an address line input pin of the WIZnet W5300 chip, and a 16-bit data bus of the DSP chip is connected with a data input pin of the WIZnet W5300 chip;
The 12 GPIO pins of the FPGA chip are respectively connected with a chip selection pin CS, a RESET signal pin RESET, a feedback signal pin BUSY and a start conversion signal pin CONVST of the 3 AD7656 chips, and the data pins of the 3 AD7656 chips are connected with a 16-bit data bus of the DSP chip; the input pins of the 6 paths of sampling of the AD7656 chip are connected with the output end of a low-pass filter, the input end of one low-pass filter is connected with a voltage sensor, and the input end of the other low-pass filter is connected with a current sensor;
The bottom plate is connected with the core plate and provides power for a control chip of the core plate; the expansion interface of the core board comprises: the system comprises a plurality of protocol serial communication interfaces, an ADC sampling input interface, a data address bus interface, a PWM output interface and a plurality of digital input/output interfaces;
The monitoring method comprises the following steps:
step S1, a DSP chip enters a system initialization process, a system phase-locked loop, system interruption and peripheral registers are configured, after the initialization of the DSP chip is completed, a data bus and a read-write chip wire selection configuration WIZnet W5300 chip are utilized to configure the system into a TCP communication mode, meanwhile, an FPGA chip solidifies a program circuit in an active serial mode and performs initialization operation on an AD7656 chip, and after the configuration of the DSP chip is completed, a synchronization signal for the completion of the configuration of the FPGA chip is waited;
Step S2, the online monitoring system enters a main circulation and interrupt mode: in the main cycle, the DSP chip performs TCP communication with the upper computer through the WIZnet W5300 chip, and transmits data and instruction signals; in an interrupt mode, the online monitoring system sequentially and circularly executes an AD sampling state, an SVPWM algorithm state, an AD sampling state and a core algorithm state, and executes one state every time of interrupt, wherein the AD sampling is that a DSP chip sends a sampling instruction to an FPGA chip, and the FPGA chip executes chip selection and data reading operation on the AD7656 chip and transmits data back to the DSP chip; the SVPWM algorithm calculates and generates PWM output pulses for the DSP chip, transmits the PWM output pulses to the FPGA chip to supplement dead zones, and finally transmits the PWM output pulses to the driving circuit to drive the switching tube of the main circuit to act; the method comprises the steps that a core algorithm is used in a core algorithm state, the core algorithm is used for completing calculation of capacitance equivalent impedance and equivalent impedance angle, calculated data are sent to a receiving and transmitting buffer of a WIZnet W5300 chip in a main cycle, and the WIZnet W5300 chip sends the received data to an upper computer;
S3, the upper computer calculates an ideal capacitance value C and an equivalent resistance value ESR in the first-order serial equivalent circuit of the capacitor according to the received data, or directly receives the calculated C and ESR, compares the calculated ideal capacitance value and equivalent resistance value with the capacitance value and equivalent resistance value of the initial state of the capacitor, and estimates the health state and the residual life of the capacitor;
The core algorithm is as follows:
Firstly, sampling capacitor voltage and current, then sending the sampled capacitor voltage and current data to a DSP chip, and calculating harmonic amplitude and phase angle of specified times of the capacitor voltage and the capacitor current in real time by the DSP chip by adopting a discrete Fourier algorithm, so as to calculate equivalent impedance and equivalent impedance angle of the capacitor;
or the core algorithm is as follows: firstly, sampling capacitor voltage and current, then transmitting the acquired capacitor voltage and current data to an upper computer by utilizing WIZnet W5300 chips, processing the capacitor voltage and current data by utilizing an equal-ripple FIR filter by the upper computer to obtain a waveform diagram of specified voltage and current harmonics, and calculating to obtain capacitor equivalent impedance and equivalent impedance angle according to the waveform diagram;
Or the core algorithm is as follows: firstly, sampling capacitor voltage and current, then transmitting the acquired capacitor voltage and current data to an upper computer by utilizing WIZnet W5300 chips, processing the capacitor voltage and current data by utilizing a Butterworth IIR filter by utilizing the upper computer, obtaining a waveform diagram of specified voltage and current harmonics, and calculating according to the waveform diagram to obtain the equivalent impedance and equivalent impedance angle of the capacitor.
Preferably, the on-line monitoring system employs an expandable connector design that allows the user to freely design the backplane for the functions and target functions of the core board.
Preferably, the DSP system adopts a window voltage detection chip to carry out overvoltage and undervoltage protection circuit design, and carries out protection and reset operation on the DSP system; the DSP minimum system unit comprises a crystal oscillator circuit, a reset circuit, a power circuit, a guide mode setting circuit and a JTAG interface circuit; the model of the DSP chip is TMS320F28377d; the DSP system also includes a plurality of data communication protocols including I 2 C, SCI, SPI, CAN, USB; the DSP system is provided with an ADC sampling module and is used for realizing differential input signal sampling with 16-bit precision and single-end input signal sampling with 12-bit precision.
Preferably, the FLASH chip adopts an SST39VF822 chip, and the RAM chip adopts an IS61LV25616AL-10TLI chip; the W5300 communication module is connected and communicated with the upper computer through an Ethernet transformer HR 911103A.
Preferably, the communication interface of the upper computer comprises an oscilloscope part, a capacitance equivalent circuit, a capacitance life and a capacitance state; the oscillograph part comprises an oscillograph control box, a waveform display frame and an oscillograph setting part, and is used for observing the capacitor voltage and the capacitor current waveforms obtained by sampling; the capacitance equivalent circuit adopts a first-order series resistance-capacitance equivalent circuit, and different algorithms are selected to calculate the actual capacitance value.
Preferably, the FPGA minimum system comprises a power circuit, a clock circuit, a JTAG circuit, a programming configuration circuit and an input/output circuit, wherein the power circuit is used for supplying power to an FPGA chip and supplying power to a core and providing reference level for the FPGA core; the clock circuit comprises a 50MHz clock signal input provided by an external active crystal oscillator circuit and a synchronous clock signal input output by a DSP chip; the JTAG circuit is used for burning programs and debugging chips on line; the programming configuration circuit adopts a four-way serial configuration chip EPCQ, and the programming mode is selected as an active serial mode and is used for solidifying a program circuit when the FPGA chip is electrified and started; the input-output circuit comprises a digital input and a digital output, and can be freely designed.
Drawings
The invention has the following drawings:
FIG. 1 is a block diagram I of an on-line monitoring system according to the present invention;
FIG. 2 is a block diagram of an on-line monitoring system according to the present invention;
FIG. 3 is a flow chart of a software control system according to the present invention;
FIG. 4 is a core algorithm processing flow diagram;
Fig. 5 is a diagram of a host communication interface.
Detailed Description
The invention is described in further detail below with reference to fig. 1-5.
The invention provides a capacitor residual life online monitoring system, which is shown in figures 1 and 2:
The monitoring system adopts a DSP TMS320F28377 d+FPGA cycle 10 LP architecture, wherein a data address bus, a PWM output signal line, a BOOT guide signal line and a general input/output signal line of a DSP chip are connected with the FPGA chip, so that the expanded functions of reset starting, data transmission, system protection and the like of the DSP system are completed. The DSP chip is used as a leading chip of the monitoring system to determine the program flow and the bus data flow direction. The FPGA chip is used as an auxiliary chip of the monitoring system to complete auxiliary functions such as data acquisition and transmission, system protection and the like. The monitoring system has the characteristics of strong computing capability, high response speed, high data throughput, large program and data space and the like, and can meet the higher real-time requirement of the monitoring system.
The power supply modules of the DSP system and the FPGA minimum system convert input voltages through DCDC power supply chips in the modules, and output voltages with different grades to respectively provide power supply and reference level for digital processing chips in the DSP system and the FPGA minimum system. In addition, the DSP system also adopts a window voltage detection chip to carry out overvoltage and undervoltage protection circuit design, and protects and resets the DSP system when necessary.
The DSP system comprises a DSP minimum system and an externally hung storage unit. The DSP minimum system comprises a crystal oscillator circuit, a reset circuit, a power circuit, a guide mode setting circuit and a JTAG interface circuit, so as to ensure that the DSP chip normally operates in various modes. The plug-in storage unit IS composed of two storage chips of FLASH SST39VF822+RAM IS61LV25616AL-10TLI, chip selection and data reading and writing are carried out through an EMIF (External Memory Interfaces, external memory interface) function of the DSP chip, wherein an EM1CS2 pin IS used for chip selection of the FLASH chip, an EM1CS3 pin IS used for chip selection of the RAM chip, EM1OE and EM1WE pins are respectively used for reading and writing operations of the FLASH chip and the RAM chip, a 19-bit address bus and a 16-bit data bus are connected to address data pins of the FLASH chip and the RAM chip, and the two storage chips are used for expanding programs and data storage spaces. In addition, DSP systems include a variety of data communication protocols, including I 2 C, SCI, SPI, CAN, USB, etc., which are suitable for most serial communication systems. In addition, the DSP system is provided with an ADC sampling module, so that 16-bit precision differential input signal sampling and 12-bit precision single-end input signal sampling can be realized.
The FPGA minimum system comprises a power circuit, a clock circuit, a JTAG circuit, a programming configuration circuit and an input-output circuit. The power supply circuit is used for supplying power to the FPGA chip and supplying power to the core and providing reference level for the FPGA core. The clock circuit includes a 50MHz clock signal input provided by an external active crystal oscillator circuit and a synchronous clock signal input output by the DSP chip. The JTAG circuit is used for burning programs and debugging chips on line. The programming configuration circuit adopts a four-way serial configuration chip EPCQ, and the programming mode is selected as an active serial mode and is used for solidifying the program circuit when the FPGA chip is powered on and started. The input/output circuit comprises digital input and output, can be designed freely, and interfaces designed by the on-line monitoring system comprise a PWM signal output interface, a system fault signal input interface, a system control signal output interface and the like.
In addition, the on-line monitoring system also designs an analog signal sampling module and an Ethernet communication module based on bus communication. The analog signal sampling module is provided with 3 AD7656 chips, 12 GPIO ports of the FPGA chips are respectively connected to chip selection pins CS, RESET signals RESET, feedback signals BUSY and starting conversion signals CONVST of the 3 AD7656 chips through chip selection control of the FPGA chips, converted data are transmitted to a 16-bit data bus of the DSP chips, and reading operation can be performed through the DSP chips or the FPGA chips. The analog signal sampling chip adopts an industrial CMOS design, supports 18 paths of true bipolar and high-impedance ADC signal input, has a voltage input range of-6V to +6V, has a throughput rate as high as 250kSPS, is internally provided with a low-noise and wide-bandwidth sampling and holding amplifier, and can process the input frequency of 12 MHz at most. The Ethernet communication module is designed based on WIZnet W5300 chips, and is controlled by chip selection of EMIF functions of the DSP chips, an EM1CS4 pin is connected to a CS pin of the W5300 chip, an EM1OE pin and an EM1WE pin are respectively connected to a read-write pin of the W5300 chip, an 8-bit address line in a data address bus is connected to an address line input pin of the W5300 chip, and a 16-bit data line is connected to a data input pin of the W5300 chip, so that independent configuration and use of the DSP chips or the FPGA chips are supported. The Ethernet communication chip is designed by adopting a CMOS process, internally integrates a 10/100M Ethernet controller, supports various communication protocol technologies such as TCP, UDP, IPv, ICMP, ARP and PPPoE, and internally comprises a 128K-byte communication data memory and 8 independent ports. The module is connected and communicated with an upper computer through an Ethernet transformer HR 911103A.
In addition, the monitoring system provided by the invention adopts an expandable connector design and is divided into a core plate and a bottom plate. The core board is composed of a DSP minimum system unit, an external storage unit and an FPGA minimum system, and the expansion interface part of the core board comprises a plurality of protocol serial communication interfaces, an ADC sampling input interface, a data address bus interface, a PWM output interface and a plurality of digital input/output interfaces. The base plate is connected with the core plate and provides power for a control chip of the core plate, the serial communication interface is used for providing an interface for hardware peripherals, the ADC sampling input interface is used for being connected with the output end of the filter circuit, the PWM output interface is used for outputting PWM signals, and the digital input and output interface is used for inputting digital signals or outputting digital signals. Meanwhile, the base plate is provided with a core board bus, and an AD7656 sampling module and a W5300 communication module are designed. The design of the connector allows the user to freely design the backplane for core board functions and target functions.
The invention provides a capacitor residual life online monitoring system which comprises the following software control system:
The basic calculation flow of the software is as shown in fig. 3:
After the software is started, the DSP chip enters a system initialization process to configure a system phase-locked loop, system interrupt, peripheral registers and the like. After the initialization of the DSP chip is completed, the W5300 chip is configured into a TCP communication mode by utilizing a data bus and a read-write chip wire. At the same time, the FPGA chip solidifies the program circuit in an active serial mode and performs initialization operation on the AD7656 chip. The DSP chip is used as a system main control chip, waits for a synchronous signal of finishing the configuration of the FPGA chip after the configuration is finished, and then enters a main circulation and interrupt mode. In the main cycle, the DSP chip performs TCP communication with the host computer through the W5300 chip, and transmits data and command signals. In the interrupt program, the on-line monitoring system is divided into a plurality of states including states of AD sampling, SVPWM algorithm, core algorithm and the like, the states are customized by a user, the states are sequentially and circularly executed, and each interrupt executes a state operation. The AD sampling state is that the DSP chip sends a sampling instruction to the FPGA chip, and the FPGA chip performs chip selection and data reading operation on the AD7656 chip and transmits data back to the DSP chip. The SVPWM state is calculated by the DSP chip and generates PWM output pulse, the PWM output pulse is transmitted to the FPGA chip to supplement dead zone, and then PWM signals are transmitted to the driving circuit to drive the main circuit switch tube to act. The core algorithm completes the calculation of the capacitance equivalent impedance and the equivalent impedance angle, and sends the calculated data to the transceiver buffer of W5300 for waiting for data transmission in the main loop part of the program, and this state is called TCP communication state.
Based on the above hardware and software systems, the present invention provides the following core algorithm, as shown in fig. 4.
Firstly, capacitance voltage and current data are sampled, and three processing schemes exist after sampling: the scheme 1 utilizes the high-performance computing capability of the DSP chip, and adopts a discrete Fourier algorithm to calculate harmonic amplitude and phase angle of specified times of capacitor voltage and capacitor current in real time, so as to calculate the equivalent impedance value and equivalent impedance angle of the capacitor. In the scheme 2 and the scheme 3, the collected capacitance current data is transmitted to an upper computer by utilizing the high-speed communication rate of the W5300 chip, and then the sampled data is processed by utilizing a high-performance filter. The difference is that the scheme 2 adopts an equal ripple FIR filter, the scheme 3 adopts a Butterworth IIR filter, a waveform diagram of the specified subvoltage current harmonic is obtained after band-pass filtering, and the capacitance equivalent impedance value and the equivalent impedance angle are obtained according to the waveform diagram. And finally, calculating the ideal capacitance value C and the equivalent resistance ESR in the first-order series equivalent circuit of the capacitor according to the impedance value and the impedance angle and the harmonic frequency. And comparing the calculated capacitance value and equivalent resistance value with the capacitance value and equivalent resistance value of the initial state of the capacitor, so that the health state and the residual life of the capacitor can be estimated.
Meanwhile, the invention designs an upper computer communication interface shown in fig. 5, which is used for predicting the residual life of the capacitor.
The interface consists of an oscilloscope, a capacitance equivalent circuit, a capacitance service life and a capacitance state. The oscilloscope part comprises an oscilloscope control box, a waveform display frame and an oscilloscope setting part, and is used for observing the capacitance voltage and capacitance current waveforms obtained by sampling. The capacitance equivalent circuit adopts a first-order series resistance-capacitance equivalent circuit, and the actual capacitance value obtained by calculation of different algorithms is selected, so that the equivalent resistance value can be displayed in the area. In order to take into account the effect of temperature on the equivalent resistance, this functional area also includes a display of the temperature. The capacitor life first needs to set an initial capacitance value and an initial equivalent resistance value, and the residual life ratio is given according to the calculated value. The failure occurrence rate refers to the probability that the capacitor may fail. The capacitor state indicates the current state of the capacitor according to the residual life ratio of the capacitor and the fault occurrence rate.
What is not described in detail in this specification is prior art known to those skilled in the art.
Claims (6)
1. A method for monitoring the residual life of DC supporting capacitor of PWM converter on line is characterized by that,
The following online monitoring system is applied, wherein the monitoring system adopts a DSP+FPGA architecture and comprises: the device comprises a core board, a bottom board, an AD7656 sampling module, a W5300 communication module and an upper computer; the core board comprises a DSP system and an FPGA minimum system; the DSP system includes: the system comprises a DSP minimum system and a plug-in storage unit; the plug-in storage unit includes: the AD7656 sampling module comprises 3 AD7656 chips and a low-pass filter, the W5300 communication module comprises WIZnet W5300 chips and an Ethernet transformer,
The data address bus, the PWM output signal line, the BOOT guide signal line and the general input/output signal line of the DSP chip are all connected with the FPGA chip; the EM1CS2 pin of the DSP chip is connected with the FLASH chip and is used for chip selection of the FLASH chip; the EM1CS3 pin of the DSP chip is connected with the RAM chip and is used for selecting the RAM chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the FLASH chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the RAM chip; the 19-bit address bus and the 16-bit data bus of the DSP chip are respectively connected with the address pin and the data pin of the FLASH chip; the 19-bit address bus and the 16-bit data bus of the DSP chip are respectively connected with the address pin and the data pin of the RAM chip;
An EM1CS4 pin of the DSP chip is connected with a pin CS of the WIZnet W5300 chip, an EM1OE pin and an EM1WE pin of the DSP chip are respectively connected with a read pin and a write pin of the WIZnet W5300 chip, an 8-bit address bus of the DSP chip is connected with an address line input pin of the WIZnet W5300 chip, and a 16-bit data bus of the DSP chip is connected with a data input pin of the WIZnet W5300 chip;
The 12 GPIO pins of the FPGA chip are respectively connected with a chip selection pin CS, a RESET signal pin RESET, a feedback signal pin BUSY and a start conversion signal pin CONVST of the 3 AD7656 chips, and the data pins of the 3 AD7656 chips are connected with a 16-bit data bus of the DSP chip; the input pins of the 6 paths of sampling of the AD7656 chip are connected with the output end of a low-pass filter, the input end of one low-pass filter is connected with a voltage sensor, and the input end of the other low-pass filter is connected with a current sensor;
The bottom plate is connected with the core plate and provides power for a control chip of the core plate; the expansion interface of the core board comprises: the system comprises a plurality of protocol serial communication interfaces, an ADC sampling input interface, a data address bus interface, a PWM output interface and a plurality of digital input/output interfaces;
The monitoring method comprises the following steps:
step S1, a DSP chip enters a system initialization process, a system phase-locked loop, system interruption and peripheral registers are configured, after the initialization of the DSP chip is completed, a data bus and a read-write chip wire selection configuration WIZnet W5300 chip are utilized to configure the system into a TCP communication mode, meanwhile, an FPGA chip solidifies a program circuit in an active serial mode and performs initialization operation on an AD7656 chip, and after the configuration of the DSP chip is completed, a synchronization signal for the completion of the configuration of the FPGA chip is waited;
Step S2, the online monitoring system enters a main circulation and interrupt mode: in the main cycle, the DSP chip performs TCP communication with the upper computer through the WIZnet W5300 chip, and transmits data and instruction signals; in an interrupt mode, the online monitoring system sequentially and circularly executes an AD sampling state, an SVPWM algorithm state, an AD sampling state and a core algorithm state, and executes one state every time of interrupt, wherein the AD sampling is that a DSP chip sends a sampling instruction to an FPGA chip, and the FPGA chip executes chip selection and data reading operation on the AD7656 chip and transmits data back to the DSP chip; the SVPWM algorithm calculates and generates PWM output pulses for the DSP chip, transmits the PWM output pulses to the FPGA chip to supplement dead zones, and finally transmits the PWM output pulses to the driving circuit to drive the switching tube of the main circuit to act; the method comprises the steps that a core algorithm is used in a core algorithm state, the core algorithm is used for completing calculation of capacitance equivalent impedance and equivalent impedance angle, calculated data are sent to a receiving and transmitting buffer of a WIZnet W5300 chip in a main cycle, and the WIZnet W5300 chip sends the received data to an upper computer;
S3, the upper computer calculates an ideal capacitance value C and an equivalent resistance value ESR in the first-order serial equivalent circuit of the capacitor according to the received data, or directly receives the calculated C and ESR, compares the calculated ideal capacitance value and equivalent resistance value with the capacitance value and equivalent resistance value of the initial state of the capacitor, and estimates the health state and the residual life of the capacitor;
The core algorithm is as follows:
Firstly, sampling capacitor voltage and current, then sending the sampled capacitor voltage and current data to a DSP chip, and calculating harmonic amplitude and phase angle of specified times of the capacitor voltage and the capacitor current in real time by the DSP chip by adopting a discrete Fourier algorithm, so as to calculate equivalent impedance and equivalent impedance angle of the capacitor;
or the core algorithm is as follows: firstly, sampling capacitor voltage and current, then transmitting the acquired capacitor voltage and current data to an upper computer by utilizing WIZnet W5300 chips, processing the capacitor voltage and current data by utilizing an equal-ripple FIR filter by the upper computer to obtain a waveform diagram of specified voltage and current harmonics, and calculating to obtain capacitor equivalent impedance and equivalent impedance angle according to the waveform diagram;
Or the core algorithm is as follows: firstly, sampling capacitor voltage and current, then transmitting the acquired capacitor voltage and current data to an upper computer by utilizing WIZnet W5300 chips, processing the capacitor voltage and current data by utilizing a Butterworth IIR filter by utilizing the upper computer, obtaining a waveform diagram of specified voltage and current harmonics, and calculating according to the waveform diagram to obtain the equivalent impedance and equivalent impedance angle of the capacitor.
2. The method for online monitoring of residual life of a dc supporting capacitor of a PWM converter according to claim 1, wherein the online monitoring system employs an expandable connector design that allows a user to freely design a backplane for functions and target functions of the core board.
3. The on-line monitoring method for the residual life of a direct-current support capacitor of a PWM converter according to claim 1, wherein the DSP system adopts a window voltage detection chip to perform overvoltage and undervoltage protection circuit design, and performs protection and reset operations on the DSP system; the DSP minimum system unit comprises a crystal oscillator circuit, a reset circuit, a power circuit, a guide mode setting circuit and a JTAG interface circuit; the model of the DSP chip is TMS320F28377d; the DSP system also includes a plurality of data communication protocols including I 2 C, SCI, SPI, CAN, USB; the DSP system is provided with an ADC sampling module and is used for realizing differential input signal sampling with 16-bit precision and single-end input signal sampling with 12-bit precision.
4. The method for online monitoring the residual life of a direct-current support capacitor of a PWM converter according to claim 1, wherein the FLASH chip adopts an SST39VF822 chip and the RAM chip adopts an IS61LV25616AL-10TLI chip; the W5300 communication module is connected and communicated with the upper computer through an Ethernet transformer HR 911103A.
5. The method for online monitoring the residual life of a direct-current support capacitor of a PWM converter according to claim 1, wherein the communication interface of the upper computer comprises an oscilloscope part, a capacitor equivalent circuit, a capacitor life and a capacitor state; the oscillograph part comprises an oscillograph control box, a waveform display frame and an oscillograph setting part, and is used for observing the capacitor voltage and the capacitor current waveforms obtained by sampling; the capacitance equivalent circuit adopts a first-order series resistance-capacitance equivalent circuit, and different algorithms are selected to calculate the actual capacitance value.
6. The on-line monitoring method for the residual life of a direct current support capacitor of a PWM converter according to claim 1, wherein the FPGA minimum system comprises a power circuit, a clock circuit, a JTAG circuit, a programming configuration circuit and an input/output circuit, wherein the power circuit is used for supplying power to an FPGA chip and supplying power to a core and providing a reference level for the FPGA core; the clock circuit comprises a 50MHz clock signal input provided by an external active crystal oscillator circuit and a synchronous clock signal input output by a DSP chip; the JTAG circuit is used for burning programs and debugging chips on line; the programming configuration circuit adopts a four-way serial configuration chip EPCQ, and the programming mode is selected as an active serial mode and is used for solidifying a program circuit when the FPGA chip is electrified and started; the input-output circuit comprises a digital input and a digital output, and can be freely designed.
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| CN111175595B (en) * | 2019-10-31 | 2020-11-20 | 北京交通大学 | Method for monitoring residual life of direct current capacitor of three-phase full-control rectification system |
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