CN110783434B - LED chip and preparation method thereof - Google Patents

LED chip and preparation method thereof Download PDF

Info

Publication number
CN110783434B
CN110783434B CN201911125980.7A CN201911125980A CN110783434B CN 110783434 B CN110783434 B CN 110783434B CN 201911125980 A CN201911125980 A CN 201911125980A CN 110783434 B CN110783434 B CN 110783434B
Authority
CN
China
Prior art keywords
layer
type material
nano
material layer
led chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911125980.7A
Other languages
Chinese (zh)
Other versions
CN110783434A (en
Inventor
朱玲
吴懿平
吕卫平
胡俊华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Yuanxin Guanglu Technology Co ltd
Original Assignee
Shenzhen Yuanxin Guanglu Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Yuanxin Guanglu Technology Co ltd filed Critical Shenzhen Yuanxin Guanglu Technology Co ltd
Priority to CN201911125980.7A priority Critical patent/CN110783434B/en
Publication of CN110783434A publication Critical patent/CN110783434A/en
Application granted granted Critical
Publication of CN110783434B publication Critical patent/CN110783434B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/813Bodies having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01Manufacture or treatment
    • H10H20/011Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/811Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures

Landscapes

  • Led Devices (AREA)

Abstract

The invention relates to an LED chip and a preparation method thereof.A first nanorod area and a second nanorod area which are composed of nanorods penetrating through an n-type material layer, a multi-quantum well layer and a p-type material layer in sequence are formed on the LED chip. The LED chip is provided with the first nanorod area and the second nanorod area, the diameter change of the nanorods can change the light emitting wavelength of a multi-quantum well layer in the nanorods by combining experimental data, the diameter of the nanorods in the first nanorod area is larger than that of the nanorods in the second nanorod area, so that the first nanorod area and the second nanorod area can respectively emit light with different wavelengths, and the LED chip can realize colorful display.

Description

LED chip and preparation method thereof
Technical Field
The invention relates to the technical field of display, in particular to an LED chip and a preparation method thereof.
Background
micro-LED is an LED device that can be used for screen display, and realizes illumination and display by emitting light through a single LED chip.
However, due to the property of the LED device emitting monochromatic light, in order to realize a multicolor display, a plurality of LED chips emitting different colors are required to be combined.
That is, a single LED chip cannot realize a multicolor display.
Disclosure of Invention
In view of this, it is necessary to provide an LED chip that can emit two or more kinds of light, thereby realizing a multicolor display.
An LED chip comprises a base layer, a first metal layer, a p-type material layer, a multi-quantum well layer, an n-type material layer and a second metal layer which are sequentially stacked;
and a first nanorod area and a second nanorod area which are formed by nanorods penetrating through the n-type material layer, the multi-quantum well layer and the p-type material layer in sequence are formed on the LED chip, and the diameter of the nanorod in the first nanorod area is larger than that of the nanorod in the second nanorod area.
A preparation method of an LED chip is used for preparing the LED chip and comprises the following steps:
providing an LED wafer, wherein the LED wafer comprises a p-type material layer, a multi-quantum well layer, an n-type material layer and a substrate which are sequentially stacked;
forming a first metal layer on the p-type material layer, and then disposing a base layer on the first metal layer such that the base layer, the first metal layer, and the p-type material layer are sequentially stacked;
removing the substrate, and then carrying out primary flattening treatment on the n-type material layer;
forming a mask layer with a required pattern on the n-type material layer, and then etching to form a first nanorod area and a second nanorod area, wherein the first nanorod area and the second nanorod area are respectively composed of nanorods penetrating through the n-type material layer, the multi-quantum well layer and the p-type material layer in sequence, and the diameter of the nanorods in the first nanorod area is larger than that of the nanorods in the second nanorod area; and
and performing secondary flattening treatment on the n-type material layer to obtain a semi-finished product, and forming a second electrode layer on the n-type material layer to obtain the LED chip.
The LED chip is provided with the first nanorod area and the second nanorod area, the diameter change of the nanorods can change the light emitting wavelength of a multi-quantum well layer in the nanorods by combining experimental data, and the diameters of the nanorods in the first nanorod area and the second nanorod area are larger than those of the nanorods in the second nanorod area, so that the first nanorod area and the second nanorod area can respectively emit light with different wavelengths, and the single LED chip can realize colorful display.
In addition, compared with the traditional LED which emits light with different colors, the LED chip can simultaneously emit more than two kinds of light through the first nano-pillar region and the second nano-pillar region, so that the display resolution and the color rendering index CRI (which can reach 100) of a device adopting the LED chip are obviously superior to those of the traditional device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Wherein:
fig. 1 is a schematic cross-sectional structure diagram of an LED chip according to an embodiment.
Fig. 2 is a process diagram for manufacturing the LED chip shown in fig. 1.
Fig. 3 is a photoluminescence spectrum of a white left region, a first nanopillar region, a second nanopillar region, a third nanopillar region, and a fourth nanopillar region of the LED chip prepared in example 1.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The LED chip according to the embodiment shown in fig. 1 includes a base layer 10, a first metal layer 20, a p-type material layer 30, a multiple quantum well layer 40, an n-type material layer 50, and a second metal layer 60, which are sequentially stacked.
Referring to fig. 1, a first nanopillar region 101 and a second nanopillar region 102 composed of nanopillars sequentially penetrating through the n-type material layer 50, the multiple quantum well layer 40, and the p-type material layer 30 are formed on the LED chip, and the diameter of the nanopillars in the first nanopillar region 101 is greater than that of the nanopillars in the second nanopillar region 102.
Referring to fig. 1, the first nanopillar region 101 may be provided with a plurality of nanopillars spaced apart from each other, or may be provided with only one nanopillar, each of which includes, from top to bottom, an n-type material layer 50, a multiple quantum well layer 40, and a p-type material layer 30.
Likewise, the second nanopillar region 102 may be provided with a plurality of nanopillars spaced apart from each other, or may be provided with only one nanopillar, each of which includes, from top to bottom, the n-type material layer 50, the multiple quantum well layer 40, and the p-type material layer 30.
In combination with experimental data, we found that the diameter of the nanopillar can be changed to change the light emission wavelength of the mqw layer in the nanopillar, and generally, as the diameter of the nanopillar is reduced, the light emission wavelength of the mqw layer in the nanopillar is also reduced.
In addition, compared with the traditional LED which emits light with different colors, the LED chip can simultaneously emit more than two kinds of light through the first nano-pillar region and the second nano-pillar region, so that the display resolution and the color rendering index CRI (which can reach 100) of a device adopting the LED chip are obviously superior to those of the traditional device.
In the LED chip disclosed in the present application, the diameter of the nanopillar in the first nanopillar region 101 is greater than the diameter of the nanopillar in the second nanopillar region 102, so that the first nanopillar region 101 and the second nanopillar region 102 can emit light with different wavelengths respectively, thereby enabling the LED chip to realize colorful display.
Preferably, each of the first nanorod region 101 and the second nanorod region 102 is a triangle or a hexagon (hexagon) formed by a plurality of nanorods. By adopting a triangular or hexagonal structure, the adjacent regions can be closely arranged, and the active area of the multiple quantum well layer 40 can be saved to the maximum extent.
In other embodiments, the first nanopillar region 101 and the second nanopillar region 102 may have other shapes such as a circle, a quadrangle, and a pentagon formed by a plurality of nanopillars.
The first nanopillar region 101 described in the present application has a hexagonal shape or the like, and means a shape of the first nanopillar region 101 in a plan view.
Preferably, the diameter of the nanopillar in the first nanopillar region 101 is 100nm to 1500nm, and the diameter of the nanopillar in the second nanopillar region 102 is 10nm to 800 nm.
Specifically, a white space may be further disposed on the LED chip, and no nano-pillars are formed in the white space, so that the white space may emit light of a third color.
The white light leaving area, the first nano-column area and the second nano-column area respectively emit light of three different colors, and the LED chip can emit light of three colors of red, yellow and blue after proper adjustment, so that three primary colors of light are formed, and the LED chip can realize full-color light emission.
Compared with the traditional full-color micro-display scheme, the LED chip has the following advantages: 1) the nano-pillars can relieve stress, improve light extraction efficiency and meet the requirement of high resolution of small pixels of the LED chip; 2) the LED color-changing material realizes full color on a single LED chip, does not depend on an external luminescent material or an optical component, has stable and uniform color and small volume, and is easy to integrate; 3) the large-scale micro-nano processing with low cost can be carried out by adopting nano-imprinting, so that the full-color LED micro display array scheme has the potential of practical application.
Preferably, the emission wavelength of the multiple quantum well layer is 560nm to 770 nm. Because the nano-pillars can shorten the light-emitting wavelength of the multi-quantum well, the multi-quantum well (red light, orange light and yellow light) with longer light-emitting wavelength is generally selected, so that the nano-pillars have better adjusting space.
In this embodiment, the p-type material layer 30 is a p-GaN layer, the n-type material layer 50 is an n-GaN layer, and the multi-quantum well layer 40 is a multi-quantum well layer (preferably, stacked six times) having InGaN/GaN as a stacked unit.
In other embodiments, other types of multiple quantum wells may be employed.
When the MQW 40 is a MQW having InGaN/GaN as a laminated unit, the number of times of lamination may be 3 to 20.
In the present application, the only standard for selecting the multiple quantum well layer 40 is the light emission wavelength thereof, and the parameters of the multiple quantum well layer 40, such as specific materials, doping ratios, stacking units, and stacking times, can be randomly matched, and only light with the light emission wavelength required by people needs to be emitted.
In this embodiment, the base layer 10 is a silica base layer, the first metal layer 20 is Ni/Au or Ni/Ag, and the material of the second metal layer 60 is Ti/Al. Here, "/" represents the meaning of lamination.
With reference to fig. 2, the present application further discloses a method for manufacturing the LED chip, which includes the following steps:
and S10, providing an LED wafer.
Referring to fig. 2a, the LED die includes a p-type material layer 30, a multiple quantum well layer 40, an n-type material layer 50, and a substrate 200, which are sequentially stacked.
The LED dies are usually purchased directly, and only the LED dies meeting the requirement of the light emission wavelength need to be purchased.
S20, the first metal layer 20 is formed on the p-type material layer 30, and then the base layer 10 is disposed on the first metal layer 20, such that the base layer 10, the first metal layer, and the p-type material layer 30 are sequentially stacked.
Referring to fig. 2b and 2c, the first metal layer 20 is typically formed by electron beam evaporation.
The first metal layer 20 is generally made of a metal material selected to have a high reflectivity so that the first metal layer 20 functions as a reflective layer.
The operation of disposing the base layer 10 on the first metal layer 20 may be: SiO by silica gel2The substrate (base layer 10) and the first metal layer 20 are bonded together.
S30, the substrate 200 is removed, and then the first planarization process is performed on the n-type material layer 50.
In this embodiment, the substrate 200 is a sapphire substrate. Removing the substrate 200 operates as: the substrate 200 is removed by a laser lift-off technique (LLO) in which a laser beam used in the laser lift-off technique is a deep ultraviolet laser beam having a wavelength of 266 nm.
The removal of the substrate 200 by laser lift-off (LLO) can avoid crosstalk effects and improve the heat dissipation capability of the LED chip and the current density of each pixel unit.
The laser beam adopted in the laser lift-off technology is a deep ultraviolet laser beam with the wavelength of 266nm to penetrate through the sapphire substrate and be strongly absorbed by the n-GaN layer, so that the interface between the n-GaN layer and the sapphire substrate is ablated.
In other embodiments, the substrate 200 may also be a silicon substrate, and the removing the substrate 200 is performed by: the substrate 200 is removed by wet etching.
In this embodiment, the first leveling process is performed on the n-type material layer by: and thinning the n-type material layer 50 by adopting dry etching, and enabling the surface roughness of the thinned n-type material layer 50 to be less than 10 nm.
After LLO removal of the substrate 200, the n-GaN interface becomes very rough, but excellent surface flatness is necessary for the nanoimprint process. By researching the influence of ICP parameters on the surface Roughness (RMS) and adopting dry etching to thin the n-type material layer, the surface Roughness (RMS) can be reduced to 10 nm. In addition, in order to further restore the smoothness of the etched surface to a level close to that of epitaxial growth, further reduction of RMS using chemical treatment and annealing treatment is required.
S40, a mask layer 300 having a desired pattern is formed on the n-type material layer 50, followed by etching to form the first nanopillar region 101 and the second nanopillar region 102.
Referring to fig. 2f, 2g and 2h, the first and second nanopillar regions 101 and 102 are composed of nanopillars sequentially penetrating the n-type material layer 50, the multiple quantum well layer 40 and the p-type material layer 30, and the diameter of the nanopillars in the first nanopillar region 101 is greater than that of the nanopillars in the second nanopillar region 102.
In this embodiment, the mask layer 300 is a photoresist layer 300.
In this embodiment, the operation of forming a mask layer having a desired pattern on the n-type material layer 50 after the first planarization process is: a photoresist layer 300 is formed by coating a photoresist on the n-type material layer 50, and then a desired pattern is transferred onto the photoresist layer 300 using a nano-imprinting method.
In other embodiments, the operation of forming a mask layer with a desired pattern on the n-type material layer 50 after the first planarization process is further performed by: a Ni etch mask is provided on the n-type material layer 50, followed by SiO deposition on the Ni etch mask2Layer for transferring a desired pattern to SiO by nanoimprint2Layer, followed by etching to remove the desired pattern from SiO2The layer is transferred to a Ni etch mask to obtain sidewall-vertical nanopillars by high etch selectivity between the Ni etch mask and the n-type material layer. The scheme can ensure that the etched nano-pillars are vertical and have smooth profiles.
S50, performing a second planarization process on the n-type material layer 50 to obtain a semi-finished product, and forming a second electrode layer 60 on the n-type material layer 50 to obtain the desired LED chip.
Referring to fig. 2i, the second electrode layer 60 is generally formed by electron beam evaporation.
Preferably, the second planarization process is performed on the n-type material layer 50 by: and filling a dielectric material in the first nano-pillar region 101 and the second nano-pillar region 102, and performing thinning treatment to expose the n-type material layer. The dielectric material may be a polyimide glass material. The filling dielectric material may fill the gap between the first nano-pillar region 101 and the second nano-pillar region 102, facilitating the preparation of the second electrode layer 60.
Preferably, the operation of forming the second electrode layer 60 on the semi-finished n-type material layer 50 is: after the semi-finished product is mounted obliquely, a second electrode layer 60 is formed on the n-type material layer 50 by evaporation.
The semi-finished product is installed obliquely, so that the metal electron beam can fill the gap obliquely in the evaporation process.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Example 1
The InGaN/GaNLED wafer with the luminous wavelength of 585nm (yellow light) is provided, and comprises a p-GaN layer, a multi-quantum well layer, an n-GaN layer and a sapphire substrate which are sequentially stacked, wherein the multi-quantum well layer is provided with six InGaN/GaN multi-quantum well layers.
A Ni layer (5nm)/Au layer (5nm) was vapor-deposited on p-GaN, followed by deposition of SiO through a silica gel2The substrate and the Ag layer are bonded together.
The substrate 200 is removed by laser lift-off (LLO) technology, and then the n-GaN is thinned by dry etching, so that the surface roughness of the thinned n-GaN is 10 nm.
And coating photoresist on the n-GaN to form a photoresist layer, transferring a required pattern to the photoresist layer by adopting a nano-imprinting method, and etching to form a blank area, a first nano-pillar area, a second nano-pillar area, a third nano-pillar area and a fourth nano-pillar area. The left white area is not provided with the nano-columns, the diameter of the nano-columns in the first nano-column area is 1000nm, the diameter of the nano-columns in the second nano-column area is 500nm, the diameter of the nano-columns in the third nano-column area is 100nm, and the diameter of the nano-columns in the fourth nano-column area is 80 nm.
And performing secondary flattening treatment on the n-GaN by adopting dry etching again, and then forming a Ti layer (50nm)/Al layer (150nm) on the n-GaN to obtain the required LED chip.
Example 2
Photoluminescence measurement was performed on the LED chip prepared in example 1, and photoluminescence spectrograms of a margin region, a first nanopillar region, a second nanopillar region, a third nanopillar region, and a fourth nanopillar region of the LED chip shown in fig. 3 were obtained.
As can be seen from fig. 3, the emission wavelength of the multiple quantum well in the form of the nanopillar is decreased, and as the size of the nanopillar is decreased, the emission wavelength of the multiple quantum well in the nanopillar is decreased.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1.一种LED芯片,其特征在于,包括依次层叠的基层、第一金属层、p型材料层、多量子阱层、n型材料层以及第二金属层;1. An LED chip, characterized in that it comprises a base layer, a first metal layer, a p-type material layer, a multi-quantum well layer, an n-type material layer and a second metal layer stacked in sequence; 所述LED芯片上形成有由依次贯穿所述n型材料层、所述多量子阱层和所述p型材料层的纳米柱组成的第一纳米柱区域和第二纳米柱区域,所述第一纳米柱区域内的纳米柱的直径大于所述第二纳米柱区域内的纳米柱的直径;A first nano-column region and a second nano-column region are formed on the LED chip, which are composed of nano-columns penetrating the n-type material layer, the multiple quantum well layer and the p-type material layer in sequence. The diameter of the nano-pillars in one nano-pillar region is larger than the diameter of the nano-pillars in the second nano-pillar region; 所述LED芯片上设有留白区域,所述留白区域内未形成纳米柱;The LED chip is provided with a blank area, and no nano-pillars are formed in the blank area; 所述第一纳米柱区域和所述第二纳米柱区域均为三角形或六角形。Both the first nano-pillar region and the second nano-pillar region are triangular or hexagonal. 2.根据权利要求1所述的LED芯片,其特征在于,2. The LED chip according to claim 1, characterized in that, 所述第一纳米柱区域内的纳米柱的直径为100nm~1500nm,所述第二纳米柱区域内的纳米柱的直径为10nm~800nm。The diameter of the nano-columns in the first nano-column region is 100 nm-1500 nm, and the diameter of the nano-columns in the second nano-column region is 10 nm-800 nm. 3.根据权利要求1或2所述的LED芯片,其特征在于,所述多量子阱层的发光波长为560nm~770nm。3 . The LED chip according to claim 1 , wherein the light emission wavelength of the multiple quantum well layer is 560 nm˜770 nm. 4 . 4.根据权利要求3所述的LED芯片,其特征在于,所述p型材料层为p-GaN层,所述n型材料层为n-GaN层,所述多量子阱层为以InGaN/GaN为层叠单元的多量子阱层;4 . The LED chip according to claim 3 , wherein the p-type material layer is a p-GaN layer, the n-type material layer is an n-GaN layer, and the multiple quantum well layer is made of InGaN/ GaN is the multiple quantum well layer of the stacked unit; 所述基层为二氧化硅基层,所述第一金属层为Ni/Au或Ni/Ag,所述第二金属层为Ti/Al。The base layer is a silicon dioxide base layer, the first metal layer is Ni/Au or Ni/Ag, and the second metal layer is Ti/Al. 5.一种LED芯片的制备方法,其特征在于,用于制备如权利要求1~4中任一项所述的LED芯片,所述LED芯片的制备方法包括如下步骤:5. A method for preparing an LED chip, characterized in that, for preparing the LED chip according to any one of claims 1 to 4, the method for preparing the LED chip comprises the following steps: 提供LED晶元,其中,所述LED晶元包括依次层叠的p型材料层、多量子阱层、n型材料层和衬底;An LED wafer is provided, wherein the LED wafer includes a p-type material layer, a multiple quantum well layer, an n-type material layer and a substrate stacked in sequence; 在所述p型材料层上形成第一金属层,接着在所述第一金属层上设置基层,从而使得所述基层、第一金属层和所述p型材料层依次层叠;forming a first metal layer on the p-type material layer, and then disposing a base layer on the first metal layer, so that the base layer, the first metal layer and the p-type material layer are sequentially stacked; 去除所述衬底,接着对所述n型材料层进行第一次平整化处理;removing the substrate, and then performing a first planarization process on the n-type material layer; 在所述n型材料层上形成具有所需的图案的掩膜层,接着刻蚀形成第一纳米柱区域、第二纳米柱区域和留白区域,其中,所述第一纳米柱区域和所述第二纳米柱区域均由依次贯穿所述n型材料层、所述多量子阱层和所述p型材料层的纳米柱组成,所述第一纳米柱区域内的纳米柱的直径大于所述第二纳米柱区域内的纳米柱的直径,所述留白区域内没有纳米柱;以及A mask layer with a desired pattern is formed on the n-type material layer, followed by etching to form a first nano-column region, a second nano-column region and a blank region, wherein the first nano-column region and all The second nano-column region is composed of nano-columns that run through the n-type material layer, the multiple quantum well layer and the p-type material layer in sequence, and the diameter of the nano-columns in the first nano-column region is larger than that of the first nano-column region. the diameter of the nano-pillars in the second nano-pillar area, and there are no nano-pillars in the blank area; and 对所述n型材料层进行第二次平整化处理后,得到半成品,在所述n型材料层上形成第二电极层,从而得到所述LED芯片;After the second planarization treatment is performed on the n-type material layer, a semi-finished product is obtained, and a second electrode layer is formed on the n-type material layer, thereby obtaining the LED chip; 所述第一纳米柱区域和所述第二纳米柱区域均为三角形或六角形。Both the first nano-pillar region and the second nano-pillar region are triangular or hexagonal. 6.根据权利要求5所述的LED芯片的制备方法,其特征在于,所述衬底为蓝宝石衬底,所述去除所述衬底操作为:通过激光剥离技术去除所述衬底,其中,所述激光剥离技术中采用的激光束为波长为266nm的深紫外激光束;6 . The method for manufacturing an LED chip according to claim 5 , wherein the substrate is a sapphire substrate, and the operation for removing the substrate is: removing the substrate by a laser lift-off technique, wherein: 7 . The laser beam used in the laser lift-off technology is a deep ultraviolet laser beam with a wavelength of 266 nm; 或者,所述衬底为硅衬底,所述去除所述衬底操作为:通过湿法刻蚀去除所述衬底。Alternatively, the substrate is a silicon substrate, and the operation of removing the substrate is: removing the substrate by wet etching. 7.根据权利要求5所述的LED芯片的制备方法,其特征在于,所述对所述n型材料层进行第一次平整化处理的操作为:采用干法刻蚀对所述n型材料层进行减薄处理,并且使得减薄后的所述n型材料层的表面粗糙度小于10nm。7 . The method for manufacturing an LED chip according to claim 5 , wherein the operation of performing the first planarization treatment on the n-type material layer is: dry etching the n-type material layer. 8 . The layer is thinned, and the surface roughness of the thinned n-type material layer is less than 10 nm. 8.根据权利要求5所述的LED芯片的制备方法,其特征在于,所述在所述n型材料层上形成具有所需的图案的掩膜层的操作为:在所述n型材料层上涂覆光刻胶形成光刻胶层,然后采用纳米压印的方法将所需的图案转移到所述光刻胶层上,所述光刻胶层即为所述掩膜层;8 . The method for manufacturing an LED chip according to claim 5 , wherein the operation of forming a mask layer with a desired pattern on the n-type material layer is: forming a mask layer on the n-type material layer. 9 . Coating photoresist on it to form a photoresist layer, and then using the method of nano-imprinting to transfer the desired pattern to the photoresist layer, and the photoresist layer is the mask layer; 或者,所述在所述n型材料层上形成具有所需的图案的掩膜层的操作为:在所述n型材料层上设置Ni蚀刻掩模,接着在所述Ni蚀刻掩模上设置SiO2层,通过纳米压印将所需的图案转化到SiO2层,接着蚀刻从而将所需的图案从所述SiO2层转印到所述Ni蚀刻掩模上,通过所述Ni蚀刻掩模与所述n型材料层之间的高刻蚀选择比来获得侧壁垂直的纳米柱。Alternatively, the operation of forming a mask layer with a desired pattern on the n-type material layer is: disposing a Ni etching mask on the n-type material layer, and then disposing an Ni etching mask on the Ni etching mask SiO 2 layer, the desired pattern is transferred to the SiO 2 layer by nanoimprinting, followed by etching to transfer the desired pattern from the SiO 2 layer onto the Ni etch mask, through which the Ni etch mask is A high etch selectivity ratio between the die and the n-type material layer is used to obtain nanopillars with vertical sidewalls. 9.根据权利要求5所述的LED芯片的制备方法,其特征在于,所述对所述n型材料层进行第二次平整化处理的操作为:在所述第一纳米柱区域和所述第二纳米柱区域填充介质材料,接着进行减薄处理,使得所述n型材料层暴露出来。9 . The manufacturing method of an LED chip according to claim 5 , wherein the operation of performing the second planarization treatment on the n-type material layer is: in the first nanopillar region and the The second nanopillar region is filled with a dielectric material, followed by a thinning process to expose the n-type material layer. 10.根据权利要求5所述的LED芯片的制备方法,其特征在于,所述在所述n型材料层上形成第二电极层的操作为:将所述半成品倾斜安装后,在所述n型材料层上蒸镀形成所述第二电极层。10 . The method for manufacturing an LED chip according to claim 5 , wherein the operation of forming the second electrode layer on the n-type material layer is: after the semi-finished product is installed obliquely, the n-type material layer is formed on the n-type material layer. The second electrode layer is formed by vapor deposition on the type material layer.
CN201911125980.7A 2019-11-18 2019-11-18 LED chip and preparation method thereof Active CN110783434B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911125980.7A CN110783434B (en) 2019-11-18 2019-11-18 LED chip and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911125980.7A CN110783434B (en) 2019-11-18 2019-11-18 LED chip and preparation method thereof

Publications (2)

Publication Number Publication Date
CN110783434A CN110783434A (en) 2020-02-11
CN110783434B true CN110783434B (en) 2021-06-11

Family

ID=69391479

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911125980.7A Active CN110783434B (en) 2019-11-18 2019-11-18 LED chip and preparation method thereof

Country Status (1)

Country Link
CN (1) CN110783434B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112216711B (en) * 2020-09-15 2023-12-22 深圳远芯光路科技有限公司 GaN light sensing biological sensing chip and preparation method and application thereof
CN112563302B (en) * 2021-03-01 2021-05-11 南京邮电大学 Micro-nano composite structure photonic integrated chip and preparation method thereof
CN113937194B (en) * 2021-09-29 2022-09-09 深圳市思坦科技有限公司 Bonding process of nano-pillar LED chip, LED chip and display device
CN119008821A (en) * 2023-05-22 2024-11-22 中国科学院苏州纳米技术与纳米仿生研究所 Micro-LED chip and preparation method and application thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102403428A (en) * 2010-09-14 2012-04-04 三星Led株式会社 Group III nitride nanorod light emitting device and method of manufacturing thereof
CN104396028A (en) * 2012-05-24 2015-03-04 香港大学 White nano-LEDs that don't require color conversion
CN104868023A (en) * 2015-05-11 2015-08-26 南京大学 III-nitride semiconductor/quantum dot hybrid white light LED device and preparing method thereof
CN205666251U (en) * 2016-06-06 2016-10-26 安徽三安光电有限公司 Spontaneous white light emitting diode
CN106784194A (en) * 2017-01-06 2017-05-31 上海应用技术大学 A kind of method for preparing single-chip ultra wide band white light LEDs
CN108598227A (en) * 2018-04-25 2018-09-28 黎明职业大学 A kind of semiconductor white light emitting diode

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201346992A (en) * 2012-04-23 2013-11-16 Nanocrystal Asia Inc Method for manufacturing low defect density flat substrate
CN104600089B (en) * 2013-10-31 2017-12-15 展晶科技(深圳)有限公司 Photoelectricity module and its manufacture method
US10708995B2 (en) * 2017-05-12 2020-07-07 The Regents Of The University Of Michigan Color mixing monolithically integrated light-emitting diode pixels

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102403428A (en) * 2010-09-14 2012-04-04 三星Led株式会社 Group III nitride nanorod light emitting device and method of manufacturing thereof
CN104396028A (en) * 2012-05-24 2015-03-04 香港大学 White nano-LEDs that don't require color conversion
CN104868023A (en) * 2015-05-11 2015-08-26 南京大学 III-nitride semiconductor/quantum dot hybrid white light LED device and preparing method thereof
CN205666251U (en) * 2016-06-06 2016-10-26 安徽三安光电有限公司 Spontaneous white light emitting diode
CN106784194A (en) * 2017-01-06 2017-05-31 上海应用技术大学 A kind of method for preparing single-chip ultra wide band white light LEDs
CN108598227A (en) * 2018-04-25 2018-09-28 黎明职业大学 A kind of semiconductor white light emitting diode

Also Published As

Publication number Publication date
CN110783434A (en) 2020-02-11

Similar Documents

Publication Publication Date Title
CN110783434B (en) LED chip and preparation method thereof
CN113498550B (en) Pixelated LED chip and chip array device, and method of manufacture
CN108281456B (en) Micro-LED device structure and manufacturing method
US20230120107A1 (en) Method of producing optoelectronic semiconductor components and an optoelectronic semiconductor component
JP2019516251A (en) Monolithic multicolor direct view display comprising LEDs of different colors and method of manufacturing the same
CN106920790A (en) A kind of full-color micro-display device and preparation method thereof
CN104396028A (en) White nano-LEDs that don't require color conversion
KR20190099050A (en) Process for manufacturing optoelectronic device comprising photoluminescent pads of photoresist
CN110277379B (en) Light emitting element and method for manufacturing the same
CN108389941A (en) It is aobvious to refer to adjustable unstressed configuration powder Single chip white light LED component and preparation method thereof
US11901480B2 (en) Method of manufacturing a light-emitting device
CN114497325B (en) Full-color Micro-LED display chip embedded with quantum dots and preparation method thereof
CN111462651A (en) Light-emitting display substrate for surface mount micro LED fluid assembly and preparation method
CN110447111B (en) Strain-induced nanostructures for spectral red-shifting of light emitting devices
CN110808315A (en) Method for increasing GaN Micro-LED color conversion efficiency
US11876154B2 (en) Light emitting diode device and method for manufacturing the same
CN109417119A (en) The quantum photonic imager and its manufacturing method of nano-phosphor conversion
TWI484663B (en) Semiconductor light emitting element and manufacturing method thereof
CN111477726A (en) Planar surface mount micro-LED for fluid assembly and method of making the same
CN113270441B (en) LED chip structure and its preparation method, display module and electronic equipment
KR100859282B1 (en) Multi-wavelength Light Emitting Diode and Manufacturing Method Thereof
CN104716242A (en) Epitaxial substrate, method for manufacturing same, and light emitting diode
CN108400211A (en) A kind of light emitting diode with multi-wavelength
KR100696445B1 (en) Light emitting diode display device and manufacturing method thereof
JP2023519987A (en) monolithic LED pixel

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant