CN110783301A - 具有电隔离信号引线的引线上芯片半导体器件封装 - Google Patents

具有电隔离信号引线的引线上芯片半导体器件封装 Download PDF

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CN110783301A
CN110783301A CN201910622243.1A CN201910622243A CN110783301A CN 110783301 A CN110783301 A CN 110783301A CN 201910622243 A CN201910622243 A CN 201910622243A CN 110783301 A CN110783301 A CN 110783301A
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signal leads
lead
signal
chip
device package
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良仁勇
王松伟
刘豪杰
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

本发明题为“具有电隔离信号引线的引线上芯片半导体器件封装”。在一般方面中,一种引线上芯片半导体器件封装可以包括具有多个信号引线的引线框。多个信号引线可以包括至少两个信号引线,该至少两个信号引线的每个信号引线具有带第一表面面积的第一面和与第一面相对的带第二表面面积的第二面,至少两个信号引线的第二面暴露在引线上芯片器件封装的表面上。多个信号引线还可以包括至少一个信号引线,该至少一个信号引线具有带第三表面面积的第一面和与至少一个信号引线的第一面相对的带第二表面面积的第二面,至少一个信号引线的第二面暴露在引线上芯片半导体器件封装的表面上。

Description

具有电隔离信号引线的引线上芯片半导体器件封装
技术领域
本说明书涉及半导体器件封装。更具体地,本说明书涉及引线上芯片半导体器件封装。
背景技术
半导体器件(半导体管芯)可以在各种半导体器件封装组件(封装组件)中实现。在一些封装组件中,可以包括隔离管芯附着焊盘(DAP),并且半导体管芯可以与封装组件中的DAP耦接(例如,其中DAP与封装组件的信号引线电隔离)。由于DAP的电隔离,这种实施方式允许半导体管芯与封装组件的信号引线电隔离(例如,在没有从信号引线到DAP的单独电连接的情况下)。
在一些实施方式中,半导体器件封装组件可以排除DAP,并且在这种封装组件中实现的半导体管芯可以部分地设置在封装组件的信号引线的表面上。这种组件可以被称为引线上芯片半导体封装组件(COL组件)。然而,COL组件可能有某些缺点。例如,半导体管芯的电气故障(例如,当针对性能规格进行测试时)可能发生在这种组件中。例如,在COL组件的信号引线(例如,高压信号引线)和包括在组件中的对应半导体管芯之间可能会发生过度漏电(例如,超过指定限值),其中半导体管芯与组件的信号引线耦接(在其上附接、安装、固定等)。
发明内容
在一般方面,引线上芯片(COL)半导体器件封装(封装)可以包括具有前侧表面和后侧表面的半导体管芯。后侧表面可以与前侧表面相对。COL封装还可以包括具有多个信号引线的引线框。多个信号引线可以包括至少两个信号引线,至少两个信号引线的每个信号引线具有带第一表面面积的第一面和与第一面相对的带第二表面面积的第二面,该至少两个信号引线的第二面暴露在引线上芯片器件封装的表面上。多个信号引线还可以包括至少一个信号引线,该至少一个信号引线具有带第三表面面积的第一面和与至少一个信号引线的第一面相对的带第二表面面积的第二面,至少一个信号引线的第二面暴露在引线上芯片半导体器件封装的表面上。半导体管芯的后侧表面可以与至少两个信号引线的第一面耦接。至少一个信号引线的第一面可以从半导体管芯的后侧表面横向地设置。
在另一个一般方面,引线上芯片(COL)半导体器件封装(封装)可以包括预模制引线框,该引线框包括多个信号引线和模塑料。多个信号引线可以包括至少两个信号引线,至少两个信号引线的每个信号引线具有带第一表面面积的第一面和与第一面相对的带第二表面面积的第二面,该至少两个信号引线的第一面暴露在预模制引线框的第一表面上,并且所述两个信号引线的第二面暴露在与预模制引线框的第一表面相对的预模制引线框的第二表面上。多个信号引线还可以包括至少一个信号引线,该至少一个信号引线具有带第三表面面积的第一面和与至少一个信号引线的第一面相对的带第二表面面积的第二面,至少一个信号引线的第一面暴露在预模制引线框的第一表面上,并且至少一个信号引线的第二面暴露在预模制引线框的第二表面上。COL封装还可以包括具有前侧表面和后侧表面的半导体管芯。后侧表面可以与前侧表面相对。半导体管芯的后侧表面可以与预模制引线框的第一表面上的模塑料和至少两个信号引线的第一面耦接。至少一个信号引线的第一面可以从半导体管芯的后侧表面横向地设置。
在另一个一般方面,引线上芯片(COL)半导体器件封装(封装)可以包括具有前侧表面和后侧表面的半导体管芯。后侧表面与前侧表面相对。COL封装还可以包括具有多个信号引线的引线框。多个信号引线的第一子集可以沿着COL封装的第一边缘布置。多个信号引线的第二子集可以沿着COL封装的第二边缘布置。第二边缘可以与第一边缘相对。多个信号引线的第一子集的第一信号引线可以与多个信号引线的第二子集的第一信号引线间隔第一距离。多个信号引线的第二子集的第一信号引线可以在COL封装中分别布置成与多个信号引线的第一子集的第一信号引线直接相对。多个信号引线的第一子集的第二信号引线可以与多个信号引线的第二子集的第二信号引线间隔第二距离。多个信号引线的第二子集的第二信号引线可以在引线上芯片半导体器件封装中分别布置成与多个信号引线的第一子集的第二信号引线直接相对。第二距离可以大于第一距离。半导体管芯的后侧表面可以与多个信号引线的第一子集的第一信号引线、多个信号引线的第二子集的第一信号引线和多个信号引线的第一子集的第二信号引线耦接。COL封装还可以包括模塑料,该模塑料可以设置在半导体管芯的后侧表面和多个信号引线的第二子集的第二信号引线之间。
附图说明
图1A是从第一侧观察的用于引线上芯片(COL)半导体器件封装的引线框的平面图。
图1B是从第二侧观察的图1A的引线框的平面图,第二侧与第一侧相对。
图2是用于COL半导体器件封装的预模制引线框的等轴视图,诸如包括图1A和1B的引线框。
图3是包括图1A和1B的引线框或图2的预模制引线框的COL半导体器件封装的等轴视图。
图4是图3的COL半导体器件封装的剖视图。
在未必按比例绘制的附图中,相同的参考符号可指示不同视图中的相同和/或相似的部件(元件,结构等)。附图大体上以举例而非限制的方式示出了本公开中所讨论的各种实施方式。在一个附图中示出的参考符号对于相关视图中的相同和/或相似元件可以不重复。在多个附图中重复的参考符号可能不针对这些附图中的每一个具体地讨论,而是提供用于相关视图之间的上下文。另外,并非附图中的所有相同元件都在示出元件的多个实例时用参考符号具体引用。
具体实施方式
图1A是从第一侧观察的用于引线上芯片(COL)半导体器件封装(封装)的引线框100的平面图。图1B是从第二侧观察的图1A的引线框100的平面图,第二侧与第一侧相对。也就是说,如图1B所示,引线框100被示出为从图1A所示的视图倒置。出于本公开的目的,图1A所示的引线框100的视图将被称为顶侧视图,而图1B所示的引线框100的视图将被称为后侧视图。
如图1A和图1B所示,引线框100可以包括外框110和信号引线120a、120b、120c、120d、120e、120f、120g和130。外框110可以与信号引线120a-120g和130一起形成,作为用于生产引线框100的引线框生产工艺的一部分。这种生产工艺可以包括用于形成引线框100的许多操作,诸如由金属(例如,铜、铝、金属合金等)片形成。这种操作可以包括轧制、冲压、化学蚀刻等。外框110可以被配置为在半导体器件组装过程期间将信号引线120a-120g和130保持在位,外框110在组装过程中的适当点被移除,以便将信号引线120a-120g和130彼此分离(物理和电分离)(例如,将COL封装从外框110分离)。在一些实施方式中,引线框100可以包括在引线框的条或矩阵中,由此可以生产多个半导体器件组件(COL封装)。
如图1A和图1B所示,信号引线120a-120g具有第一配置,而信号引线130具有第二配置。如本文所述,引线框实施方式,诸如引线框100,可以克服当前COL封装引线框的缺点。例如,在一些实施方式中,信号引线130(或其他类似配置的信号引线)可以防止对应COL封装(例如,包括诸如引线框100的引线框的COL封装)中的半导体管芯的电气(例如,漏电)故障。
虽然如图1A和图1B所示的引线框100包括具有信号引线130的配置的一个信号引线,但是引线框100的布置是通过示例给出的。在一些实施方式中,用于COL封装的引线框可以包括具有信号引线130的配置的多个信号引线(或者类似配置的信号引线)。此外,在一些实施方式中,用于COL封装的引线框可以具有信号引线的其他布置,该布置具有信号引线120a-120和130的配置(或类似配置)。例如,用于给定COL封装的引线框中包括的每种配置(例如,信号引线120a-120g的配置,或者信号引线130的配置)的信号引线的数量,以及这些信号引线在对应COL封装中的组织将取决于具体的实施方式,诸如在COL封装中实现的对应半导体管芯的布置。
如图1A所示,对于引线框100,信号引线120a-120g各自在引线框100的顶侧具有带第一表面面积(surfacearea)的第一面,分别是面122a、122b、122c、122d、122e、122f和122g(例如,如图1A所示)。在一些实施方式中,在对应的COL封装中,半导体管芯可以安装在信号引线120a-120g的面122a-122g上,诸如在图2所示的实施方式中。
如图1B所示,与引线框100的后侧上的第一面122a-122g相对,信号引线120a-120g各自具有带第二表面面积的第二面,分别是面124a、124b、124c、124d、124e、124f和124g。在一些实施方式中,诸如本文所述的那些实施方式中,信号引线120a-120g的第二面124a-124g可以暴露在对应COL封装的表面上,例如作为到COL封装中包括的半导体管芯的电触点。在一些实施方式中,第二表面面积(例如,面124a-124g的表面面积)可以小于第一表面面积(例如,面122a-122g的表面面积)。
如图1A进一步所示,对于引线框100,信号引线130可以在引线框100的顶侧具有第一面132,第一面132具有第三表面面积。如图1B所示,与引线框100的后侧上的第一面132相对,信号引线130具有第二面134,该第二面具有第二表面面积(例如,信号引线120a-122g的面124a-124g的表面面积)。在一些实施方式中,诸如本文所述的那些实施方式中,信号引线130的第二面134可以暴露在COL封装的与面124a-124g相同的表面上(例如,作为到COL封装中包括的半导体管芯的另一电触点,诸如用于50V或更高的高压信号)。在一些实施方式中,第三表面面积(例如,面134的表面面积)可以小于第一表面面积(例如,面122a-122g的表面面积),并且小于第二表面面积(例如,面124a-124g的表面面积)。
图2是可以用于实现COL半导体器件封装组件(COL封装)的预模制引线框200的等轴视图。如图2所示,预模制引线框200可以形成为包括图1A和图1B的引线框100。因此,在图2中,来自图1A和图1B的类似附图标记被用于参考预模制引线框200中的引线框100的元件。
如图2所示,在一些实施方式中,引线框100可以部分地封装在模塑料240中,诸如环氧树脂模塑料。如图2所示,信号引线120a-120g的面122a-122g和132可以通过模塑料240的第一表面(例如,图2中面向上的表面)(与其共面等)暴露。虽然在图2中没有具体示出,但是信号引线120a-120g和130的面124a-124g和134可以通过模塑料240的第二表面(例如,预模制引线框200的面向下的表面,诸如图4中针对信号引线120c和130所示)(与其共面等)类似地暴露。
如上所述,面124a-124g和134(暴露在预模制引线框200的第二表面上)可以用作到包括在对应COL封装中的半导体管芯的电触点(例如,在引线接合被用于将半导体管芯的接合焊盘与信号引线120a-120g和130电连接之后,诸如图3所示)。在一些实施方式中,模塑料240可以在预模制引线框200的第一表面和/或第二表面上机械研磨,以通过预模制引线框200的第一表面(例如,图2中面向上的表面)上的模塑料240暴露面122a-122g和132,和/或暴露预模制引线框200的第二表面(例如,图2中面向下的不可见表面)上的面124a-124g和134。
如图2所示,包括信号引线120a-120d的引线框100的多个信号引线的第一子集可以沿着预模制引线框200的第一边缘123(以及包括预模制引线框200的COL封装的对应第一边缘)布置。如图2中进一步所示,包括信号引线120e-120g和130的多个信号引线的第二子集可以沿着预模制引线框200的第二边缘125(以及包括预模制引线框200的COL封装的对应第二边缘)布置。如图2所示,第二边缘125可以与第一边缘123相对。
如图2所示,根据预模制引线框200的信号引线(例如,引线框100的信号引线)的特定配置,沿着第一边缘123布置的信号引线与沿着第二边缘125相对(直接相对)的相应信号引线之间的相应间隔可以变化,从信号引线到预模制引线框200的中心线201的相应距离也可以变化。例如,如图2可见,信号引线120d(信号引线120d的面122d)在图2所示的预模制引线框200的表面上与信号引线120g(信号引线120g的面122g)间隔开距离D1,信号引线120d和120g的面122d和122g中的每一个都与中心线201相距相同的距离,信号引线120d和120g在预模制引线框200中彼此相对(彼此直接相对)。同样如图2所示,信号引线120c(信号引线120c的面122c)可以与图2所示的预模制引线框200的表面上的信号引线130(信号引线130的面132)间隔开距离D2,其中D2大于D1,信号引线120c和130在预模制引线框200中彼此相对(彼此直接相对)。此外,如图2所示,信号引线120c的面122c比信号引线130的面132更靠近中心线201。
图3是包括图1A和图1B的引线框100或图2的预模制引线框200的COL半导体器件封装300的等轴视图。在图3中,器件300被示出为X光视图,其中出于说明的目的,在物理器件实施方式中不可见的器件300的内部元件被示出在图3中的适当位置。与图2一样,来自图1A和图1B的类似附图标记被用于参考器件300中的引线框100(或预模制引线框200的引线框100)的元件。
如图3所示,器件300包括引线框100(或预模制引线框200)的信号引线120a-120g和130、模塑料340、半导体管芯350、介电粘合剂360和引线接合370。图3还示出了剖面线4-4,表示对应于下面讨论的图4中所示器件300的剖视图的剖面线。
在图3的器件300中,半导体管芯350可以具有前侧表面(例如,面向上)和后侧表面(例如,面向下),其中后侧表面与前侧表面相对。如图3所示,半导体管芯350的后侧表面可以与信号引线120a-120d(例如,与信号引线120a-120g的面122a-122g)耦接(例如,通过介电粘合剂360)。同样如图3所示,信号引线130(例如,信号引线103的面134)可以从半导体管芯350的后侧表面横向地设置。也就是说,信号引线130(例如,信号引线的表面)可以通过模塑料340的一部分与半导体管芯350的后侧表面分离。这种分离可以在信号引线130和半导体管芯(例如,半导体管芯的后侧表面)之间提供电隔离(除了介电粘合剂360的电隔离之外)。这种额外的电隔离可以防止半导体管芯的电气故障,诸如当高电压(例如,50V或更高)施加到信号引脚130时,防止信号引线130和半导体管芯350之间的漏电。
如图3所示,介电粘合剂360可以设置在半导体管芯350(例如,半导体管芯350的后侧表面)和引线框100(或预模制引线框200)的信号引线120a-120g之间。在包括预模制引线框(诸如预模制引线框200)的器件300的实施方式中,介电粘合剂360也可以设置在半导体管芯350(例如半导体管芯350的后侧表面)和预模制引线框200的模塑料(模塑料240)之间。在诸如器件300的一些实施方式中,介电粘合剂将半导体管芯350耦接到信号引线120a-120g和130和/或预模制引线框200的模塑料240。介电粘合剂可以包含例如非导电环氧树脂、非导电膜和/或非导电带。
如图3所示,器件300的引线接合370可以用于将信号引线120a-120g和130与半导体管芯350(例如,与设置在半导体管芯350的前侧表面上的相应的接合焊盘)电耦接。在器件300中,模塑料340可以完全封装半导体管芯350、介电粘合剂360和引线接合370(例如,使得半导体管芯350、介电粘合剂360和引线接合370被包封(例如,完全包封)在模塑料340中)。此外,模塑料340可以至少部分地封装引线框。例如,信号引线120a-120g和130的面124a-124g和134可以通过模塑料340暴露(例如,未封装在模塑料340中),以提供到(COL封装)器件300外部的半导体管芯350的电触点。在包括预模制引线框(诸如预模制引线框200)的器件300的实施方式中,模塑料340可以包括第一模塑料(例如预模制引线框200的模塑料240),并且还包括第二模塑料,该第二模塑料与第一模塑料结合用于封装(完全封装)半导体管芯350、介电粘合剂360和引线接合370。
图4是对应于图3中的剖面线4-4的图3的COL半导体器件封装(COL封装)300的剖视图。如图4所示,器件300被示出为部分X光视图,其中出于说明的目的,在物理器件实施方式中不可见的器件300的引线接合370(因为它们将被包封在模塑料340中)被示出在图4中的适当位置。同样,与图2和图3一样,来自图1A和图1B的类似附图标记被用于参考器件300中所示的引线框100(或预模制引线框200的引线框100)的元件,如图4所示。
在图4所示的器件300的剖视图中,示出了器件的信号引线120c和130。图4中还示出了图2中的距离D3(例如,信号引线120c的面122c和信号引线130的面132之间的距离)。在一些实施方式中,信号引线130可以通过在引线框100的制造过程期间执行蚀刻工艺来生产。例如,信号引线130最初可以具有与引线框100的其他信号引线120a-120g基本上相同的配置(尽管与图4所示的信号引线120c相比是镜像的)。蚀刻工艺(例如,半蚀刻工艺、部分蚀刻工艺等)可以被执行以移除这种信号引线的一部分,以便从具有与引线框100的信号引线120a-120g基本上相同的配置(构造、结构等)的信号引线产生信号引线130。
如图4所示,信号引线120c和130的下部部分(例如,分别限定面124c和134的部分)可以在器件300中通过间隔D5来分开,该间隔可以等于D3、小于D3或大于D3,具体取决于特定的实施方式。同样如图4所示,介电粘合剂360(设置在半导体管芯350的后侧表面上)可以与限定面134的引线130的下部部分的内表面间隔开距离D6,其中距离D6填充有模塑料340,以在信号引线130和半导体管芯350之间提供电隔离(除了由介电粘合剂340提供的电隔离之外)。
应当理解,在前面的描述中,当元件诸如层、区域或衬底被提及在另一个元件上,连接到另一个元件,电连接到另一个元件,耦接到另一个元件,或电耦接到另一个元件上时,该元件可直接在另一个元件上,连接或耦接到另一个元件上,或者可以存在一个或多个中间元件。相反,当元件被提及直接在另一个元件或层上、直接连接到另一个元件或层、或直接耦接到另一个元件或层时,不存在中间元件或层。虽然在整个详细描述中可能不会通篇使用术语直接在…上、直接连接到…、或直接耦接到…,但是被示为直接在元件上、直接连接或直接耦接的元件能以此类方式提及。本申请的权利要求可被修订以叙述在说明书中描述或者在附图中示出的示例性关系。
如在本说明书中所使用的,除非根据上下文明确地指出特定情况,否则单数形式可包括复数形式。除了附图中所示的取向之外,空间相对术语(例如,在…上方、在…上面、在…之上、在…下方、在…下面、在…以下、在…之下、在…顶部、在…底部等)旨在涵盖器件在使用或操作中的不同取向。在一些实施方式中,在…上面和在…下面的相对术语可分别包括竖直地在…上面和竖直地在…下面。在一些实施方式中,术语邻近能包括横向邻近或水平邻近。
一些实施方式可使用各种半导体处理和/或封装技术来实现。一些实施方式可以使用与半导体衬底相关联的各种类型的半导体处理技术来实现,所述半导体衬底包括但不限于例如硅(Si)、碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)等。
虽然所描述的实施方式的某些特征已经如本文所述进行了说明,但是本领域技术人员现在将想到许多修改形式、替代形式、变化形式和等同形式。因此,应当理解,所附权利要求书旨在涵盖落入实施方式的范围内的所有此类修改形式和变化形式。应当理解,这些修改形式和变化形式仅仅以示例的方式呈现,而不是限制,并且可以进行形式和细节上的各种改变。除了相互排斥的组合以外,本文所述的装置和/或方法的任何部分可以任意组合进行组合。本文所述的实施方式能包括所描述的不同实施方式的功能、部件和/或特征的各种组合和/或子组合。

Claims (11)

1.一种引线上芯片半导体器件封装,包括:
半导体管芯,所述半导体管芯具有前侧表面和后侧表面,所述后侧表面与所述前侧表面相对;和
引线框,所述引线框具有多个信号引线,所述多个信号引线包括:
至少两个信号引线,所述至少两个信号引线的每个信号引线具有带第一表面面积的第一面和与所述第一面相对的带第二表面面积的第二面,所述至少两个信号引线的所述第二面暴露在所述引线上芯片器件封装的表面上;和
至少一个信号引线,所述至少一个信号引线具有带第三表面面积的第一面和与所述至少一个信号引线的所述第一面相对的带所述第二表面面积的第二面,所述至少一个信号引线的所述第二面暴露在所述引线上芯片半导体器件封装的所述表面上,
所述半导体管芯的所述后侧表面与所述至少两个信号引线的所述第一面耦接,所述至少一个信号引线的所述第一面从所述半导体管芯的所述后侧表面横向地设置。
2.根据权利要求1所述的引线上芯片半导体器件封装,还包括介电粘合剂,所述介电粘合剂设置在所述半导体管芯的所述后侧表面和所述至少两个信号引线的所述第一面之间。
3.根据权利要求2所述的引线上芯片半导体器件封装,其中:
所述介电粘合剂将所述半导体管芯耦接到所述至少两个信号引线的所述第一面;并且
所述介电粘合剂包含非导电环氧树脂、非导电膜或非导电带中的至少一种。
4.根据权利要求1所述的引线上芯片半导体器件封装,还包括:
多个引线接合,所述多个引线接合将所述引线框的所述多个信号引线与设置在所述半导体管芯的所述前侧表面上的相应接合焊盘电耦接;和
模塑料,其中,所述模塑料:
完全包装所述半导体管芯和所述引线接合;以及
至少部分地包装所述引线框,
所述模塑料的一部分设置在所述半导体管芯的所述后侧表面和所述至少一个信号引线之间,并且
所述至少两个信号引线的所述第二面和所述至少一个信号引线的所述第二面通过所述模塑料暴露。
5.一种引线上芯片半导体器件封装,包括:
预模制引线框,所述预模制引线框包括多个信号引线和模塑料,所述多个信号引线包括:
至少两个信号引线,所述至少两个信号引线的每个信号引线具有带第一表面面积的第一面和与所述第一面相对的带第二表面面积的第二面,所述至少两个信号引线的所述第一面暴露在所述预模制引线框的第一表面上,并且所述至少两个信号引线的所述第二面暴露在与所述预模制引线框的所述第一表面相对的所述预模制引线框的第二表面上;和
至少一个信号引线,所述至少一个信号引线具有带第三表面面积的第一面和与所述至少一个信号引线的所述第一面相对的带所述第二表面面积的第二面,所述至少一个信号引线的所述第一面暴露在所述预模制引线框的所述第一表面上,并且所述至少一个信号引线的所述第二面暴露在所述预模制引线框的所述第二表面上;和
半导体管芯,所述半导体管芯具有前侧表面和后侧表面,所述后侧表面与所述前侧表面相对,所述半导体管芯的所述后侧表面与所述预模制引线框的所述第一表面上的所述模塑料和所述至少两个信号引线的所述第一面耦接,所述至少一个信号引线的所述第一面从所述半导体管芯的所述后侧表面横向地设置。
6.根据权利要求5所述的引线上芯片半导体器件封装,还包括介电粘合剂,所述介电粘合剂设置在所述半导体管芯的所述后侧表面和所述预模制引线框的所述第一表面之间,
所述介电粘合剂将所述半导体管芯耦接到所述预模制引线框的所述第一表面。
7.根据权利要求5所述的引线上芯片半导体器件封装,还包括多个引线接合,所述多个引线接合将所述预模制引线框的所述多个信号引线与设置在所述半导体管芯的所述前侧表面上的相应接合焊盘电耦接,
所述预模制引线框的所述模塑料是第一模塑料,所述引线上芯片半导体器件封装还包括第二模塑料,
所述第二模塑料与所述第一模塑料结合完全包装所述半导体管芯和所述引线接合。
8.根据权利要求5所述的引线上芯片半导体器件封装,其中:
所述第二表面面积小于所述第一表面面积;并且
所述第三表面面积小于所述第二表面面积。
9.一种引线上芯片半导体器件封装,包括:
半导体管芯,所述半导体管芯具有前侧表面和后侧表面,所述后侧表面与所述前侧表面相对;和
引线框,所述引线框具有多个信号引线,所述多个信号引线的第一子集沿着所述引线上芯片半导体器件封装的第一边缘布置,并且所述多个信号引线的第二子集沿着所述引线上芯片半导体器件封装的第二边缘布置,所述第二边缘与所述第一边缘相对,
所述多个信号引线的所述第一子集的第一信号引线与所述多个信号引线的所述第二子集的第一信号引线间隔第一距离,所述多个信号引线的所述第二子集的所述第一信号引线在所述引线上芯片半导体器件封装中分别布置成与所述多个信号引线的所述第一子集的所述第一信号引线直接相对,
所述多个信号引线的所述第一子集的第二信号引线与所述多个信号引线的所述第二子集的第二信号引线间隔第二距离,所述多个信号引线的所述第二子集的所述第二信号引线在所述引线上芯片半导体器件封装中分别布置成与所述多个信号引线的所述第一子集的所述第二信号引线直接相对,所述第二距离大于所述第一距离,
所述半导体管芯的所述后侧表面与所述多个信号引线的所述第一子集的所述第一信号引线、所述多个信号引线的所述第二子集的所述第一信号引线和所述多个信号引线的所述第一子集的所述第二信号引线耦接,并且
所述引线上芯片半导体器件封装的模塑料设置在所述半导体管芯的所述后侧表面和所述多个信号引线的所述第二子集的所述第二信号引线之间。
10.根据权利要求9所述的引线上芯片半导体器件封装,还包括介电粘合剂,所述介电粘合剂设置在所述半导体管芯的所述后侧表面和所述多个信号引线的所述第一子集的所述第一信号引线、所述多个信号引线的所述第二子集的所述第一信号引线和所述多个信号引线的所述第一子集的所述第二信号引线之间。
11.根据权利要求9所述的引线上芯片半导体器件封装,其中,所述引线框是预模制引线框,所述半导体管芯的所述后侧表面进一步与所述预模制引线框的模塑料的表面区域耦接,所述预模制引线框的所述模塑料的所述表面与所述多个信号引线的相应表面共面,所述预模制引线框的所述模塑料包括所述引线上芯片半导体器件封装的设置在所述半导体管芯的所述后侧表面和所述多个信号引线的所述第二子集的所述第二信号引线之间的所述模塑料。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022178806A1 (en) * 2021-02-26 2022-09-01 Yangtze Memory Technologies Co., Ltd. Semiconductor package structure and packaging method thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USD940090S1 (en) * 2019-05-29 2022-01-04 Diodes Incorporated Leadframe
USD939458S1 (en) * 2019-05-29 2021-12-28 Diodes Incorporated Leadframe
NL2027540B1 (en) 2021-02-11 2022-09-12 Sencio B V Semiconductor Lead-on-Chip Assembly
IT202100017189A1 (it) * 2021-06-30 2022-12-30 St Microelectronics Srl Procedimento per fabbricare dispositivi a semiconduttore, substrato e dispositivo a semiconduttore corrispondenti

Family Cites Families (5)

* Cited by examiner, † Cited by third party
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MY169839A (en) * 2011-12-29 2019-05-16 Semiconductor Components Ind Llc Chip-on-lead package and method of forming
US9331003B1 (en) * 2014-03-28 2016-05-03 Stats Chippac Ltd. Integrated circuit packaging system with pre-molded leadframe and method of manufacture thereof
US9947636B2 (en) * 2014-06-02 2018-04-17 Stmicroelectronics, Inc. Method for making semiconductor device with lead frame made from top and bottom components and related devices
US9583421B2 (en) * 2015-07-16 2017-02-28 Semiconductor Components Industries, Llc Recessed lead leadframe packages
US10312184B2 (en) * 2015-11-04 2019-06-04 Texas Instruments Incorporated Semiconductor systems having premolded dual leadframes

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WO2022178806A1 (en) * 2021-02-26 2022-09-01 Yangtze Memory Technologies Co., Ltd. Semiconductor package structure and packaging method thereof
US11721686B2 (en) 2021-02-26 2023-08-08 Yangtze Memory Technologies Co., Ltd. Semiconductor package structure and packaging method thereof

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