CN110783267B

CN110783267B - Cut fin isolation region and method of forming the same

Info

Publication number: CN110783267B
Application number: CN201910243925.1A
Authority: CN
Inventors: 王祥保; 殷立炜; 徐绍华
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-07-31
Filing date: 2019-03-28
Publication date: 2022-04-05
Anticipated expiration: 2039-03-28
Also published as: DE102018126937B4; US20220059685A1; DE102018126937A1; CN110783267A

Abstract

The present disclosure relates to cut fin isolation regions and methods of forming the same. A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of an isolation region. The isolation region includes a portion between the first semiconductor fin and the second semiconductor fin. The method also includes forming a gate stack spanning over the first and second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation region, the first and second semiconductor fins are exposed to the opening, etching the first and second semiconductor fins and the portion of the isolation region to extend the opening into a body portion of the semiconductor substrate below the isolation region, and filling the opening with a dielectric material to form a cut fin isolation region.

Description

Cut fin isolation region and method of forming the same

Technical Field

The present disclosure generally relates to a cut fin isolation region and a method of forming the same.

Background

Technological advances in Integrated Circuit (IC) materials and design have resulted in several generations of ICs, each of which has smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (e.g., the number of interconnected devices per chip area) generally increases, while the geometry decreases. Such a shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

This shrinkage also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances. For example, fin field effect transistors (finfets) have been introduced in place of planar transistors. FinFET structures and methods of fabricating FinFETs are being developed

Disclosure of Invention

According to an embodiment of the present disclosure, there is provided a method for semiconductor processing, including forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of an isolation region, wherein the isolation region includes: a first portion between the first semiconductor fin and the second semiconductor fin; forming a gate stack across the first and second semiconductor fins; etching a first portion of the gate stack to form an opening, wherein the first portion of the isolation region, the first semiconductor fin, and the second semiconductor fin are exposed to the opening; etching the first semiconductor fin, the second semiconductor fin, and the first portion of the isolation region to extend the opening into the body portion of the semiconductor substrate below the isolation region; and filling the opening with a dielectric material to form a cut fin isolation region.

According to another embodiment of the present disclosure, there is provided a method for a semiconductor process, including: forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of an isolation region, wherein the isolation region extends into the semiconductor substrate and the isolation region includes a bottom surface; forming a gate stack across the first and second semiconductor fins; and replacing a portion of the gate stack with an additional isolation region, wherein the additional isolation region further includes a portion that passes through the first and second semiconductor fins, and the additional isolation region extends below a bottom surface of the isolation region.

According to still another embodiment of the present disclosure, there is provided a semiconductor device including: a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of a Shallow Trench Isolation (STI) region; first and second gate stacks spanning over the first and second semiconductor fins; first and second isolation regions parallel to the first and second semiconductor fins, wherein the first and second semiconductor fins are between the first and second isolation regions, and both the first and second isolation regions pass through the first and second gate stacks; and a third isolation region between the first gate stack and the second gate stack, wherein the third isolation region has a first end contacting the first isolation region and a second end contacting the second isolation region, and a portion of the STI region between the first semiconductor fin and the second semiconductor fin is penetrated by the third isolation region.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9, 10, 11A-11C, 12A-12C, 13A-13C, 14A-14C, 15A-15C, 16A-16C, 17A-17C, and 18 illustrate perspective, top, and cross-sectional views of intermediate stages in the formation of a Fin field effect transistor (FinFET), according to some embodiments.

Fig. 19 illustrates a cross-sectional view of a p-type FinFET in accordance with some embodiments.

Fig. 20 illustrates a process flow for forming an n-type FinFET in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to readily describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fin field effect transistors (finfets) formed using a fin cut process and methods of forming the same are provided according to various embodiments. An intermediate stage in forming a transistor is shown according to some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments.

Fig. 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9, 10, 11A-11C, 12A-12C, 13A-13C, 14A-14C, 15A-15C, 16A-16C, 17A-17C, and 18 illustrate cross-sectional, top, and perspective views of an intermediate stage in the formation of a FinFET employing a fin cut process according to some embodiments of the present disclosure. These processes are also schematically reflected in the process flow shown in fig. 20.

Figure 1 shows a perspective view of the initial structure. The initial structure includes a wafer 10, the wafer 10 further including a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type or n-type impurities. Isolation regions 22, such as Shallow Trench Isolation (STI) regions, are formed to extend from the top surface of the substrate 20 into the substrate 20. STI region 22 includes a liner 23 and a dielectric region 25, according to some embodiments of the present disclosure. The liner 23 may be formed of silicon nitride, silicon oxide, or the like. The dielectric region 25 may be formed of an oxide-based dielectric material (e.g., silicon oxide), which may be formed using Flowable Chemical Vapor Deposition (FCVD), spin coating, or the like.

The portion of the substrate 20 between adjacent STI regions 22 is referred to as a semiconductor strip 24. The top surfaces of the semiconductor strips 24 and the top surfaces of the STI regions 22 may be substantially flush with each other. According to some embodiments of the present disclosure, the semiconductor strips 24 are part of the original substrate 20, and the material of the semiconductor strips 24 is the same as the material of the substrate 20. In accordance with an alternative embodiment of the present disclosure, semiconductor strips 24 are replacement strips formed by etching portions of substrate 20 between STI regions 22 to form recesses, and performing an epitaxial process to re-grow another semiconductor material in the recesses. Thus, the semiconductor strips 24 are formed of a semiconductor material that is different from the semiconductor material of the substrate 20. According to some embodiments of the present disclosure, the semiconductor strips 24 are formed of silicon germanium, silicon carbon, or III-V compound semiconductor materials.

Referring to fig. 2, the STI region 22 is recessed such that the top of the semiconductor strip 24 protrudes above the top surface 22A of the remaining portion of the STI region 22 to form a protruding fin 24'. The corresponding process is shown in the process flow shown in fig. 20 as process 202. The etching may be performed using a dry etching process, wherein HF₃And NH₃Used as an etching gas. According to an alternative embodiment of the present disclosure, the recessing of the STI regions 22 is performed using a wet etch process. For example, the etching chemistry may include an HF solution.

In the embodiments described above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double-patterning or multi-patterning processes combine lithographic and self-aligned processes, allowing for the creation of patterns with, for example, smaller pitches than would otherwise be obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the fin may then be patterned using the remaining spacers or mandrels.

The material of the protruding fins 24' may be the same as or different from the material of the substrate 20. For example, the protruding fin 24' may be formed of Si, SiP, SiC, SiPC, SiGe, SiGeB, Ge, or III-V compound semiconductors (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs, etc.).

Referring to fig. 3, a dummy gate stack 30 is formed on the top surface and sidewalls of the (protruding) fin 24'. The corresponding process is shown as process 204 in the process flow shown in fig. 20. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 over the dummy gate dielectric 32. The dummy gate electrode 34 may be formed using, for example, polysilicon and other materials may also be used. Each dummy gate stack 30 may also include one (or more) hard mask layer(s) 36 over dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, a multilayer thereof, or the like. The dummy gate stack 30 may span a single or multiple protruding fins 24' and/or STI regions 22. The dummy gate stack 30 also has a length direction that is perpendicular to the length direction of the protruding fins 24'.

Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, and may have a single layer structure or a multilayer structure including a plurality of dielectric layers.

According to some embodiments of the present disclosure, an etching step (hereinafter referred to as fin recess) is performed to etch the portion of the protruding fins 24' not covered by the dummy gate stack 30 and the gate spacers 38, resulting in the structure shown in fig. 4. The recess may be anisotropic, so that the portion of the fin 24' directly under the dummy gate stack 30 and the gate spacer 38 is protected from the etching process. According to some embodiments, the top surface of the recessed semiconductor strips 24 may be lower than the top surface 22A of the STI region 22. Thus, recesses 40 are formed between the STI regions 22. Recesses 40 are located on opposite sides of dummy gate stack 30.

Next, epitaxial regions (source/drain regions) 42 are formed by selectively growing semiconductor material from the recesses 40, resulting in the structure in fig. 5A. The corresponding process is shown as process 206 in the process flow shown in fig. 20. According to some embodiments of the present disclosure, epitaxial region 42 comprises silicon germanium, silicon carbon, or the like. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, epitaxy may be used to dope the p-type or n-type impurity in-situ, respectively. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), GeB, or the like may be grown. In contrast, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown. According to an alternative embodiment of the present disclosure, epitaxial region 42 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof. After the epi region 42 completely fills the recess 40, the epi region 42 begins to expand horizontally and may form a facet. Adjacent epitaxial regions 42 may merge with one another or may be separated from one another.

After the epitaxy step, the epitaxial regions 42 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also denoted with reference numeral 42. According to an alternative embodiment of the present disclosure, the implantation step is skipped when the epitaxial region 42 is in-situ doped with p-type or n-type impurities during epitaxy. The epitaxial source/drain regions 42 may include a lower portion formed in the STI region 22 and an upper portion formed above the top surface of the STI region 22.

Fig. 5B illustrates the formation of cladding source/drain regions 42 according to an alternative embodiment of the present disclosure. According to these embodiments, the protruding fin 24 'as shown in fig. 3 is not recessed, and an epitaxial region 41 is grown on the protruding fin 24'. The material of the epitaxial region 41 may be similar to the material of the epitaxial semiconductor material 42 as shown in fig. 5A, depending on whether the resulting FinFET is a p-type or n-type FinFET. Thus, source/drain regions 42 include protruding fin 24' and epitaxial region 41. Implantation may be performed to implant an n-type impurity or a p-type impurity (or implantation may not be performed). Adjacent cladding source/drain regions 42 may also merge with one another or remain separate from one another.

Fig. 6A shows a perspective view of the structure after forming a Contact Etch Stop Layer (CESL)46 and an interlayer dielectric (ILD) 48. A corresponding process is shown in the process flow shown in fig. 20 as process 208. CESL46 may be formed of silicon nitride, silicon carbonitride, or the like. E.g. CESL46 may be formed using a conformal deposition method such as ALD or CVD. ILD 48 may comprise a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or another deposition method. ILD 48 may also be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as Tetraethylorthosilicate (TEOS) oxide, plasma-enhanced CVD (PECVD) oxide (SiO)₂) Phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like. A planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, is performed to make the top surfaces of the ILD 48, dummy gate stack 30 and gate spacer 38 flush with each other.

Fig. 6B shows a cross-sectional view of the structure shown in fig. 6A. The cross-sectional view is taken from a vertical plane containing line 6B-6B in fig. 6A. As shown in fig. 6B, one of the dummy gate stacks 30 is shown. The illustrated portion of dummy gate stack 30 is the portion directly above STI region 22. The protruding fins 24' lie in other planes not shown.

Next, the dummy gate stack 30, including the hard mask layer 36, dummy gate electrode 34, and dummy gate dielectric 32, is replaced with a replacement gate stack, which may include a metal gate and a replacement gate dielectric as shown in fig. 7A and 7B. The corresponding process is shown as process 210 in the process flow shown in fig. 20. According to some embodiments of the present disclosure, the replacement process includes etching the hard mask layer 36, dummy gate electrode 34, and dummy gate dielectric 32 as shown in fig. 6A and 6B in one or more process steps such that openings are formed between opposing portions of the gate spacers 38. A corresponding structure may be realized from the structure shown in fig. 6A by removing dummy gate stack 30.

Next, referring to fig. 7A and 7B, a (replacement) gate stack 60 is formed, which includes the gate dielectric layer 54 (see fig. 7B) and the gate electrode 56. The formation of the gate stack 60 includes forming/depositing a plurality of layers and then performing a planarization process, such as a CMP process or a mechanical polishing process. The formation of the gate stack 60 includes forming/depositing a plurality of layers and then performing a planarization process, such as a CMP process or a mechanical polishing process. Gate dielectric layer 54 extends into the trench left by the removed dummy gate stack. According to some embodiments of the present disclosure, the gate dielectric layer 54 includes an Interfacial Layer (IL) as a lower portion thereof. IL is formed on the exposed surface of the protruding fin 24'. Each IL may include an oxide layer (e.g., a silicon oxide layer) formed by thermal oxidation, chemical oxidation process, or deposition process of the protruding fins 24'. Gate dielectric layer 54 may also include a high-k dielectric layer 52 formed over the corresponding IL. The high-k dielectric layer 52 may be formed of a high-k dielectric material, e.g., HfO₂、ZrO₂、HfZrOx、HfSiOx、HfSiON、ZrSiOx、HfZrSiOx、Al₂O₃、HfAlOx、HfAlN、ZrAlOx、La₂O₃、TiO₂、Yb₂O₃Silicon nitride, and the like. The high-k dielectric material has a dielectric constant (k value) higher than 3.9 and may be higher than about 7.0. The high-k dielectric layer is formed as a conformal layer and extends over the sidewalls of the protruding fins 24' and the sidewalls of the gate spacers 38. According to some embodiments of the present disclosure, the high-k dielectric layer is formed using ALD or CVD.

Referring again to fig. 7A and 7B, a gate electrode 56 is formed over dielectric layer 52 and fills the remaining portion of the trench left by the removed dummy gate stack. The sublayers in the gate electrode 56 are not separately shown in fig. 7A, but the sublayers may be distinguished from each other due to their different compositions. The deposition of at least some of the lower sub-layers may be performed using a conformal deposition method, such as ALD or CVD, such that the thickness of the vertical portions and the thickness of the horizontal portions of the gate electrode 56 (and each sub-layer) are substantially equal to each other.

Gate electrode 56 may include multiple layers including, but not limited to: a Titanium Silicon Nitride (TSN) layer, a titanium nitride (TiN) layer, a titanium aluminum (TiAl) layer, an additional TiN and/or TaN layer, and a filler metal. Some of these layers define the work function of the corresponding FinFET. It is to be understood that this layer stack is an example, and that metal stacks having different structures may be employed. Further, the metal layers of the p-type finfets and the n-type finfets may be different from each other such that the work function of the metal layers is appropriate for the respective p-type or n-type finfets. The filler metal may include aluminum, copper, tungsten, cobalt, and the like.

Fig. 7B shows a cross-sectional view of the metal gate stack 60. The cross-sectional view is taken from a vertical plane containing 7B-7B as shown in fig. 7A. Since the cross-sectional view is taken from a plane that intersects the STI region 22 rather than the protruding fin 24', there may be no IL present in the cross-sectional view. In contrast, the high-k dielectric layer in gate dielectric 52 contacts the top surface of STI region 22.

Next, as shown in fig. 8A and 8B, a dielectric hard mask 62 is formed. The corresponding process is shown in the process flow shown in fig. 20 as process 212. The material of the hard mask 62 may be the same as or different from some of the CESL46, ILD 48, and/or gate spacers 38. The formation of the hard mask 62 includes recessing the replacement gate stack 60 by etching to form a recess, filling a dielectric material into the recess, and performing planarization to remove excess portions of the dielectric material, according to some embodiments of the present disclosure. The remaining portion of the dielectric material is a hard mask 62. According to some embodiments of the present disclosure, the hard mask 62 is formed of silicon nitride, silicon oxynitride, silicon oxycarbide nitride, or the like.

Fig. 8B shows a cross-sectional view of the structure shown in fig. 8A, taken from a plane containing line 8B-8B in fig. 8A.

Fig. 9 illustrates a top view of a portion of a device die in a wafer 10, according to some embodiments of the present disclosure. The plurality of fins 24' and semiconductor strips 24 are allocated as parallel strips between STI regions 22. A plurality of gate stacks 60 and hard masks 62 are also formed as parallel strips and source/drain regions 42 are formed based on the fins 24' and between the gate stacks 60. A plurality of isolation regions 66 are formed to cut the long gate stacks 60 apart. Throughout the specification, the isolation region 66 is alternatively referred to as a cut metal isolation region. The isolation region 66 may be formed of, for example, silicon nitride, silicon oxide, or the like, and may be formed of a single layer or a composite layer including a plurality of layers.

Fig. 10 shows a perspective view of one of the isolation regions 66. The regions shown in fig. 10 include regions 63 as in fig. 9. As shown in fig. 10, the isolation region 66 may pass through the ILD 48, CESL46, hard mask 62, and gate stack 60, and may extend into a bulk portion of the substrate 20. The formation of the isolation region 66 may include etching the ILD 48, CESL46, hard mask 62, and gate stack 60, and filling the resulting recess with a dielectric material. A corresponding process for forming the isolation regions 66 is shown in the process flow as shown in fig. 20 as process 214.

Fig. 11A, 11B and 11C to fig. 17A, 17B and 17C show cross-sectional views of intermediate stages in the formation of isolation regions for cutting the semiconductor fins 24' and the semiconductor strips 24. Corresponding isolation regions are formed in the region 65 as shown in fig. 9. In fig. 11A, 11B, and 11C to fig. 17A, 17B, and 17C, the reference numbers include the letter "a", the letter "B", or the letter "C". The letter "a" indicates that the corresponding drawing is a cross-sectional view taken from the same vertical plane as the vertical plane containing the line a-a in fig. 9. The letter "B" indicates that the corresponding drawing is taken from the same vertical plane as the vertical plane containing the line B-B in fig. 9. The letter "C" indicates that the corresponding drawing is taken from the same vertical plane as the vertical plane containing the line C-C in fig. 9. FIG. 10 also shows lines A-A, B-B and C-C.

Referring to fig. 11A, 11B and 11C, a patterned etch mask 68 is formed over the structure shown in fig. 9 and 10. The corresponding process is shown as process 216 in the process flow shown in fig. 20. According to some embodiments, the etch mask 68 comprises a photoresist, a metal-containing hard mask such as a TiN layer, or the like. An opening(s) 69 is formed in the etch mask 68 to expose an underlying portion of the gate stack. The isolation region 66 may expose portions through the opening 69. The size and location of the opening 69 is substantially the same as the area 65 shown in fig. 9. As shown in fig. 11A, portions of the protruding fin 24' are located directly below the opening 69. As shown in fig. 11B, portions of STI regions 22 are located directly below openings 69. According to some embodiments, as shown in fig. 11A and 11B, STI region 22 includes a dielectric liner 23 and a capping dielectric region 25. According to some embodiments, dielectric liner 23 is formed of silicon nitride and overlying dielectric region 25 may be formed of silicon oxide, and other dielectric materials may also be used to form dielectric liner 23 and dielectric region 25. In subsequent figures, layers 23 and 25 in STI region 22 are not shown, but are still present. Fig. 11C shows the source/drain regions 42 between the gate stacks 60.

Fig. 12A, 12B and 12C illustrate etching the hard mask 62 and the gate stack 60 to form an opening 70. A corresponding process is shown as process 218 in the process flow shown in fig. 20. The etch causes removal of the portion of metal gate stack 60 exposed through opening 70. The etching may be performed by wet etching or dry etching. For example, when a wet etch is employed, a Sulfate Peroxide Mixture (SPM) solution (a solution of sulfuric acid and hydrogen peroxide) may be used to etch metal gate 56. The gate dielectric 52 may also be removed by an SPM solution. When dry etching is used, Cl may be used₂And BCl₃A mixture of gases. It is also possible to use a compound selected from but not limited to Cl₂、SiCl₄、O₂、C₄F₆HBr, He, and combinations thereof. The dry etch may be such that the gate electrode 56 and the high-k dielectric in the gate dielectric 52 are removed (fig. 11A), and the interfacial layer in the gate dielectric 52 may remain unetched. Fig. 12B and 12C show cross-sectional views taken from the same plane as the plane including lines B-B and C-C in fig. 9 after etching the gate stack 60, the STI region 22, and the semiconductor fin 24' (over the top surface 22A of the STI region 22). As shown in fig. 12C and some subsequent figures, top surface 22A and bottom surface 22B of STI region 22 are shown, and STI region 22 will be located at a level between top surface 22A and bottom surface 22B.

Referring to fig. 13A, 13B and 13C, the exposed portions of STI regions 22 are recessed, forming recesses 72. The corresponding process is shown as process 220 in the process flow shown in fig. 20. The thickness T1 of the remaining portion of STI region 22 is less than about 20nm, and may be in a range between about 5nm and about 20nm, according to some embodiments of the present disclosure. According to some embodiments, the etchant is selected such that there is a high etch selectivity between STI regions 22 and fin/strips 24'/24, e.g., the etch selectivity may be greater than about 50. The etchant may include an etching gas, for exampleE.g. CF₄、N₂And H₂A mixture of (A) or (C)₄F₆And O₂A mixture of (a). As shown in fig. 13B, the recess 72 extends into the STI region 22. According to some embodiments of the present disclosure, the bottom of the recess 72 is higher than the top surface of the dielectric liner 23. The structure shown in fig. 13C is the same as that shown in fig. 12C.

The protruding fins 24' (fig. 13A) and the underlying semiconductor strips 24 are then etched, resulting in the structure shown in fig. 14A, 14B and 14C. A corresponding process is shown as process 222 in the process flow shown in fig. 20. In addition, the portion of the body substrate 20 underlying the semiconductor strips 24 is also etched such that a recess 74 is formed between the remaining portions of the STI regions 22 and extends further into the body portion of the substrate 20. The etchant is selected such that during etching, the STI regions 22 are not substantially etched. According to some embodiments, the etchant comprises a chlorine-based etching gas or an HBr-based etching gas. The etchant is selected such that there is a high etch selectivity between the fin/strip 24'/24 and the STI region 22, for example, the etch selectivity may be greater than about 50. The etching gas may include Cl₂、SiCl₄And O₂Mixture of (1), Cl₂、SiCl₄And N₂HBr, O₂And Ar, or HBr, O₂And a mixture of He. In fig. 14C, an opening 74 is shown through the protruding fin 24'.

Next, the remaining portions of the STI regions 22 are removed in an etching process, and the resulting structure is shown in fig. 15A, 15B, and 15C. The corresponding process is shown as process 224 in the process flow shown in fig. 20. As shown in fig. 15A, all STI regions 22 exposed to opening 69 are removed (fig. 14A) and the underlying host substrate 20 is exposed. Fig. 15B shows

openings

72 and 74 through STI region 22. The structure shown in fig. 15C is similar to the structure shown in fig. 14C, except that portions of the body portion of the substrate 20 may be recessed during the etching process. According to some embodiments, as shown in fig. 15B, recessing of the body portion of substrate 20 causes opening 74 to extend into the body portion of substrate 20 to a depth D1, which may be greater than about 1nm, and may range between about 1nm and about 150 nm. The etch mask 68 is then removed.

Fig. 16A, 16B, and 16C illustrate the deposition of dielectric isolation regions 76, which are alternatively referred to as cut fin isolation regions 76. A corresponding process is shown as process 226 in the process flow shown in fig. 20. The formation of the dielectric isolation regions 76 may include depositing a dielectric material into the

openings

70, 72, and 74 (fig. 15A, 15B, and 15C). The deposition methods may include Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD), spin coating, Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like. The deposited dielectric material 76 may comprise silicon oxide, silicon carbide, silicon oxycarbide, or other types of low defect density dielectric materials. According to some embodiments, the deposited dielectric material 76 includes a liner formed of a non-SiN material, such as silicon oxide, and a fill dielectric material over the liner. The fill dielectric material may be formed of a SiN or non-SiN material. According to some embodiments, the entire dielectric material 76 is formed of a non-SiN dielectric material, such as silicon oxide. Using a non-SiN material to form the liner of the dielectric isolation region 76 may advantageously prevent leakage in the substrate 20, as will be discussed in subsequent paragraphs.

Fig. 17A, 17B and 17C illustrate a planarization process, such as a CMP process or a mechanical polishing process, to remove excess portions of the isolation regions 76. According to some embodiments of the present disclosure, the hard mask 62 is used as a stop layer for the planarization process. In subsequent processes, source/drain silicide regions, source/drain contact plugs, gate contact plugs, etc. (not shown) are formed to complete the formation of

finfets

90A and 90B (fig. 18).

In fig. 17A, the removed portions of the STI regions 22 and the protruding fins 24' and strips 24 are shown using dashed lines. As shown in fig. 17A, the bottom of isolation region 76 is recessed a distance D1 below the bottom of STI region 22, which distance D1 may be greater than about 1nm, and may range between about 1nm and about 150 nm. If the distance D1 is less than about 1nm, the process may risk leaving the dielectric liner 23 behind, which results in leakage current. If the distance D1 is greater than about 150nm, the formation of the well region (which may be a p-well region) may cause problems. The isolation region 76 may extend downward from the top of the protruding fin 24' by a height H1, which height H1 may be in a range between about 80nm and about 250 nm. If height H1 is less than about 80nm, semiconductor strip 24 (fig. 11A) may not be completely removed when process variations occur, and thus leakage will occur in semiconductor strip 24. If the height H1 is greater than about 250nm, the formation of the well region may cause problems.

Fig. 18 shows a top view of the resulting structure, where finfets 90A and 90B are formed as a result of the foregoing process.

Finfets

90A and 90B are defined by

isolation regions

66 and 76. Isolation regions 76 separate source/drain regions (e.g., 90A and 90B) of finfets (e.g., 90A and 90B) from one another. The isolation region 66 separates the gate stack of a FinFET (e.g., 90A and 90B) from the gate stack of an adjacent FinFET. It should be understood that the layout, size, and location of the

isolation regions

66 and 76 may be different than shown. For example, rather than cutting multiple gate stacks 60, the isolation region 66 may include multiple individual shorter portions, each cutting one of the gate stacks 60.

Isolation regions 76 formed according to some embodiments of the present disclosure have advantageous features for eliminating leakage currents. Referring again to fig. 17A, the location of the removed dielectric liner 23 is shown. When the dielectric liner 23 is not removed and is formed of some vulnerable dielectric material such as silicon nitride, positive charges (as schematically shown using a "+" symbol) are trapped in the dielectric liner 23. The captured positive charges attract negative charges (shown schematically using the "-" symbol) to thin surface layers (shown using dashed lines as they are removed) in the semiconductor strip 24. Thus, the negative charge accumulation layer forms a leakage path extending in a direction into or out of the plane, as shown in fig. 17A. The leakage path is also shown by arrow 88 in fig. 18. The leakage path affects the n-type FinFET because the dominant carrier of the n-type FinFET is an electron. An advantageous feature according to some embodiments of the present disclosure is that the STI region 22, as shown using dashed lines in fig. 17A, is removed, thus eliminating leakage paths.

Referring to fig. 18, according to some embodiments of the present disclosure, finfets 90A and 90B are both n-type finfets. On the same die and same wafer, there may be p-type finfets, which may have substantially the same or similar top-view structure as shown in fig. 18, and the corresponding cut-fin isolation regions between the p-type finfets may have the same structure as shown in fig. 17A. According to an alternative embodiment, because p-type finfets use holes as the majority carriers, p-type finfets may not suffer from leakage problems caused by the aforementioned accumulated charge. Thus, the cut fin isolation regions used to isolate the source/drain regions of a p-type FinFET may have the structure shown in fig. 19, on the same die and on the same semiconductor substrate 20. The corresponding cut fin isolation regions 76 also cut the fins, while the STI regions 22 exposed during removal of the gate stack are not etched. Thus, the STI regions 22 "are retained between the two extensions of the respective isolation regions 76. The formation of isolation regions 76 is similar to that discussed with reference to fig. 11A, 11B and 11C to fig. 17A, 17B and 17C, except that after the steps shown in fig. 12A, 12B and 12C, the protruding fin 24', the semiconductor strip 24 and the underlying body portion of the substrate 20 are etched to form recesses, while the STI region 22 "is not etched.

According to some embodiments, isolation regions 66 are formed prior to forming isolation regions 76. According to other embodiments of the present disclosure, the isolation region 66 is formed after the isolation region 76 is formed. These processes are similar to those shown in fig. 9, 10, 11A to 11C, 12A to 12C, 13A to 13C, 14A to 14C, 15A to 15C, 16A to 16C, 17A to 17C, and 18, except that in fig. 9 and 10, the isolation regions 66 have not yet been formed. Instead, the isolation regions 66 are formed after the step shown in fig. 18.

Embodiments of the present disclosure have some advantageous features. By removing the STI regions exposed during the formation of the cut fin isolation regions, leakage currents caused by the STI regions, in particular by the fragile dielectric liner in the STI regions, are eliminated.

According to some embodiments of the present disclosure, a method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of an isolation region, wherein the isolation region includes a first portion between the first semiconductor fin and the second semiconductor fin; forming a gate stack across the first and second semiconductor fins; etching a first portion of the gate stack to form an opening, wherein the first portion of the isolation region, the first semiconductor fin, and the second semiconductor fin are exposed to the opening; etching the first semiconductor fin, the second semiconductor fin, and the first portion of the isolation region to extend the opening into the body portion of the semiconductor substrate below the isolation region; and filling the opening with a dielectric material to form a cut fin isolation region. In an embodiment, a first portion of the isolation region is etched through to expose a body portion of the semiconductor substrate. In an embodiment, when etching the first portion of the isolation region, a second portion of the isolation region is etched, and the second portion of the isolation region is on an opposite side of a combined region that includes both the first semiconductor fin and the second semiconductor fin. In an embodiment, etching the first semiconductor fin, the second semiconductor fin, and the first portion of the isolation region includes: performing a first etching step to recess a first portion of the isolation region; performing a second etching step to etch the first and second semiconductor fins; and a third etching step is performed to completely remove the first portion of the isolation region. In an embodiment, in the first etching step, the first and second semiconductor fins are substantially not etched, and in the second etching step, a remaining portion of the first portion of the isolation region is substantially not etched. In an embodiment, the method further comprises forming a cut metal isolation region to cut the gate stack into a first portion and a second portion, wherein sidewalls of the cut metal isolation region are exposed to the opening. In an embodiment, a portion of the cut fin isolation region in contact with the cut metal isolation region has a bottom surface higher than a bottom surface of the cut metal isolation region.

According to some embodiments of the disclosure, a method comprises: forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of an isolation region, wherein the isolation region extends into the semiconductor substrate and the isolation region includes a bottom surface; forming a gate stack across the first and second semiconductor fins; and replacing a portion of the gate stack with a cut fin isolation region, wherein the cut fin isolation region further includes a portion that passes through the first and second semiconductor fins, and the cut fin isolation region extends below a bottom surface of the isolation region. In an embodiment, an entire bottom surface of the cut fin isolation region is lower than a bottom surface of the isolation region. In an embodiment, forming the cut fin isolation region includes: etching a portion of the gate stack to form an opening, wherein a portion of the first semiconductor fin, a portion of the second semiconductor fin, and a first portion of the isolation region are exposed to the opening, and the first portion of the isolation region is between the first semiconductor fin and the second semiconductor fin; etching the portion of the first semiconductor fin, the portion of the second semiconductor fin, and the first portion of the isolation region to extend the opening into the body portion of the semiconductor substrate below the isolation region; and filling the opening with a dielectric material to form a cut fin isolation region. In an embodiment, when etching the first portion of the isolation region, a second portion of the isolation region is also etched, and the second portion of the isolation region is on an opposite side of a combined region including both the first semiconductor fin and the second semiconductor fin. In an embodiment, filling the opening with a dielectric material includes forming a silicon oxide region that contacts a body portion of the semiconductor substrate. In an embodiment, the method further includes forming a first cut metal isolation region and a second cut metal isolation region each cutting the gate stack into two portions, wherein a first sidewall and a second sidewall of the cut fin isolation region contact sidewalls of the first cut metal isolation region and the second cut metal isolation region. In an embodiment, forming the gate stack includes forming a metal gate stack. In an embodiment, the gate stack is between two gate spacers, and the cut fin isolation region is formed between the two gate spacers.

According to some embodiments of the disclosure, a device comprises: a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of the isolation region; first and second gate stacks spanning over the first and second semiconductor fins; first and second cut metal isolation regions parallel to the first and second semiconductor fins, wherein the first and second semiconductor fins are between the first and second cut metal isolation regions, and both the first and second cut metal isolation regions pass through the first and second gate stacks; and a cut fin isolation region between the first gate stack and the second gate stack, wherein the cut fin isolation region has a first end contacting the first cut metal isolation region and a second end contacting the second cut metal isolation region, and a portion of the isolation region between the first semiconductor fin and the second semiconductor fin is penetrated by the cut fin isolation region. In an embodiment, an entire bottom surface of the cut fin isolation region is lower than a bottom surface of the isolation region. In an embodiment, a portion of the cut fin isolation region that is in contact with the first semiconductor fin is formed of silicon oxide. In an embodiment, cutting the bottom surface of the fin isolation region comprises: a first portion aligned with a portion of the first semiconductor fin in a top view of the device; a second portion aligned with an additional portion of the second semiconductor fin in a top view of the device; and a third portion connecting the first portion to the second portion of the bottom surface, wherein the third portion is higher than the first portion and the second portion. In an embodiment, the isolation region comprises: a silicon nitride liner; and a silicon oxide region over and contacting the bottom portion of the silicon nitride liner.

The foregoing has outlined features of some embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is a method for semiconductor processing, comprising: forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of an isolation region, wherein the isolation region comprises: a first portion between the first semiconductor fin and the second semiconductor fin; forming a gate stack across the first and second semiconductor fins; etching a first portion of the gate stack to form an opening, wherein the first portion of the isolation region, the first semiconductor fin, and the second semiconductor fin are exposed to the opening; etching the first semiconductor fin, the second semiconductor fin, and the first portion of the isolation region to extend the opening into a body portion of the semiconductor substrate below the isolation region; and filling the opening with a dielectric material to form a cut fin isolation region.

Example 2 is the method of example 1, wherein the first portion of the isolation region is etched through to expose a body portion of the semiconductor substrate.

Example 3 is the method of example 1, wherein when etching the first portion of the isolation region, a second portion of the isolation region is etched, and the second portion of the isolation region is on opposite sides of a combined region including both the first semiconductor fin and the second semiconductor fin.

Example 4 is the method of example 1, wherein etching the first semiconductor fin, the second semiconductor fin, and the first portion of the isolation region includes: performing a first etching step to recess the first portion of the isolation region; performing a second etching step to etch the first and second semiconductor fins; and performing a third etching step to completely remove the first portion of the isolation region.

Example 5 is the method of example 4, wherein, in the first etching step, the first and second semiconductor fins are substantially not etched, and in the second etching step, a remaining portion of the first portion of the isolation region is substantially not etched.

Example 6 is the method of example 1, further comprising forming a cut metal isolation region to cut the gate stack into the first and second portions, wherein sidewalls of the cut metal isolation region are exposed to the opening.

Example 7 is the method of example 6, wherein a portion of the cut fin isolation region in contact with the cut metal isolation region has a bottom surface higher than a bottom surface of the cut metal isolation region.

Example 8 is a method for semiconductor processing, comprising: forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of an isolation region, wherein the isolation region extends into a semiconductor substrate and comprises a bottom surface; forming a gate stack across the first and second semiconductor fins; and replacing a portion of the gate stack with an additional isolation region, wherein the additional isolation region further includes a portion that passes through the first and second semiconductor fins, and the additional isolation region extends below a bottom surface of the isolation region.

Example 9 is the method of example 8, wherein an entire bottom surface of the additional isolation region is lower than the bottom surface of the isolation region.

Example 10 is the method of example 8, wherein forming the additional isolation region comprises: etching a portion of the gate stack to form an opening, wherein a portion of the first semiconductor fin, a portion of the second semiconductor fin, and a first portion of the isolation region are exposed to the opening, and the first portion of the isolation region is between the first semiconductor fin and the second semiconductor fin; etching the portion of the first semiconductor fin, the portion of the second semiconductor fin, and the first portion of the isolation region to extend the opening into a body portion of the semiconductor substrate below the isolation region; and filling the opening with a dielectric material to form the additional isolation region.

Example 11 is the method of example 10, wherein when etching the first portion of the isolation region, a second portion of the isolation region is also etched, and the second portion of the isolation region is on opposite sides of a combined region including both the first semiconductor fin and the second semiconductor fin.

Example 12 is the method of example 10, wherein filling the opening with the dielectric material includes forming a silicon oxide region that contacts the body portion of the semiconductor substrate.

Example 13 is the method of example 8, further comprising: forming a first cut metal isolation region and a second cut metal isolation region each cutting the gate stack into two portions, wherein first and second sidewalls of the additional isolation region contact sidewalls of the first and second cut metal isolation regions.

Example 14 is the method of example 8, wherein forming the gate stack includes forming a metal gate stack.

Example 15 is the method of example 8, wherein the gate stack is between two gate spacers, and the additional isolation region is formed between the two gate spacers.

Example 16 is a semiconductor device, comprising: a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of a Shallow Trench Isolation (STI) region; a first gate stack and a second gate stack spanning over the first semiconductor fin and the second semiconductor fin; first and second isolation regions parallel to the first and second semiconductor fins, wherein the first and second semiconductor fins are between the first and second isolation regions, and the first and second isolation regions both pass through the first and second gate stacks; and a third isolation region between the first gate stack and the second gate stack, wherein the third isolation region has a first end contacting the first isolation region and a second end contacting the second isolation region, and a portion of the STI region between the first semiconductor fin and the second semiconductor fin is intersected by the third isolation region.

Example 17 is the device of example 16, wherein an entire bottom surface of the third isolation region is lower than a bottom surface of the STI region.

Example 18 is the device of example 16, wherein a portion of the third isolation region in contact with the first semiconductor fin is formed of silicon oxide.

Example 19 is the device of example 16, wherein a bottom surface of the third isolation region includes: a first portion aligned with a portion of the first semiconductor fin in a top view of the device; a second portion aligned with an additional portion of the second semiconductor fin in the top view of the device; and a third portion connecting the first portion to the second portion of the bottom surface, wherein the third portion is higher than the first portion and the second portion.

Example 20 is the device of example 16, wherein the STI region comprises: a silicon nitride liner; and a silicon oxide region over and contacting a bottom portion of the silicon nitride liner.

Claims

1. A method for semiconductor processing, comprising:

forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of an isolation region, wherein the isolation region comprises:

a first portion between the first semiconductor fin and the second semiconductor fin;

forming a gate stack across the first and second semiconductor fins;

etching a first portion of the gate stack to form an opening, wherein the first portion of the isolation region, the first semiconductor fin, and the second semiconductor fin are exposed to the opening;

etching the first semiconductor fin, the second semiconductor fin, and the first portion of the isolation region to extend the opening into a body portion of the semiconductor substrate below the isolation region; and

filling the opening with a dielectric material to form a cut fin isolation region,

wherein the method further comprises: forming a cut metal isolation region to cut the gate stack into the first and second portions, wherein sidewalls of the cut metal isolation region are exposed to the opening.

2. The method of claim 1, wherein the first portion of the isolation region is etched through to expose a body portion of the semiconductor substrate.

3. The method of claim 1, wherein when etching the first portion of the isolation region, a second portion of the isolation region is etched, and the second portion of the isolation region is on opposite sides of a combined region including both the first and second semiconductor fins.

4. The method of claim 1, wherein etching the first semiconductor fin, the second semiconductor fin, and the first portion of the isolation region comprises:

performing a first etching step to recess the first portion of the isolation region;

performing a second etching step to etch the first and second semiconductor fins; and is

A third etching step is performed to completely remove the first portion of the isolation region.

5. The method of claim 4, wherein in the first etching step, the first and second semiconductor fins are not etched, and in the second etching step, a remaining portion of the first portion of the isolation region is not etched.

6. The method of claim 1, wherein a portion of the cut fin isolation region in contact with the cut metal isolation region has a bottom surface that is higher than a bottom surface of the cut metal isolation region.

7. A method for semiconductor processing, comprising:

forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of an isolation region, wherein the isolation region extends into a semiconductor substrate and comprises a bottom surface;

forming a gate stack across the first and second semiconductor fins; and

replacing a portion of the gate stack with an additional isolation region, wherein the additional isolation region further includes a portion that passes through the first and second semiconductor fins, and the additional isolation region extends below a bottom surface of the isolation region,

wherein the method further comprises: forming first and second cut metal isolation regions each cutting the gate stack into two portions, wherein first and second sidewalls of the additional isolation region contact sidewalls of the first and second cut metal isolation regions.

8. The method of claim 7, wherein an entire bottom surface of the additional isolation region is lower than the bottom surface of the isolation region.

9. The method of claim 7, wherein forming the additional isolation region comprises:

etching a portion of the gate stack to form an opening, wherein a portion of the first semiconductor fin, a portion of the second semiconductor fin, and a first portion of the isolation region are exposed to the opening, and the first portion of the isolation region is between the first semiconductor fin and the second semiconductor fin;

etching the portion of the first semiconductor fin, the portion of the second semiconductor fin, and the first portion of the isolation region to extend the opening into a body portion of the semiconductor substrate below the isolation region; and is

Filling the opening with a dielectric material to form the additional isolation region.

10. The method of claim 9, wherein when etching the first portion of the isolation region, a second portion of the isolation region is also etched, and the second portion of the isolation region is on an opposite side of a combined region that includes both the first and second semiconductor fins.

11. The method of claim 9, wherein filling the opening with the dielectric material comprises forming a silicon oxide region that contacts the body portion of the semiconductor substrate.

12. The method of claim 7, wherein forming the gate stack comprises forming a metal gate stack.

13. The method of claim 7, wherein the gate stack is between two gate spacers and the additional isolation region is formed between the two gate spacers.

14. A semiconductor device, comprising:

a first semiconductor fin and a second semiconductor fin parallel to each other and protruding above a top surface of a Shallow Trench Isolation (STI) region;

a first gate stack and a second gate stack spanning over the first semiconductor fin and the second semiconductor fin;

first and second isolation regions parallel to the first and second semiconductor fins, wherein the first and second semiconductor fins are between the first and second isolation regions, and the first and second isolation regions both pass through the first and second gate stacks; and

a third isolation region between the first gate stack and the second gate stack, wherein the third isolation region has a first end contacting the first isolation region and a second end contacting the second isolation region, and a portion of the STI region between the first semiconductor fin and the second semiconductor fin is intersected by the third isolation region.

15. The device of claim 14, wherein an entire bottom surface of the third isolation region is lower than a bottom surface of the STI region.

16. The device of claim 14, wherein a portion of the third isolation region in contact with the first semiconductor fin is formed of silicon oxide.

17. The device of claim 14, wherein a bottom surface of the third isolation region comprises:

a first portion aligned with a portion of the first semiconductor fin in a top view of the device;

a second portion aligned with an additional portion of the second semiconductor fin in the top view of the device; and

a third portion connecting the first portion to the second portion of the bottom surface, wherein the third portion is higher than the first portion and the second portion.

18. The device of claim 14, wherein the STI region comprises:

a silicon nitride liner; and

a silicon oxide region over and contacting a bottom portion of the silicon nitride liner.