TWI755178B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.

Description

Semiconductor element and method of manufacturing the same

The present disclosure relates to a semiconductor element and a method of manufacturing the same.

Technological advances in integrated circuit (IC) materials and design have produced several generations of integrated circuits, each of which has smaller and more complex circuits than previous generations. During the development of integrated circuits, functional density (eg, the number of interconnecting elements per wafer area) has generally increased while geometry has decreased. This scaling down process often benefits from increased production efficiency and reduced associated costs.

This scaling down also increases the complexity of integrated circuit processing and fabrication, and in order for these advancements to be realized, similar developments in integrated circuit processing and fabrication are required. For example, Fin Field-Effect Transistors (FinFETs) have been introduced to replace planar transistors. The structure of the fin field effect transistor and the method of fabricating the fin field effect transistor are under development.

FinFET formation typically involves forming long semiconductor fins and long gate stacks, and then forming isolation regions to connect the long semiconductor fins. The body fin and long gate stack are cut into shorter sections so that the shorter sections can serve as the fin and gate stack of the finFET.

According to some embodiments of the present disclosure, there is provided a method comprising: forming a semiconductor fin projecting above a plurality of top surfaces of a plurality of isolation regions, wherein the isolation regions extend into a semiconductor substrate; and etching portions of the semiconductor fin to form a trench, wherein the trench extends below the bottom surface of the isolation region and into the semiconductor substrate; fills the trench with a first dielectric material to form a first fin isolation region; recesses the first fin isolation region forming a first groove; and filling the first groove with a second dielectric material, wherein the first dielectric material and the second dielectric material combine to form a second fin isolation region.

According to some embodiments of the present disclosure, there is provided a device including: a semiconductor substrate, a plurality of isolation regions, and a dielectric region. A plurality of isolation regions extend into the semiconductor substrate. The dielectric region includes a lower portion and an upper portion. The lower portion has a first slit therein. The upper portion has a second slit therein, wherein the first slit is spaced from the second slit through a bottom portion of the upper portion of the dielectric region.

According to some embodiments of the present disclosure, there is provided a device including: a substrate, a plurality of isolation regions, a semiconductor fin, a first epitaxial semiconductor region, a second epitaxial semiconductor region, a first dielectric region, and a second dielectric region. electrical area. A plurality of isolation regions extend into the substrate. Semiconductor fins extend upward from the plurality of top surfaces of the isolation regions. The first epitaxial semiconductor region and the first Two epitaxial semiconductor regions extend into the semiconductor fins. The first dielectric region is laterally between the first epitaxial semiconductor region and the second epitaxial semiconductor region. The second dielectric region is on the first dielectric region, wherein the second dielectric region includes a U-shaped bottom site in contact with the top surface of the first dielectric region.

10: Wafer

20: Substrate

22: Shallow trench isolation region

22A: Top surface

22B: Bottom surface

24: Semiconductor strips

24': Protruding fins

25: Dielectric Dummy Strips

25': Dummy Fin

30: Dummy gate stack

32: Dummy gate dielectric

34: Dummy gate electrode

36: Hard mask layer

38: Gate spacer

38TS: Top surface

40: Groove

41: Epitaxy area

42: Epitaxy area

46: Contact etch stop layer

48: Interlayer dielectric layer

50: Gate isolation area

51: Gap

52: Dielectric Mask

54: Fin isolation area

54': Pad

54's: Line

54S: Interface layer

55: Gap

56: Groove

57: Dotted line

58: gate dielectric layer

60: Gate electrode

62: Gate stack

66: Dielectric hard mask

66S: Interface layer

67: Gap

68: Groove

68A: Groove

68B: Groove

70: Dielectric region

70A: Dielectric area

70B: Dielectric region

70C: Dielectric region

71: Gap

71A: Gap

71B: Gap

73: Area

74: Gate contact plug

75: Quarantine area

76: source/drain silicide region

78: source/drain contact plug

80A: Fin Field Effect Transistor

80B: Fin Field Effect Transistor

84: Area

200: Manufacturing Process

202: Steps

204: Steps

206: Steps

208: Steps

210: Steps

212: Steps

214: Steps

216: Steps

218: Steps

220: Steps

222: Steps

224: Steps

226: Steps

228: Steps

230: Steps

232: Steps

7B-7B: Cross Section

8B-8B: Cross Section

D1: Distance

H1: height

W1: width

W2: width

X: direction

Y: direction

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is understood that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity.

Figures 1-4, 5A, 5B, 6, 7A, 7B, 8A, 8B, and 9-15 illustrate the formation according to some embodiments Perspective, cross-sectional, and top views of the isolation region and intermediate stage of the finFET.

FIG. 16A shows a top view of the device region according to some embodiments.

FIG. 16B shows a perspective view of a device area according to some embodiments.

FIG. 17 illustrates a fabrication flow for forming isolation regions and finFETs in accordance with some embodiments.

Many different embodiments or examples for implementing the various features of the present disclosure are provided below. Specific examples of elements and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. example For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which the first feature and the second feature are formed in direct contact. Embodiments where additional features are formed between features such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or text in various instances. This repetition is for the purpose of simplicity and clarity, and in itself does not indicate a relationship between the various embodiments and/or configurations discussed.

What's more, spatially relative terms (eg, "below", "below", "below", "above", "above", etc. related terms) are used here to simply describe the elements shown in the figures or The relationship of a feature to another element or feature. In use or operation, these spatially relative terms encompass different orientations of elements in addition to the orientations depicted in the figures. Furthermore, these elements can be rotated (rotated 90 degrees or other angles) and the spatially relative descriptors used herein can be interpreted accordingly.

According to some embodiments, isolation regions for dicing fin and gate stacks, fin field effect transistors, and methods of forming the same are provided. According to some embodiments of the present disclosure, gate isolation regions and fin isolation regions are formed, then recessed, and a dielectric material is filled into the resulting recesses. Through this process, the gaps created in the gate isolation region and the fin isolation region can be sealed. According to some of the illustrated embodiments, the formation of a fin field effect transistor is used as an example to explain the concepts of the present disclosure. Other types of transistors (eg, planar transistors, Gate-All-Around (GAA) transistors, etc.) may also employ embodiments of the present disclosure to cut the corresponding active regions and gate stacks. The embodiments discussed in this disclosure will provide examples, to enable the making or use of the disclosed subject matter, and those of ordinary skill in the art will readily appreciate that various modifications can be made while remaining within the intended scope of the different embodiments. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Figures 1-4, 5A, 5B, 6, 7A, 7B, 8A, 8B, and 9-15 illustrate the formation according to some embodiments Perspective, cross-sectional, and top views of the isolation region and intermediate stage of the finFET. The corresponding process is also schematically reflected in the process flow shown in FIG. 17 .

Figure 1 shows a perspective view of the initial structure. The initial structure includes wafer 10 , wherein wafer 10 further includes substrate 20 . The substrate 20 may be a semiconductor substrate, and the semiconductor substrate may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type or n-type impurities. Isolation regions 22 (eg, Shallow Trench Isolation (STI) regions) may be formed extending into the substrate 20 from the top surface of the substrate 20 . The corresponding process is shown as step 202 in the manufacturing process 200 shown in FIG. 17 . The portions of substrate 20 between adjacent shallow trench isolation regions 22 are referred to as semiconductor strips 24 . According to some embodiments of the present disclosure, the semiconductor strips 24 are part of the original substrate 20 , so the material of the semiconductor strips 24 is the same as the material of the substrate 20 . According to other embodiments of the present disclosure, the semiconductor strips 24 are formed by etching a portion of the substrate 20 between the shallow trench isolation regions 22 to form grooves, and an epitaxial process is performed. A replacement bar formed by re-growing another semiconductor material in the groove. Thus, the semiconductor strips 24 are formed of a different semiconductor material than the substrate 20 . According to some embodiments, the semiconductor strips 24 are made of silicon (Si), silicon phosphorus (SiP), silicon carbon (SiC), silicon phosphorus carbon (SiPC), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium (Ge) , III-V compound semiconductors (eg, indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), indium arsenide (InAs), indium aluminum arsenide (InAlAs), indium gallium arsenide (InAlAs) (InGaAs) etc.).

The shallow trench isolation region 22 may include a pad oxide (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 20 . The pad oxide can also be a deposited silicon oxide layer formed using methods such as Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (High-Density Plasma Chemical Vapor Deposition) Vapor Deposition, HDPCVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), etc. The shallow trench isolation region 22 may also include a dielectric material over the pad oxide, which may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, or the like Dielectric material.

Figure 2 illustrates the formation of a dielectric dummy strip 25, which can be formed by etching one of the semiconductor strips 24 to form a recess, and then filling the recess with a dielectric material. The corresponding process is shown as step 204 in the manufacturing process 200 shown in FIG. 17 . The dielectric material can be made of a high-k dielectric material A material (eg, silicon nitride) is formed of or contains a high-k dielectric material. Additionally, the material of the dielectric dummy strips 25 is selected to have high etch selectivity relative to the material of the subsequently formed dummy gate stack and the material of the shallow trench isolation region 22 (eg, silicon oxide). The bottom surfaces of the dielectric dummy bars 25 may be higher, flush, or lower than the bottom surfaces of the shallow trench isolation regions 22 .

Referring to FIG. 3, the shallow trench isolation region 22 is recessed. The tops of the semiconductor strips 24 and the dielectric dummy strips 25 protrude above the top surface 22A of the remaining portion of the shallow trench isolation region 22 to form the protruding fins 24' and the dummy fins 25', respectively. The corresponding process is shown as step 206 in the manufacturing process 200 shown in FIG. 17 . The etching may be performed using a dry etching process, wherein an etching gas such as a mixture of (HF ₃ ) and ammonia (NH ₃ ) may be used. According to other embodiments of the present disclosure, the recessing of the shallow trench isolation regions 22 is performed using a wet etch process. The etching chemistry may include, for example, a hydrofluoric acid (HF) solution.

In the above-described embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithographic processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing, for example, to produce patterns with smaller pitches than would be obtainable using a single, direct lithography method. For example, in some embodiments, a sacrificial layer is formed over the substrate and patterned using a photolithographic process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the fins can then be patterned using the remaining spacers or mandrels.

With further reference to Figure 3, at (protruding) fins 24' and dummy Dummy gate stacks 30 and gate spacers are formed on top surfaces and sidewalls of fins 25'. The corresponding process is shown as step 208 in the manufacturing process 200 shown in FIG. 17 . Dummy gate stack 30 may include dummy gate dielectric 32 and dummy gate electrode 34 over dummy gate dielectric 32 . For example, the dummy gate electrode 34 may be formed using polysilicon or amorphous silicon or using other materials. Each dummy gate stack 30 may also include one (or more) hard mask layer 36 over the dummy gate electrode 34 . The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. Dummy gate stack 30 may span single or multiple protruding fins 24 ′ and dummy fins 25 ′ and/or shallow trench isolation regions 22 . The length direction of the dummy gate stack 30 is perpendicular to the length direction of the protruding fins 24 ′ and the dummy fins 25 ′.

Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30 . According to some embodiments of the present disclosure, the gate spacer 38 is made of a dielectric material (eg, silicon nitride (SiN), silicon oxide ( _SiO2 ), silicon carbonitride (SiCN), silicon oxynitride (SiON) , silicon oxycarbonitride (SiOCN), etc.), and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The width of gate spacers 38 may range between about 1 nanometer and about 3 nanometers.

According to some embodiments of the present disclosure, an etch process (hereinafter referred to as source/drain recess) is performed to etch the portion of the protruding fin 24' not covered by the dummy gate stack 30 and gate spacer 38, resulting in The structure shown in Figure 4. The corresponding process is shown as step 210 in the manufacturing process 200 shown in FIG. 17 . This recessing process may be anisotropic, so that the portion of the protruding fin 24' located directly below the dummy gate stack 30 and gate spacer 38 is protected and not etched. According to some embodiments, the top surfaces of the recessed semiconductor strips 24 may be lower than the top surfaces 22A of the shallow trench isolation regions 22 . The space left by the etched portion of the protruding fin 24 ′ is called a groove 40 . During the etching process, the dielectric dummy fins 25' are not etched. For example, a mixture of nitrogen trifluoride (NF ₃ ) and ammonia (NH ₃ ), a mixture of hydrofluoric acid (HF) and ammonia (NH ₃ ), or the like may be used to etch the protruding fins 24 ′.

Next, epitaxial regions (source/drain regions) 42 are formed by selectively growing semiconductor material from the recesses 40, resulting in the structure of FIG. 5A. The corresponding process is shown as step 212 in the manufacturing process 200 shown in FIG. 17 . According to some embodiments, the epitaxial region 42 includes silicon germanium, silicon, silicon carbon, or the like. Depending on whether the resulting finFET is a p-type or n-type finFET, p-type or n-type impurities can be doped in-situ as epitaxy proceeds. For example, when the resulting fin field effect transistor is a p-type fin field effect transistor, silicon germanium boron (SiGeB), silicon boron (SiB), germanium boron (GeB), etc. may be grown. Conversely, when the resulting fin field effect transistor is an n-type fin field effect transistor, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), and the like may be grown. According to other embodiments of the present disclosure, the epitaxial region 42 is formed of a III-V compound semiconductor (eg, gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), indium gallium arsenide (InGaAs) , indium aluminum arsenide (InAlAs), gallium antimonide (GaSb), aluminum antimonide (AlSb), aluminum arsenide (AlAs), aluminum phosphide (AlP), gallium phosphide (GaP), combinations or layers thereof )form. After the epitaxial region 42 completely fills the groove 40, the epitaxial region 42 begins to expand horizontally, And a facet can be formed.

FIG. 5B illustrates the formation of source/drain regions 42 in accordance with other embodiments of the present disclosure. According to these embodiments, the protruding fins 24' as shown in FIG. 4 are not recessed, and the epitaxial regions 41 are grown on the protruding fins 24'. Depending on whether the resulting finFET is p-type or n-type finFET, the material of epitaxial region 41 may be similar to that of epitaxial region 42 shown in FIG. 5A. Accordingly, source/drain regions 42 include protruding fins 24 ′ and epitaxial regions 41 . The implantation process may (or may not) be performed to implant n-type impurities or p-type impurities.

FIG. 6 is a perspective view of the structure after forming a Contact Etch Stop Layer (CESL) 46 and an Inter-Layer Dielectric (ILD) 48 . The corresponding process is shown as step 214 in the manufacturing process 200 shown in FIG. 17 . Contact etch stop layer 46 may be formed of silicon nitride, silicon carbonitride, or the like. For example, contact etch stop layer 46 may be formed using conformal deposition methods such as atomic layer deposition or chemical vapor deposition. The interlayer dielectric layer 48 may comprise a dielectric material formed using methods such as flowable chemical vapor deposition, spin coating, chemical vapor deposition, or other deposition methods. The interlayer dielectric layer 48 may also be made of an oxygen-containing dielectric material, which may be a silicon oxide-based material (eg, silicon oxide, Phospho-Silicate Glass (PSG), borosilicate glass) Salt glass (Boro-Silicate Glass, BSG), boron-doped phosphosilicate glass (Boron-Doped Phospho-Silicate Glass, BPSG), etc.). perform tasks such as chemical mechanical planarization A planarization process such as a Polish, CMP) process or a mechanical polishing process to make the top surfaces of the interlayer dielectric layer 48 , the dummy gate stack 30 and the gate spacer 38 flush with each other.

7A shows a plan view (top view) of a portion of wafer 10 after forming gate isolation regions 50, which are sometimes referred to as cut-poly (CPO) regions. The corresponding process is shown as step 216 in the manufacturing process 200 shown in FIG. 17 . The corresponding process may also be referred to as a dicing polysilicon process. Protruding fins 24', dielectric dummy fins 25', dummy gate stacks 30, and gate spacers 38 are shown. The protruding fins 24 ′ may be directly below the dummy gate stacks 30 , and the source/drain regions 42 are formed between the dummy gate stacks 30 . It will be appreciated that source/drain regions 42 grown from adjacent protruding fins 24' may be merged (not shown in Figure 7A for clarity). The protruding fins 24' are elongated strips having a length in the X direction. The dummy gate stack 30 is a long strip with a length in the Y direction.

Figure 7B shows a cross-sectional view obtained from reference cross-section 7B-7B in Figure 7A. The gate isolation region 50 is formed to divide the long dummy gate stack 30 into shorter sections so that the shorter dummy gate stack 30 can serve as a dummy gate stack for different finFETs. It should be appreciated that in the example embodiment shown, the gate isolation region 50 is formed prior to forming the replacement gate stack. In other embodiments, the gate isolation region 50 may also be formed after the replacement gate stack is formed, and thus the replacement gate stack is cut by the gate isolation region 50 . According to some embodiments, the formation of the gate isolation region 50 includes forming an etch mask (eg, a patterned photoresist), The region where gate isolation region 50 (FIG. 7A) is to be formed is exposed through openings in the etch mask. The opening in the etch mask is directly above a portion of the dummy fin 25'. Then, the portion of the dummy gate stack 30 exposed through the etch mask is etched. As can be seen in Figure 7B, the etching can be stopped after exposing the dummy fins 25'. Next, the etch mask is removed, and a dielectric material is deposited to fill the openings in the dummy gate stack 30 .

According to some embodiments, the deposition of the dielectric material is performed using a conformal deposition method such as atomic layer deposition, which may be Plasma-Enhanc Atomic Layer Deposition (PEALD), thermal atomic layer deposition deposition, etc. The dielectric material may be formed of silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), etc., or a combination thereof, or include silicon nitride (SiN), oxide Silicon (SiO ₂ ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), etc. According to some embodiments, the dielectric material includes silicon nitride (SiN), and the deposition is performed using a process gas including dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). Hydrogen (H ₂ ) can also be added. The deposition process may be performed at a temperature between about 450°C and about 650°C using plasma enhanced atomic layer deposition. After the deposition process, a planarization process such as a chemical mechanical planarization process or a mechanical polishing process is performed. The remainder of the dielectric material is the gate isolation region 50 . The slit 51 may be formed in the middle of the gate isolation region (as shown in FIGS. 7A and 7B ). The width of the slit 51 may be in a range between about 0.5 nanometers and about 2 nanometers.

FIG. 8A shows a plan view of forming the fin isolation region 54, the fin Die isolation region 54 is sometimes referred to as a Cut-Poly on OD Edge (CPODE) region. The corresponding process is shown as step 218 in the manufacturing process 200 shown in FIG. 17 . The corresponding process may also be referred to as a CPODE process. The fin isolation region 54 divides the long protruding fins 24' into a plurality of shorter sections so that the plurality of shorter protruding fins 24' can serve as active regions for different finFETs (eg, aisle). Fin isolation regions 54 may also separate the source/drain regions of adjacent FinFETs from each other.

Figure 8B shows a cross-sectional view obtained from reference cross-section 8B-8B in Figure 8A. According to some embodiments, forming the fin isolation region 54 includes forming an etch mask and using the etch mask to etch the dummy gate stack 30 . In the etching process, the dummy gate stack 30 is first etched anisotropically until the underlying protruding fins 24' are exposed. Etching may be stopped on shallow trench isolation regions 22 . The protruding fins 24 ′ are then etched, and the etching continues down into the underlying semiconductor strips 24 , and further down into the bulk portion of the underlying semiconductor substrate 20 . The shallow trench isolation regions 22 serve as etch masks to define the pattern of openings formed. Next, a dielectric material is deposited into the openings formed by the etching process, followed by a planarization process to remove excess portions of the dielectric material. The remaining dielectric material forms fin isolation regions 54 .

According to some embodiments, a dielectric mask 52 is formed (before or after the fin isolation regions 54 are formed) to protect the interlayer dielectric layer 48 . Formation of the dielectric mask 52 may include recessing the interlayer dielectric layer 48 and filling the formed recesses with a dielectric material. The dielectric mask 52 may be formed of silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), etc. or include silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), etc. The material of the dielectric mask 52 may be the same as or different from the material of the fin isolation regions 54 .

According to some embodiments, deposition of the dielectric material of isolation regions 54 is performed using a conformal deposition process such as atomic layer deposition, which may be plasma enhanced atomic layer deposition, thermal atomic layer deposition, or the like. The dielectric material may be formed of silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), etc., or a combination thereof, or include silicon nitride (SiN), oxide Silicon (SiO ₂ ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN). The fin isolation region 54 may be formed of a homogeneous material, or may have a composite structure comprising more than one layer. For example, FIG. 8B shows that the fin isolation region 54 may include a dielectric liner 54', which may be formed of, for example, silicon oxide. According to some embodiments, the dielectric material of the isolation region 54 includes silicon nitride (SiN), and the deposition is performed using a process gas including dichlorosilane and ammonia. Hydrogen ( _H2 ) may or may not be added. The deposition process may be performed at a temperature between about 450°C and about 650°C using plasma enhanced atomic layer deposition. As shown in FIGS. 8A and 8B , the slit 55 may be formed in the middle of the fin isolation region 54 . The width of the slit 55 may be in a range between about 0.5 nanometers and about 2 nanometers. In FIG. 8B, the top surface 22A and bottom surface 22B of the shallow trench isolation region are labeled to illustrate where the shallow trench isolation region 22 is.

FIGS. 9 and 10 illustrate the formation of the alternate gate stack 62 . Dummy gate stack 30 is removed by etching (shown in FIG. 8B ), and trenches 56 are formed (shown in FIG. 9 ). The corresponding process is shown as step 220 in the manufacturing process 200 shown in FIG. 17 . Next, as shown in FIG. 10 , a (alternative) gate stack 62 is formed, which includes gate dielectric layer 58 and gate electrode 60 . The corresponding process is shown as step 222 in the manufacturing process 200 shown in FIG. 17 . Formation of the gate stack 62 includes forming/depositing multiple layers and then performing a planarization process such as a chemical mechanical planarization process or a mechanical polishing process. According to some embodiments of the present disclosure, each gate dielectric layer 58 includes an interface layer (IL) as its lower portion. An interface layer is formed on the exposed surfaces of the protruding fins 24'. The interface layer may include an oxide layer (eg, a silicon oxide layer) formed by oxidizing the surface layer of each protruding fin 24' through a thermal oxidation process or a chemical oxidation process, or by a deposition process. Each of the gate dielectric layers 58 may also include a high-k dielectric layer formed over the interface layer. The high-k dielectric layer may include a high-k dielectric material (eg, hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), zirconium hafnium oxide (HfZrO _x ), hafnium silicon oxide (HfSiO _x ) ), hafnium silicon oxynitride (HfSiON), zirconium silicon oxide (ZrSiO _x ), hafnium silicon zirconium oxide (HfZrSiO _x ), aluminum oxide (Al ₂ O ₃ ), hafnium aluminum oxide (HfAlO _x ), hafnium aluminum nitride (HfAlN) ), aluminum oxide zirconium (ZrAlO _x ), lanthanum oxide (La ₂ O ₃ ), titanium oxide (TiO ₂ ), ytterbium oxide (Yb ₂ O ₃ ), silicon nitride, etc.). The dielectric constant (k value) of high-k dielectric materials is higher than 3.9, and may be higher than about 7.0. The high-k dielectric layer may be formed as a conformal layer and extend over the sidewalls of the protruding fins 24 ′ and the sidewalls of the gate spacers 38 . The gate dielectric layer 58 also extends over the top surface and sidewalls of certain portions of the dielectric dummy fins 25', however if the interfacial layer is formed by thermal oxidation, then over the dielectric dummy fins 25' An interfacial layer may not be formed. According to some embodiments of the present disclosure, the high-k dielectric layer in gate dielectric layer 58 is formed using atomic layer deposition, chemical vapor deposition, or the like.

Gate electrode 60 is formed on top of gate dielectric layer 58 and fills the remainder of the trench left by the removed dummy gate stack. The sub-layers in the gate electrode 60 are not individually shown in the figures, however, they can be distinguished from each other due to the different compositions of the sub-layers. The deposition of at least the lower portion of the sublayers may be performed using a conformal deposition method such as atomic layer deposition or chemical vapor deposition such that the thickness of the vertical portion and the thickness of the horizontal portion of the gate electrode 60 (and each sublayer) are are substantially equal to each other.

Sublayers in gate electrode 60 may include, but are not limited to, titanium silicon nitride (TiSN) layers, tantalum nitride (TaN) layers, titanium nitride (TiN) layers, titanium aluminum (TiAl) layers, additional titanium nitride layers (TiN) and/or tantalum nitride (TaN) layers and fill metal regions. Hereinafter, the gate electrode 60 is referred to as a metal gate 60 . Some of these sublayers define the work function of the respective finFET. In addition, the metal layer of the p-type finFET and the metal layer of the n-type finFET may be different from each other, so that the work function of the metal layer is suitable for the corresponding p-type or n-type finFET. The filler metal may contain tungsten, cobalt, or the like.

FIG. 11 shows that the replacement gate stack 62 is recessed, such as by an etch process, thus again forming the top of the trench 56 . The corresponding process is shown as step 224 in the manufacturing process 200 shown in FIG. 17 .

Next, as shown in FIG. 12, a dielectric hard mask 66, sometimes referred to as a Self-Aligned Contact (SAC) fill layer 66, is formed. The corresponding process is shown as step 226 in the manufacturing process 200 shown in FIG. 17 . The dielectric hard mask 66 may be formed of silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), etc., or a combination thereof, or include silicon nitride (SiN) ), silicon oxide (SiO ₂ ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), etc. According to some embodiments, the dielectric material includes silicon nitride (SiN) and is deposited by plasma enhanced atomic layer deposition using a process gas including dichlorosilane and ammonia. Hydrogen ( _H2 ) may or may not be added. The deposition process may be performed at a temperature between about 350°C and about 550°C using plasma enhanced atomic layer deposition. After the deposition process, a planarization process is performed. The remainder of the dielectric material is the dielectric hard mask 66 . A slit 67 may be formed. The width of the slit 67 may range between about 0.5 nanometers and about 2 nanometers. When viewed in a top view of wafer 10 as shown in FIG. 8A , dielectric hard mask 66 is located at the same location as dummy gate stack 30 as shown, and slot 67 is located on the opposite side of dummy gate stack 30 on the middle between the gate spacers 38 .

Process conditions such as temperature, deposition rate, etc. can be adjusted to make the dielectric hard mask 66, the fin isolation region 54 and the gate isolation region 50 different from each other. For example, according to some embodiments, the density of fin isolation regions 54 may be higher than the density of dielectric hard mask 66 , and the density of dielectric hard mask 66 may be further higher than the density of gate isolation regions 50 .

Referring to Figure 13, make the dielectric hard mask 66 and the fin isolation region Domains 54 are recessed to form grooves 68A and 68B, respectively (collectively, grooves 68). The corresponding process is shown as step 228 in the manufacturing process 200 shown in FIG. 17 . Gate isolation regions 50 that are not in the plane shown may also be recessed. The dielectric mask 52 may be removed through a recess process. According to some embodiments, the recessing of the dielectric hard mask 66 and the fin isolation regions 54 is performed in a common etch process. According to other embodiments, the recessing of the dielectric hard mask 66 and the recessing of the fin isolation regions 54 are performed in different etch processes. According to some embodiments, the pad 54' is not recessed. According to other embodiments, the pad 54' is recessed, eg, line 54'S depicts a possible location of the top surface of the pad 54' when the pad 54' is recessed.

According to some embodiments, the bottom of the fin isolation region 54 is at a controlled height (eg, at a lower height than the dashed line 57 ), wherein the distance D1 between the dashed line 57 and the top surface of the protruding fin 24 ′ is made less than about 50 nm or less than about 20 nm. The bottom of recess 68A may also be located lower than the top surface of replacement gate stack 62, between (or flush with) the top surface of replacement gate stack 62 and the top surface of protruding fin 24', or Any height below the top surface of the protruding fins 24'. The fin isolation regions 54 may be recessed below the dielectric hard mask 66 . Grooves 68A may also be deeper than grooves 68B. After recessing, gaps 55 and 67 may still be present.

The etching process may include a wet etching process or a dry etching process. For example, when a dry etching process is used, the etching gas may use a gas containing carbon and fluorine (C _x F _y -based) (eg, carbon tetrafluoride (CF ₄ )), ethane (C ₂ H ₆ ), and the like. The temperature may range between about 25°C to about 300°C. Etch durations may range between about 5 seconds to about 300 seconds. When a wet etching process is used, phosphoric acid (H ₃ PO ₄ ) can be used. In etching, the temperature may range between about 150°C to about 200°C. Etch durations may range between about 50 seconds to about 2,000 seconds. The desired depth of the grooves 68 can be controlled by controlling the etching time. According to some embodiments, the etch rate of fin isolation regions 54 may be greater than the etch rate of dielectric hard mask 66 , and the etch rate of dielectric hard mask 66 may be further greater than the etch rate of gate isolation regions 50 .

During the etching process, the interlayer dielectric layer 48 and the gate spacer 38 are not intended to be etched. For example, the etch selectivity ER _50-54-66 /ER ₄₈ and the etch selectivity ER _50-54-66 /ER ₃₈ can be greater than about 10, where ER ₄₈ is the etch rate of the interlayer dielectric 48 and ER ₃₈ is the gate The etch rate of spacer 38 , and ER 50 - 54 - 66 are the _etch rates of gate isolation region 50 , fin isolation region 54 , and dielectric hard mask 66 . Therefore, typically the interlayer dielectric layer 48 and gate spacer 38 are not etched. However, as the dielectric hard mask 66 is recessed, it may also occur that the gate spacers 38 are etched from the sidewalls thereof, and since the gate spacers 38 are thin, in some embodiments, the gate spacers 38 are thin. Spacers 38 are also recessed. In these embodiments, the top surface of the recessed gate spacer 38 may be depicted as 38TS, which is lower than the top surface of the interlayer dielectric layer 48 . The top surface 38TS may be inclined. The gate spacers 38 on opposite sides of the alternate gate stack 62 may be symmetrical or may be asymmetrical.

FIG. 14 illustrates the formation of dielectric regions 70A and 70B (collectively referred to as dielectric regions 70). The corresponding process is shown as step 230 in the manufacturing process 200 shown in FIG. 17 . In addition, the slits 71A and 71B (generally Referred to as slits 71), are formed in dielectric regions 70A and 70B, respectively. Meanwhile, a dielectric region ( 70C, FIGS. 16A and 16B ) is formed on top of the recessed gate isolation region 50 , and the dielectric region 70C and the underlying gate isolation region 50 may have the same Substance region 70B and dielectric hard mask 66 have similar profiles. Dielectric regions 70A, 70B, and 70C may be formed in a common deposition process, which may include a conformal deposition process such as atomic layer deposition or chemical vapor deposition, followed by a common planarization process. Dielectric region 70A and the remaining fin isolation region 54 below combine to form isolation region 75 .

The widths of slits 71A and 71B may range between about 0.5 nanometers and about 2 nanometers. According to some embodiments, the dielectric region 70 is formed of materials such as silicon nitride (SiN), silicon oxide ( _SiO2 ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), the like, or a combination thereof, or includes nitrogen Silicon oxide (SiN), silicon oxide (SiO ₂ ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN). Furthermore, the material of dielectric region 70 may be the same or different from the material of underlying dielectric hard mask 66 , gate isolation region 50 and/or fin isolation region 54 . The interface between dielectric region 70 and underlying dielectric hardmask 66, gate isolation region 50, and fin isolation region 54 (eg, 54S and 66S as indicated) may be distinguishable or may be Indistinguishable (eg, distinguishable or indistinguishable in a Transmission Electron Microscopy (TEM image)), whether they are formed from the same material or from different materials. For example, when dielectric hard mask 66 , gate isolation region 50 and fin isolation region 54 are formed of silicon nitride (SiN), dielectric hard mask 66 , gate isolation region 50 and fin isolation region The surface layer of 54 can be oxidized in natural oxidation to form a thin silicon oxynitride (SiON) interface layer. Figure 14 depicts exemplary interface layers, also labeled 66S and 54S. According to some embodiments, the interface layers 66S and 54S have a U-shape in cross-sectional view.

As shown in FIG. 14, the bottom portion of the dielectric region 70A separates the upper slit 71A from the lower slit 55. The bottom bit of the dielectric region 70B separates the corresponding upper slit 71B from the corresponding lower slit 67 . The width W1 of the bottom bit of the dielectric region 70A may be in the range of about 12 nm to about 16 nm, and the width W1 may be significantly larger than the width W2 (the width W2 may be in the range of about 0.5 nm to about 2 nm). range between). The height H1 of the bottom bit of the dielectric region 70A may be in a range between about 5 nanometers and about 20 nanometers.

Figure 15 illustrates the formation of additional features of a finFET. The corresponding process is shown as step 232 in the manufacturing process 200 shown in FIG. 17 . For example, gate contact plug 74 is formed over and in contact with gate electrode 60 . Source/drain silicide regions 76 and source/drain contact plugs 78 are formed to electrically connect to source/drain regions 42 . Thus, fin field effect transistors 80A and 80B are formed. It will be appreciated that the top bits of dielectric regions 70A and 70B may be removed, for example, during the planarization and etch processes used to form gate contact plugs 74 and source/drain contact plugs 78 . Gap 71B may be completely removed along with the top bits of the corresponding dielectric region 70B, while gap 71A may be shortened.

FIG. 16A depicts a portion of wafer 10 in accordance with some embodiments Top view of points. In FIG. 16A, some gate contact plugs 74 and source/drain contact plugs 78 are shown, however more gate contact plugs and source/drain contact plugs may be formed. Dielectric regions 70A and 70B as shown in FIG. 15 are shown in FIG. 16A. In addition, dielectric region 70C is shown formed in the same deposition process as dielectric regions 70A and 70B. It should be understood that in top view, the dielectric regions 70A, 70B and 70C may form continuous regions with no distinguishable interface between them. In other words, when viewed from the top of wafer 10, there are no distinguishable interfaces between dielectric regions 70A, 70B, and 70C formed by the same process. Therefore, there is no distinguishable interface in region 73 . According to other embodiments, the dielectric region 70C may be completely removed in the process shown in FIG. 15, thus, in FIGS. 16A and 16B, the dielectric region 70C is not left behind. Instead, the gate isolation region 50 will be visible.

Figure 16B shows a perspective view of the area 84 in Figure 16A. In the illustrated embodiment, portions of fin isolation region 54 over shallow trench isolation region 22 and dielectric region 70A over fin isolation region 54 are shown in perspective view, and slits 67 and 71A is also depicted. In other embodiments, fin isolation region 54 is not visible in FIG. 16B because dielectric region 70A extends to the top surface of shallow trench isolation region 22 . Dielectric regions 70B and 70C are also shown in the figure.

Embodiments of the present disclosure have several features. By recessing the gate isolation regions, fin isolation regions, and dielectric hardmask, additional dielectric regions can be formed in the resulting recesses. The gaps in the gate isolation region, the fin isolation region and the dielectric hard mask can be sealed. Otherwise, long seams The gap may be divided into shorter upper and lower parts. This reduces problems caused by gaps.

According to some embodiments of the present disclosure, a method includes: forming a semiconductor fin projecting above a top surface of an isolation region, wherein the isolation region extends into a semiconductor substrate; and etching a portion of the semiconductor fin to form a trench, wherein the trench extends below the bottom surface of the isolation region and into the semiconductor substrate; fills the trench with a first dielectric material to form a first fin isolation region; isolates the first fin The region is recessed to form a first recess; the first recess is filled with a second dielectric material, wherein the first dielectric material and the second dielectric material combine to form a second fin isolation region. In some embodiments, the first dielectric material includes a first slit, and the second dielectric material includes a second slit overlapping the first slit. In some embodiments, the method further includes removing the top bits of the second dielectric material including the second slits, wherein the bottom bits of the second dielectric material without the second slits remain. In some embodiments, the first dielectric material is the same as the second dielectric material. In some embodiments, the method further includes forming a gate stack on the semiconductor fin; and forming a gate isolation region to divide the gate stack into a first portion and a second portion, wherein when the first fin isolation region is recessed , the gate isolation region is also recessed to form a second recess, and the second recess is filled with a second dielectric material. In some embodiments, the method further includes forming a replacement gate stack on the semiconductor fin; recessing the replacement gate stack; and forming a dielectric hard mask over the replacement gate stack and connecting the replacement gate stack with the dielectric A hard mask contact, wherein when the first fin isolation region is recessed, the dielectric hard mask is recessed to form an attached The additional grooves are filled, and the second dielectric material is filled into the additional grooves. In some embodiments, after the first fin isolation region is recessed, the top surface of the remaining portion of the first fin isolation region is lower than another top surface of the semiconductor fin.

According to some embodiments of the present disclosure, an element includes a semiconductor substrate; an isolation region extends into the semiconductor substrate; and a dielectric region extends from a first height above a top surface of the isolation region to a height below a bottom surface of the isolation region a second height, wherein the dielectric region includes a lower portion having a first slit therein; and an upper portion having a second slit therein, wherein the first slit penetrates a bottom portion of the upper portion of the dielectric region and the second slit spaced apart. In some embodiments, there is a distinguishable interface between the lower portion and the upper portion. In some embodiments, the lower portion and the upper portion are formed of the same material, and the distinguishable interface comprises an interfacial layer, and the interfacial layer comprises the same material and oxygen. In some embodiments, the second slit overlaps the first slit. In some embodiments, the method further includes a first protruding semiconductor fin and a second protruding semiconductor fin having lengthwise aligned with the same line, wherein the dielectric region connects the first protruding semiconductor fin to the The second protruding semiconductor fins are separated. In some embodiments, the device further includes a first finFET including a first protruding semiconductor fin and a first source/drain region, wherein the first source/drain a drain region between the first protruding semiconductor fin and the dielectric region; and a second finFET including a second protruding semiconductor fin and a second source/drain region, wherein the second source The /drain region is between the second protruding semiconductor fin and the dielectric region. In some embodiments, this element further includes a gate stack contained on the first protruding semiconductor fin; and a dielectric hard mask over the gate stack including an additional lower portion having a third slit therein; and over the additional lower portion and The additional upper part with which it comes into contact. In some embodiments, the additional upper portion has no gaps.

According to some embodiments of the present disclosure, an element includes a substrate; an isolation region extending into the substrate; a semiconductor fin extending upwardly from a top surface of the isolation region; a first epitaxial semiconductor region extending into the semiconductor fin, and a second epitaxial semiconductor region; a first dielectric region laterally between the first epitaxial semiconductor region and the second epitaxial semiconductor region; and a second dielectric region over the first dielectric region, Wherein the second dielectric region includes a U-shaped bottom site in contact with the top surface of the first dielectric region. In some embodiments, the first dielectric region and the second dielectric region comprise the same dielectric material. In some embodiments, the first dielectric region and the second dielectric region include a first slit and a second slit, respectively, and the first slit is separated from the second slit by a portion of the second dielectric region. In some embodiments, the first slit extends to the bottom of the U-shape. In some embodiments, the bottom surface of the second dielectric region is lower than the other top surface of the first epitaxial semiconductor region.

The foregoing has outlined features of several embodiments so that those of ordinary skill in the art may better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same benefits of the embodiments described herein. It should also be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, And they can be made various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

10: Wafer

20: Substrate

22A: Top surface

22B: Bottom surface

24': Protruding fins

42: Epitaxy area

46: Contact etch stop layer

48: Interlayer dielectric layer

54: Fin isolation area

54S: Interface layer

55: Gap

58: gate dielectric layer

60: Gate electrode

62: Gate stack

66: Dielectric hard mask

67: Gap

70A: Dielectric area

70B: Dielectric region

71A: Gap

74: Gate contact plug

75: Quarantine area

76: source/drain silicide region

78: source/drain contact plug

80A: Fin Field Effect Transistor

80B: Fin Field Effect Transistor

Claims (10)

A method of manufacturing a semiconductor device, comprising: forming a semiconductor fin protruding above a plurality of top surfaces of a plurality of isolation regions, wherein the isolation regions extend into a semiconductor substrate; etching a portion of the semiconductor fin to form a trench, wherein the trench extends below the bottom surfaces of the isolation regions and into the semiconductor substrate; filling the trench with a first dielectric material to form a first fin isolation region; recessing the first fin isolation region to form a first groove; and filling the first groove with a second dielectric material, wherein the first dielectric material and the second dielectric The materials combine to form a second fin isolation region. The method of claim 1, wherein the first dielectric material includes a first slit, and the second dielectric material includes a second slit overlapping the first slit. The method of claim 1, further comprising: forming a gate stack on the semiconductor fin; and forming a gate isolation region to divide the gate stack into a first portion and a second portion, wherein when the first portion When a fin isolation region is recessed, the gate isolation region is also recessed to form a second groove, and the second dielectric material is filled into the second groove. The method of claim 1, wherein after recessing the first fin isolation region, a top surface of a remaining portion of the first fin isolation region is lower than another top surface of the semiconductor fin. A semiconductor element, comprising: a semiconductor substrate; a plurality of isolation regions extending into the semiconductor substrate; and a dielectric region including: a lower portion having a first slit in the lower portion; and an upper portion a portion having a second slit in the upper portion, wherein the first slit is spaced apart from the second slit through a bottom portion of the upper portion of the dielectric region, and the upper portion of the dielectric region The first slit in the dielectric region overlaps the second slit in the lower portion of the dielectric region. The semiconductor device of claim 5, wherein a distinguishable interface is provided between the lower portion and the upper portion. The semiconductor device according to claim 5, further comprising: a first protruding semiconductor fin and a second protruding semiconductor fin, the lengths of the first protruding semiconductor fin and the second protruding semiconductor fin The directions are aligned on the same line, wherein the dielectric region separates the first protruding semiconductor fin from the second protruding semiconductor fin. A semiconductor device, comprising: a substrate; a plurality of isolation regions extending into the substrate; a semiconductor fin extending upward from a plurality of top surfaces of the isolation regions; a first epitaxial semiconductor region and a first Two epitaxial semiconductor regions extending into the semiconductor fin; a first dielectric region laterally between the first epitaxial semiconductor region and the second epitaxial semiconductor region; and a second dielectric region region, on the first dielectric region, wherein the second dielectric region includes a U-shaped bottom site in contact with a top surface of the first dielectric region. The semiconductor device of claim 8, wherein the first dielectric region and the second dielectric region comprise a same dielectric material. The semiconductor device according to claim 8, wherein the first dielectric region and the second dielectric region respectively comprise a first slit and a second slit, and the first slit and the second slit pass through A portion of the second dielectric region is spaced apart.

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