CN110783197A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN110783197A
CN110783197A CN201910485262.4A CN201910485262A CN110783197A CN 110783197 A CN110783197 A CN 110783197A CN 201910485262 A CN201910485262 A CN 201910485262A CN 110783197 A CN110783197 A CN 110783197A
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dummy
dummy gate
dielectric layer
gate
layer
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CN110783197B (zh
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余德伟
赵晟博
邓运桢
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

公开了半导体装置的制造方法及通过此方法形成的半导体装置。在一实施例中，半导体装置的制造方法包含在从基底延伸出的鳍部上沉积虚设介电层；在虚设介电层上沉积虚设栅极晶种层；将虚设栅极晶种层回焊；蚀刻虚设栅极晶种层；以及在虚设栅极晶种层上方选择性地沉积虚设栅极材料，虚设栅极材料和虚设栅极晶种层构成虚设栅极。

Description

半导体装置及其制造方法
技术领域
本发明实施例有关于半导体技术，且特别是有关于半导体装置及其制造方法。
背景技术
半导体装置用于各式各样的电子应用中，例如个人电脑、手机、数码相机和其他电子设备。半导体装置一般通过在半导体基底上依序地沉积绝缘层或介电层、导电层和半导体层材料，并使用光刻(微影)技术将各种材料层图案化，以在其上形成电路组件和元件。
半导体工业通过持续降低最小部件(feature，特征)的尺寸，持续改善各种电子器件(例如晶体管、二极管、电阻、电容等)的集成密度，使得更多的器件集成于既定面积中。然而，当降低最小部件的尺寸，出现了应解决的附加问题。
发明内容
在一些实施例中，提供半导体装置的制造方法，此方法包含：在从基底延伸出的鳍部上沉积虚设介电层；在虚设介电层上沉积虚设栅极晶种层；将虚设栅极晶种层回焊；蚀刻虚设栅极晶种层；以及在虚设栅极晶种层上方选择性地沉积虚设栅极材料，其中虚设栅极材料和虚设栅极晶种层构成虚设栅极。
在一些其他实施例中，提供半导体装置的制造方法，此方法包含：在从基底延伸出的鳍部上沉积虚设介电层；在虚设介电层上沉积第一虚设栅极材料；将第一虚设栅极材料回焊；蚀刻第一虚设栅极材料和虚设介电层，其中蚀刻虚设介电层之后，形成具有末端基的(terminated)虚设介电层；以及在第一虚设栅极材料上方沉积第二虚设栅极材料以形成虚设栅极，其中第二虚设栅极材料选择性地沉积于第一虚设栅极材料上。
在另外一些实施例中，提供半导体装置，该半导体装置包含：栅极堆叠，位于半导体基底上方；栅极间隙壁，设置于栅极堆叠的侧壁上；以及介电层，设置于半导体基底与栅极间隙壁之间，介电层包含卤素末端表面(halogen-terminated surface)。
附图说明
根据以下的详细说明并配合附图可以更加理解本发明实施例。应注意的是，根据本产业的标准惯例，图示中的各种部件(feature)并非必然按照比例绘制。事实上，可能任意的放大或缩小各种部件的尺寸，以做清楚的说明。
图1显示依据一些实施例的鳍式场效晶体管(Fin Field-Effect Transistor，FinFET)的范例的三维视图。
图2、图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14A、图14B、图15A、图15B、图16A、图16B、图16C、图16D、图17A、图17B、图18A、图18B、图19A、图19B、图20A、图20B、图21A、图21B、图22A、图22B和图23为依据一些实施例的制造鳍式场效晶体管的中间阶段的剖面示意图。
【附图标记说明】
50 基底
50A 第一区
50B 第二区
51 分隔线
52、58 鳍部
54 绝缘材料
56 隔离区
60 虚设介电层
61 卤素末端虚设介电层
62 虚设栅极层
63 虚设栅极材料
63’ 附加虚设栅极材料
64 遮罩层
72 虚设栅极
74 遮罩
80 栅极密封间隙壁
82 外延源极/漏极区
86 栅极间隙壁
88、108 层间介电层
90 凹口
92 栅极介电层
93 功函数层
94 栅极电极
110 栅极接点
112 源极/漏极接点
H1、H2、H3 高度
T1、T2、T3 厚度
具体实施方式
要了解的是以下的公开内容提供许多不同的实施例或范例，以实施提供的主体的不同部件。以下叙述各个构件及其排列方式的特定范例，以求简化公开内容的说明。当然，这些仅为范例并非用以限定本发明。例如，以下的公开内容叙述了将一第一部件形成于一第二部件之上或上方，即表示其包含了所形成的上述第一部件与上述第二部件是直接接触的实施例，亦包含了尚可将附加的部件形成于上述第一部件与上述第二部件之间，而使上述第一部件与上述第二部件可能并未直接接触的实施例。此外，公开内容中不同范例可能使用重复的参考符号(附图标记)及/或用字。这些重复符号或用字是为了简化与清晰的目的，并非用以限定各个实施例及/或所述外观结构之间的关系。
再者，为了方便描述图中一元件或部件与另一(多个)元件或(多个)部件的关系，可使用空间相关用语，例如“在……之下”、“下方”、“下部”、“上方”、“上部”及类似的用语。除了附图所绘示的方位之外，空间相关用语也涵盖了装置在使用或操作中的不同方位。所述装置也可被另外定位(例如，旋转90度或者位于其他方位)，并对应地解读所使用的空间相关用语的描述。
各种实施例提供用于形成改善的虚设(dummy)栅极的工艺。举例来说，虚设栅极晶种层可沉积于鳍部上方。虚设栅极晶种层可从鳍部上方回焊(reflow)至与鳍部相邻的沟槽中。可通过卤素气体蚀刻(halogen-gas etch)来蚀刻虚设栅极晶种层。卤素气体蚀刻也可作用于设置于鳍部上的虚设介电层的暴露表面部分，虚设介电层在鳍部与虚设栅极晶种层之间。可在虚设栅极晶种层和虚设介电层上方进行额外的沉积工艺。额外的沉积工艺可选择性地沉积材料于虚设栅极晶种层上。在一些实施例中，额外的沉积工艺可以沉积材料于虚设栅极晶种层上的速率高于沉积材料于虚设介电层上的速率。接着，可将最终的结构平坦化，以形成虚设栅极。
进行虚设栅极的由下而上沉积防止了鳍部弯曲，且更防止了虚设栅极中形成接缝或孔隙，因此改善了装置产率并减少装置失效。
图1显示依据一些实施例的鳍式场效晶体管的范例的三维视图。鳍式场效晶体管包括在基底50(例如半导体基底)上的鳍部58。隔离区56设置于基底50中，且鳍部58突出于相邻的隔离区56之上。虽然分别描述和显示的隔离区56与基底50，但是本文所用的术语“基底”可单指半导体基底或包含隔离区56的半导体基底。栅极介电层92沿鳍部58的侧壁和顶表面(分布)，而栅极电极94在栅极介电层92上方。外延源极/漏极区82设置于鳍部58相对于栅极介电层92和栅极电极94的两侧上。图1还显示了用于后续附图的参考剖面。剖面A-A为沿栅极电极94的纵轴且在例如垂直于鳍式场效晶体管的外延源极/漏极区82之间的电流方向的方向。剖面B-B垂直于剖面A-A且沿鳍部58的纵轴，并在例如鳍式场效晶体管的外延源极/漏极区82之间的电流方向的方向。剖面C-C平行于剖面A-A，并延伸通过鳍式场效晶体管的外延源极/漏极区82。为了清楚起见，后续附图参考这些参考剖面。
在使用栅极后制(gate-last)工艺形成的鳍式场效晶体管的背景下讨论本文描述的一些实施例。在其他实施例中，可使用栅极先制(gate-first)工艺。再者，一些实施例考虑了在平面装置中使用的方面，例如平面场效晶体管。
图2至图23为依据一些实施例的制造鳍式场效晶体管的中间阶段的剖面示意图。图2-图13显示图1中的参考剖面A-A，除了图2-图13图有多个鳍部/鳍式场效晶体管。在图14A-图22B中，以“A”标记结尾的附图沿着图1中的参考剖面A-A显示，而以“B”标记结尾的附图沿着图1中的相似参考剖面B-B显示，除了图14A-图22B有多个鳍部/鳍式场效晶体管。图16C和D16图显示沿图1的参考剖面C-C，除了图16C和图16D有多个鳍部/鳍式场效晶体管。图23显示图1中的参考剖面B-B，除了图23有多个栅极/鳍式场效晶体管。
在图2中，提供基底50。基底50可为半导体基底，例如块状(bulk)半导体、绝缘层上覆半导体(semiconductor-on-insulator，SOI)基底或类似物，基底50可为掺杂(例如掺杂p型或n型掺杂物)或未掺杂。基底50可为晶圆，例如硅晶圆。一般来说，绝缘层上覆半导体基底为形成于绝缘层上的半导体材料层。绝缘层可为例如埋置氧化(buried oxide，BOX)层、氧化硅层或类似物。绝缘层提供于基底上，一般为硅基底或玻璃基底。也可使用其他基底，例如多层或梯度(gradient)基底。在一些实施例中，基底50的半导体材料可包含硅、锗、化合物半导体(包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟)、合金半导体(包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP)或前述的组合。
基底50具有第一区50A和第二区50B。第一区50A可用于形成n型装置，例如N型金属氧化物半导体(n-type metal oxide semiconductor，NMOS)晶体管(例如n型鳍式场效晶体管)。第二区50B可用于形成p型装置，例如P型金属氧化物半导体(p-type metal oxidesemiconductor，PMOS)晶体管(例如p型鳍式场效晶体管)。第一区50A可与第二区50B物理隔开(通过分隔线51)，且任何数量的装置部件(例如其他主动装置、掺杂区、隔离结构等)可设置于第一区50A与第二区50B之间。在一些实施例中，第一区50A和第二区50B均用于形成相同型的装置，例如两区域均用于n型装置或p型装置。
在图3中，鳍部52形成于基底50中。鳍部52为半导体条带(strip)。在一些实施例中，鳍部52可通过在基底50中蚀刻沟槽来形成于基底50中。蚀刻可为任何合适的蚀刻工艺，例如反应性离子蚀刻(reactive ion etch，RIE)、中子束蚀刻(neutral beam etch，NBE)、类似方法或前述的组合。此蚀刻可为非等向性。请注意，虽然显示的鳍部52具有线性边缘，但是鳍部52可为圆头或具有其他合适的形状。鳍部52可具有从鳍部到鳍部的间距在约5nm与约50nm之间，例如约20nm。然而，在一些实施例中，鳍部52可具有从鳍部到鳍部的间距大于约50nm或小于约5nm。
在图4中，绝缘材料54形成于基底50上方以及相邻鳍部52之间。绝缘材料54可为氧化物(例如氧化硅)、氮化物、类似物或前述的组合，且可通过高密度等离子体化学气相沉积(high density plasma chemical vapor deposition，HDP-CVD)、可流动化学气相沉积(flowable CVD，FCVD)(例如在远端等离子体系统中的基于化学气相沉积的材料沉积，并后固化使其转变为另一材料，例如氧化物)、类似方法或前述的组合形成。可使用通过任何合适的工艺形成的其他绝缘材料。在显示的实施例中，绝缘材料54为通过可流动化学气相沉积工艺形成的氧化硅。在形成绝缘材料之后，可进行退火工艺。在一实施例中，形成绝缘材料54，使得多余的绝缘材料覆盖鳍部52。
在图5中，将平坦化工艺应用至绝缘材料54。在一些实施例中，平坦化工艺包含化学机械研磨(chemical mechanical polish，CMP)、回蚀刻工艺、前述的组合或类似方法。平坦化工艺暴露出鳍部52。在完成平坦化工艺之后，鳍部52的顶表面和绝缘材料54的顶表面齐平。
在图6中，将绝缘材料54凹陷，以形成隔离区56(有时也被称为浅沟槽隔离(Shallow Trench Isolation，STI)区)。将绝缘材料54凹陷，使得在第一区50A和第二区50B中的鳍部58从相邻的隔离区56之间突出。再者，隔离区56的顶表面可具有如图所示的平坦表面、凸面、凹面(例如凹陷)或前述的组合。隔离区56的顶表面可通过合适的蚀刻形成平坦、凸形及/或凹形。隔离区56可通过使用合适的蚀刻工艺凹陷，例如对绝缘材料54的材料有选择性的蚀刻工艺。举例来说，使用无等离子体气体蚀刻工艺(例如使用氟化氢(hydrogen fluoride，HF)气体、氨(NH3)气体或类似物的蚀刻工艺)的化学氧化物移除、远端等离子体辅助干蚀刻工艺(例如使用氢(H2)、三氟化氮(NF3)和氨副产物或类似物)，或可使用稀释氢氟酸(dilute hydrofluoric，dHF)。
本发明所属技术领域中具通常知识者将容易理解关于图2-图6所描述的工艺仅为可如何形成鳍部58的一范例。在一些实施例中，介电层可形成于基底50的顶表面上方；可蚀刻沟槽穿透介电层；同质外延结构可外延成长于沟槽中；以及可将介电层凹陷，使得同质外延结构从介电层突出，以形成鳍部58。在一些实施例中，异质外延结构可用于鳍部52。举例来说，可将图5中的鳍部52进行凹陷，并在凹陷处外延成长不同于鳍部52的材料。在另一实施例中，介电层可形成于基底50的顶表面上方；可蚀刻沟槽穿透介电层；异质外延结构可通过使用不同于基底50的材料外延成长于沟槽中；以及将介电层凹陷，使得异质外延结构从介电层突出，以形成鳍部58。在外延成长同质外延或异质外延结构的一些实施例中，外延成长材料可在成长期间原位(in situ)掺杂，其可免除之前或后续的布植(implant，种植)，但是可一起使用原位掺杂和布植掺杂。再者，在N型金属氧化物半导体区域中外延成长不同于在P型金属氧化物半导体区域可为有利的。在各种实施例中，鳍部58可由硅锗(SixGe1-x，其中x可在0至1的范围中)、碳化硅、纯锗或大致纯锗、第III-V族化合物半导体、第II-VI族化合物半导体或类似物形成。举例来说，可用于形成第III-V族化合物半导体的材料包含InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP和类似物，但不限于此。
在其他实施例中，合适的井区(未显示)可形成于鳍部58、鳍部52及/或基底50中。在一些实施例中，P型井可形成于第一区50A中，且N型井可形成于第二区50B中。在一些实施例中，P型井或N型井可均形成于第一区50A和第二区50B中。
在有着不同井区类型的实施例中，可通过使用光刻胶或其他遮罩(未个别显示)来达成用于第一区50A和第二区50B的不同布植步骤。举例来说，光刻胶可形成于第一区50A和第二区50B中的鳍部58和隔离区56上方。将光刻胶图案化以暴露出基底50的第二区50B(例如P型金属氧化物半导体区域)。光刻胶可通过使用旋涂技术形成，且可通过使用合适的光刻技术图案化。在将光刻胶图案化之后，进行n型杂质布植于第二区50B中，且光刻胶可作为遮罩来大致防止n型杂质植入第一区50A(例如N型金属氧化物半导体区域)中。N型杂质可为被植入区域中的磷、砷或类似物至浓度等于或小于1018cm-3，例如在约1017cm-3至约1018cm-3之间。在布植之后，例如通过合适的灰化工艺来移除光刻胶。
在第二区50B的布植之后，第二光刻胶形成于第一区50A和第二区50B中的鳍部58和隔离区56上方。将此光刻胶图案化以暴露出基底50的第一区50A(例如N型金属氧化物半导体区域)。光刻胶可通过使用旋涂技术形成，且可通过使用合适的光刻技术而图案化。在将光刻胶图案化之后，进行p型杂质布植于第一区50A中，且光刻胶可作为遮罩来大致防止p型杂质植入第二区50B(例如P型金属氧化物半导体区域)中。P型杂质可为被植入区域中的硼、BF2或类似物至浓度等于或小于1018cm-3，例如在约1017cm-3至约1018cm-3之间。在布植之后，例如通过合适的灰化工艺来移除光刻胶。
在第一区50A和第二区50B的布植之后，可进行退火来活化被植入的p型及/或n型杂质。在一些实施例中，外延鳍部的成长材料可在成长期间原位掺杂，其可免除布植。依据一些实施例，可一起使用原位掺杂和布植掺杂。
在图7中，虚设介电层60形成于鳍部58上。虚设介电层60可例如为氧化硅、氮化硅、前述的组合或类似物，且可通过合适的技术来沉积或热成长。虚设介电层60可具有厚度T1在约与约
Figure BDA0002085181290000082
之间，例如约
Figure BDA0002085181290000083
如图7所示，虚设介电层60可选择性地形成于鳍部58上，且可不形成于隔离区56上。
在图8中，虚设栅极材料63形成于虚设介电层60和隔离区56上方。在一些实施例中，虚设栅极材料63可由非晶硅(a-Si)材料形成。虚设栅极材料63可通过任何合适的工艺形成，例如化学气相沉积(chemical vapor deposition，CVD)工艺、原子层沉积(atomiclayer deposition，ALD)工艺、低压化学气相沉积(low pressure chemical vapordeposition，LPCVD)工艺或类似方法。虚设栅极材料63的形成可包含沉积硅晶种层(未个别显示)，以及接着在硅晶种层上成长额外的硅。依据一些实施例，虚设栅极材料63可被称为虚设栅极晶种层。用于沉积虚设栅极材料63的前驱物可包含SiH3-N((CH-(CH3)2)2、二硅烷(Si2H6)、单硅烷(SiH4)、前述的组合或类似物。虚设栅极材料63可没有其他元素，例如锗(Ge)、n型杂质(例如磷(P)和砷(As))和p型杂质(例如硼(B)和铟(In))，或可包含这些元素的其中一些。
在使用二硅烷成长虚设栅极材料63的实施例中，温度可在约300℃与约450℃之间。在使用单硅烷成长虚设栅极材料63的实施例中，温度可在约400℃与约600℃之间。依据温度、虚设栅极材料63的成长速率和其他工艺条件，虚设栅极材料63可为非晶硅层或多晶硅层。如图8所示，虚设栅极材料63可为顺应层，且沿虚设介电层60和隔离区56的顶表面以及虚设介电层60的侧表面具有均匀的厚度。虚设栅极材料63可具有的厚度T2在约1nm与约20nm之间，例如约5nm。
在图9中，虚设栅极材料63从鳍部58上方回焊至与鳍部58相邻的沟槽中。虚设栅极材料63可通过加热基底50、循环加热在虚设栅极材料63的顶表面上方的气体、前述的组合或任何其他合适的方法来回焊。在一些实施例中，进行回焊的温度在约450℃与约600℃之间，例如约470℃。回焊可持续约3分钟至约2小时，回焊时间取决于温度，较高的温度对应至较短的回焊时间，而较低的温度对应至较长的回焊时间。在回焊期间，可引入工艺气体，例如氮(N2)或氢(H2)。虚设栅极材料63可在压力小于约100Torr来回焊，例如在约1mTorr与约90Torr之间。可将虚设栅极材料63回焊使得在虚设介电层60的顶表面上的虚设栅极材料63的厚度T3在约0.1nm与约20nm之间，例如约5nm。在回焊之后，虚设栅极材料63的氢(H)浓度可在约0.1wt％(重量百分比)与约2wt％之间，或小于约2wt％。在一些实施例中，在将虚设栅极材料63回焊之后，虚设栅极材料63可具有氢浓度小于约2×1020atoms/cm3。
在图10中，蚀刻虚设栅极材料63以暴露出虚设介电层60的至少一部分。可通过任何合适的工艺蚀刻虚设栅极材料63，例如卤素系气体蚀刻(例如卤素系等离子体蚀刻)或类似方法。蚀刻工艺可使用合适的气体。蚀刻工艺可使用含卤素气体，例如含有氯(Cl2)、氟(F2)、溴(Br2)、碘(I2)、前述的组合或类似物的气体。蚀刻气体可与虚设介电层60的暴露部分反应以作用于虚设介电层60的暴露部分，形成卤素末端(halogen-terminated)虚设介电层61。卤素末端虚设介电层61可作为保护层。在一些实施例中，蚀刻气体也可与虚设栅极材料63的暴露部分反应以作用于虚设栅极材料63的暴露部分，在虚设栅极材料63的暴露部分上形成卤素末端层(未个别显示)。
可蚀刻虚设栅极材料63，使得虚设栅极材料63的高度H2大于虚设介电层60和卤素末端虚设介电层61的总和的高度H1的约10％。举例来说，高度H1可在约30nm与约100nm之间，例如约35nm。高度H2可在约3nm与约99nm之间，例如约30nm。高度H2可在高度H1的约10％与约99％之间，例如高度H1的约80％。在一些实施例中，高度H2可大于高度H1的约10％。
在图11中，附加虚设栅极材料63’通过额外的沉积工艺沉积于虚设栅极材料63上，沉积工艺例如化学气相沉积、原子层沉积或类似方法。额外的沉积工艺可为选择性的且可仅沉积于虚设栅极材料63上，而不沉积于卤素末端虚设介电层61上。如此一来，附加虚设栅极材料63’可在由下而上工艺沉积于图10的虚设栅极材料63上方。在一些实施例中，附加虚设栅极材料63’可均沉积于虚设栅极材料63和卤素末端虚设介电层61上方，但是在虚设栅极材料63上的沉积速率高于在卤素末端虚设介电层61上的沉积速率。在一些实施例中，卤素末端虚设介电层61的培养时间(incubation time)(在暴露于额外的沉积工艺之后，附加虚设栅极材料63’形成于层的表面上的所需时间)可比虚设栅极材料63的培养时间多出约40分钟或多出约5分钟。
在图12中，通过额外的沉积工艺更进一步沉积附加虚设栅极材料63’，且接着将其平坦化以形成虚设栅极层62。虚设栅极层62可通过合适的平坦化工艺来平坦化，例如化学机械研磨(chemical mechanical planarization，CMP)工艺、研磨、回蚀刻平坦化工艺或类似方法。虚设栅极层62可具有的高度H3在约60nm与约190nm之间，例如约100nm。虚设栅极层62可由与虚设栅极材料63相同或相似的材料形成。举例来说，虚设栅极层62可始终由非晶硅(a-Si)材料形成。
通过沉积虚设栅极材料63、将虚设栅极材料63回焊、蚀刻虚设栅极材料63并反应作用于虚设介电层60，以及在虚设栅极材料63上进行额外沉积附加虚设栅极材料63’(例如通过由下而上沉积工艺形成虚设栅极层62)形成虚设栅极层62减少了鳍部58之间形成接缝或孔隙，并降低了鳍部58之间的沟槽的深宽比。此工艺也减少鳍部58弯曲。举例来说，在形成虚设栅极层62之后，鳍部到鳍部的间距的差值(例如鳍部到鳍部的间距的差异或改变)可小于约6nm，例如约0.55nm，或约0.29nm。虚设栅极层62中形成的接缝/孔隙以及鳍部58的弯曲均可导致取代栅极的沉积问题(以下参照图20A和图20B讨论)，而通过上述方法形成虚设栅极层62有利地减少了这些问题。
在一些实施例中，上述由下而上沉积工艺可用于形成晶体管在基底50上的一些区域中，而传统工艺可用于形成晶体管在基底50上的其他区域中。仅通过上述由下而上沉积工艺形成的晶体管可具有由下而上工艺的益处。再者，卤素末端虚设介电层61可仅存在于通过由下而上工艺形成的晶体管中。相对地，通过传统工艺形成的晶体管可包含非卤素末端的虚设介电层。
在图13中，遮罩层64形成于虚设栅极层62上方。遮罩层64可通过任何合适的方法沉积于虚设栅极层62上方，例如化学气相沉积、等离子体辅助化学气相沉积(plasma-enhanced CVD，PECVD)、低压化学气相沉积(LPCVD)或类似方法。遮罩层64可包含例如氮化硅(例如Si3N4)、氧化硅(SiO2)、氮氧化硅(Si2N2O)或类似物。
图14A-图22B显示实施例装置的制造中的各种额外步骤。图14A-图22B显示第一区50A和第二区50B中的任一个的部件。举例来说，显示于图14A-图22B的结构均可应用于第一区50A和第二区50B。第一区50A和第二区50B的结构中的差异(如果有)描述于附于每幅图的正文中。
在图14A和图14B中，遮罩层64可通过使用合适的光刻和蚀刻技术形成遮罩74。接着，遮罩74的图案可通过合适的蚀刻技术转移至虚设栅极层62以形成虚设栅极72。在一些实施例中，遮罩74的图案也可转移至虚设介电层60及/或卤素末端虚设介电层61(未个别显示)。虚设栅极72覆盖鳍部58的个别通道区。遮罩74的图案可用于将每个虚设栅极72与相邻的虚设栅极物理地隔开。虚设栅极72也可具有长度方向大致垂直于个别的外延鳍部52/58的长度方向。
再者，在图14A和图14B中，栅极密封间隙壁80可形成于虚设栅极72、遮罩74及/或鳍部58的暴露表面上。热氧化或沉积之后进行非等向性蚀刻可形成栅极密封间隙壁80。
在形成栅极密封间隙壁80之后，可进行用于轻掺杂源极/漏极(lightly dopedsource/drain，LDD)区(未明确显示)的布植。在有着不同装置类型的实施例中，相似于上述图6的布植，遮罩(例如光刻胶)可形成于第一区50A上方，同时暴露出第二区50B，且可将合适类型(例如p型)的杂质植入第二区50B中暴露的鳍部58中。接着，可移除遮罩。之后，遮罩(例如光刻胶)可形成于第二区50B上方，同时暴露出第一区50A，且可将合适类型(例如n型)的杂质植入第一区50A中暴露的鳍部58中。接着，可移除遮罩。n型杂质可为任何前述的n型杂质，且p型杂质可为任何前述的p型杂质。轻掺杂源极/漏极区具有杂质的浓度在约1015cm-3至约1016cm-3。可使用退火来活化植入的杂质。
在图15A和图15B中，栅极间隙壁86沿虚设栅极72和遮罩74的侧壁形成于栅极密封间隙壁80上。栅极间隙壁86可通过顺应性沉积材料，接着非等向性蚀刻此材料来形成。栅极间隙壁86的材料可为氮化硅、SiCN、前述的组合或类似物。
在图16A和图16B中，外延源极/漏极区82(有时也被简称为源极/漏极区)形成于鳍部58中。外延源极/漏极区82形成于鳍部58中，使得每个虚设栅极72设置于各对相邻的外延源极/漏极区82之间。在一些实施例中，外延源极/漏极区82可延伸进入鳍部52中。在一些实施例中，栅极间隙壁86用于将外延源极/漏极区82与虚设栅极72以合适的横向距离隔开，使得外延源极/漏极区82不会导致后续形成最终的鳍式场效晶体管的栅极短路。
第一区50A(例如N型金属氧化物半导体区)中的外延源极/漏极区82可通过将第二区50B(例如P型金属氧化物半导体区)遮蔽，并蚀刻第一区50A中的鳍部58的源极/漏极区，以在鳍部58中形成凹口。接着，第一区50A中的外延源极/漏极区82外延成长于凹口中。外延源极/漏极区82可包含任何合适的材料，例如适用于n型鳍式场效晶体管的材料。举例来说，假如鳍部58为硅，第一区50A中的外延源极/漏极区82可包含硅、SiC、SiCP、SiP或类似物。第一区50A中的外延源极/漏极区82可具有从鳍部58的各自表面凸起的表面，且可具有多面。
第二区50B(例如P型金属氧化物半导体区)中的外延源极/漏极区82可通过将第一区50A(例如N型金属氧化物半导体区)遮蔽，接着蚀刻第二区50B中的鳍部58的源极/漏极区，以在鳍部58中形成凹口。接着，第二区50B中的外延源极/漏极区82外延成长于凹口中。外延源极/漏极区82可包含任何合适的材料，例如适用于p型鳍式场效晶体管的材料。举例来说，假如鳍部58为硅，第二区50B中的外延源极/漏极区82可包含SiGe、SiGeB、Ge、GeSn或类似物。第二区50B中的外延源极/漏极区82可具有从鳍部58的各自表面凸起的表面，且可具有多面。
可将外延源极/漏极区82及/或鳍部58植入掺杂物以形成源极/漏极区，此工艺相似于上述用于形成轻掺杂源极/漏极区的工艺，接着进行退火。源极/漏极区可具有杂质浓度在约1019cm-3至约1021cm-3之间。用于源极/漏极区的n型杂质及/或p型杂质可为前述的任何杂质。在一些实施例中，外延源极/漏极区82可在成长期间原位掺杂。
由于用于在第一区50A和第二区50B中形成外延源极/漏极区82的外延工艺，因此外延源极/漏极区82的上表面具有多面横向向外扩展超过鳍部58的侧壁。在一些实施例中，如图16C所示，这些面导致同一个鳍式场效晶体管装置的相邻外延源极/漏极区82合并。在其他实施例中，如图16D所示，在完成外延工艺之后，相邻的外延源极/漏极区82保持分开。
在图17A和图17B中，层间介电层(interlayer dielectric layer，ILD)88设置于图16A和图16B显示的结构上方。层间介电层88可由介电材料或半导体材料形成，且可通过任何合适的方法沉积，例如化学气相沉积、等离子体辅助化学气相沉积(PECVD)或可流动化学气相沉积。介电材料可包含磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、硼掺杂磷硅酸盐玻璃(boron-doped phosphosilicateglass，BPSG)、未掺杂硅酸盐玻璃(undoped silicate glass，USG)或类似物。半导体材料可包含非晶硅(a-Si)、硅锗(SixGe1-x，其中x可在大致0至1之间)、纯锗或类似物。可使用通过任何合适的工艺形成的其他绝缘物或半导体材料。在一些实施例中，接触蚀刻停止层(contact etch stop layer，CESL)(未个别显示)设置于层间介电层88与外延源极/漏极区82、遮罩74以及栅极间隙壁86之间。
在图18A和图18B中，可进行平坦化工艺(例如化学机械研磨)，使层间介电层88的顶表面与虚设栅极72的顶表面齐平。平坦化工艺也可移除虚设栅极72上的遮罩74以及栅极密封间隙壁80和栅极间隙壁86沿遮罩74的侧壁的部分。在平坦化工艺之后，虚设栅极72、栅极密封间隙壁80、栅极间隙壁86和层间介电层88的顶表面齐平。因此，虚设栅极72的顶表面从层间介电层88暴露出来。
在图19A和图19B中，在蚀刻步骤中移除虚设栅极72和卤素末端虚设介电层61在暴露的虚设栅极72正下方的部分，以形成凹口90。在一些实施例中，虚设栅极72通过非等向性干蚀刻工艺移除。举例来说，蚀刻工艺可包含干蚀刻工艺，干蚀刻工艺使用反应气体选择性地蚀刻虚设栅极72而不蚀刻层间介电层88或栅极间隙壁86。每个凹口90暴露出各自鳍部58的通道区。每个通道区设置于各对相邻的外延源极/漏极区82之间。在移除工艺期间，卤素末端虚设介电层61可用作当虚设栅极72被蚀刻时的蚀刻停止层。在移除虚设栅极72之后，可接着移除卤素末端虚设介电层61。
在图20A和图20B中，形成用于取代栅极的栅极介电层92、功函数层93和栅极电极94。栅极介电层92顺应性沉积于凹口90中，例如沉积于鳍部58的顶表面和侧壁上以及栅极密封间隙壁80/栅极间隙壁86的侧壁上。栅极介电层92也可形成于层间介电层88的顶表面上。依据一些实施例，栅极介电层92包括氧化硅(SiO2)、氮化硅(Si3N4)或前述的多层。在一些实施例中，栅极介电层92为高介电常数(high-k)介电材料，且在这些实施例中，栅极介电层92可具有介电常数值大于约7.0，且可包含Hf、Al、Zr、La、Mg、Ba、Ti、Pb和前述的组合的金属氧化物或硅酸盐。栅极介电层92的形成方法可包含分子束沉积(Molecular-BeamDeposition，MBD)、原子层沉积、等离子体辅助化学气相沉积和类似方法。
再者，在图20A和图20B中，形成导电材料填入凹口90中。导电材料可包含一种或多种阻障层、功函数层及/或功函数调整层，以调整后续形成的栅极电极的功函数。在一实施例中，功函数层93沉积于栅极介电层92上方。功函数层93可为含金属材料，例如Al、TiC、TiN、前述的组合或前述的多层。
栅极电极94沉积于功函数层93上方，并填充凹口90的剩下部分。栅极电极94可为含金属材料，例如TiN、TaN、TaC、Co、Ru、Al、前述的组合或前述的多层。在填充栅极电极94之后，可进行平坦化工艺(例如化学机械研磨)来移除栅极介电层92、功函数层93和栅极电极94的材料的多余部分，其中多余部分在层间介电层88的顶表面上方。栅极电极94、功函数层93和栅极介电层92的剩下部分因此形成最终鳍式场效晶体管的取代栅极。栅极电极94、功函数层93和栅极介电层92可被统称为“栅极”或“栅极堆叠”。栅极和栅极堆叠可沿鳍部58的通道区的侧壁延伸。
在第一区50A和第二区50B中的栅极介电层92的形成可同时发生，使得在每一区域中的栅极介电层92由相同材料形成。相似地，在第一区50A和第二区50B中的功函数层93的形成和栅极电极94的形成可各自同时发生，使得在每个区域中的功函数层93和栅极电极94由相同于另一区域中的功函数层93和栅极电极94的材料。在一些实施例中，在每一区域中的栅极介电层92、功函数层93和栅极电极94可由不同的工艺形成，使得在每一区域中的栅极介电层92、功函数层93和栅极电极94可为不同材料。当使用不同工艺时，可使用各种遮罩步骤来遮蔽并暴露出合适的区域。
在图21A和图21B中，层间介电层108设置于层间介电层88上方。在一实施例中，层间介电层108为通过可流动化学气相沉积方法形成的可流动膜。在一些实施例中，层间介电层108由介电材料形成，例如磷硅酸盐玻璃、硼硅酸盐玻璃、硼掺杂磷硅酸盐玻璃、未掺杂硅酸盐玻璃或类似物，且层间介电层108可通过任何合适的方法沉积，例如化学气相沉积或等离子体辅助化学气相沉积。
在图22A和图22B中，形成栅极接点110和源极/漏极接点112通过层间介电层108和层间介电层88。用于源极/漏极接点112的开口(未个别显示)形成通过层间介电层108和层间介电层88，而用于栅极接点110的开口(未个别显示)形成通过层间介电层108。开口可通过使用合适的光刻和蚀刻技术形成。选择性地，在形成栅极接点110和源极/漏极接点112之前，可形成硅化物接点(未个别显示)。硅化物接点可包括钛、镍、钴或铒，且可用以降低栅极接点110和源极/漏极接点112的萧基阻障高度(Schottky barrier height，肖特基势垒高度)。然而，也可使用其他金属，例如铂、钯和类似物。硅化可通过毯覆式沉积合适的金属层以及接着使金属与下方暴露的硅反应的退火步骤来进行。接着，例如以选择性蚀刻工艺移除未反应的金属。硅化物接点的厚度可在约5nm与约50nm之间。
栅极接点110和源极/漏极接点112可由导电材料形成，例如Al、Cu、W、Co、Ti、Ta、Ru、TiN、TiAl、TiAlN、TaN、TaC、NiSi、CoSi、前述的组合或类似物，但是也可使用任何合适的导电材料。栅极接点110和源极/漏极接点112可通过使用沉积工艺(例如溅镀、化学气相沉积、电镀、无电电镀或类似方法)沉积于层间介电层108和层间介电层88的开口中，以填充及/或过填充开口。当填充或过填充之后，可通过使用平坦化工艺(例如化学机械研磨(CMP))移除在开口之外的任何沉积材料。
栅极接点110物理及电性连接至栅极电极94，且源极/漏极接点112物理及电性连接至外延源极/漏极区82。图22A和图22B在相同剖面显示栅极接点110和源极/漏极接点112，然而，在其他实施例中，栅极接点110和源极/漏极接点112可设置于不同剖面中。再者，图22A和图22B中的栅极接点110和源极/漏极接点112仅为说明性，而不是以任何方式进行限制。举例来说，如图所示，栅极接点110可与鳍部52垂直对齐，或栅极接点110可设置于在栅极电极94上的其他位置。再者，源极/漏极接点112可在形成栅极接点110之前、同时或之后形成。如图22A和图22B所示，卤素末端虚设介电层61的至少一部分可保留在鳍部58上。
图23显示第一区50A中的鳍式场效晶体管装置和第二区50B中的鳍式场效晶体管装置。如图23所示，第一区50A和第二区50B中的鳍式场效晶体管装置彼此相同或相似，且可通过上述参照图14A-图22B的步骤形成。第一区50A中的鳍式场效晶体管装置可与第二区50B中的鳍式场效晶体管装置同时形成，或可与第二区50B中的鳍式场效晶体管装置分别形成。
许多晶体管可形成横跨基底50的表面。在一些实施例中，上述的由下而上工艺可用于形成基底50的一些区域中的晶体管，而传统工艺可用于形成基底50的其他区域中的晶体管。因此，仅在包含通过由下而上工艺形成的晶体管的区域可具有由下而上工艺的益处，且卤素末端虚设介电层61可仅存在于通过由下而上工艺形成的晶体管的区域中。包含通过传统工艺形成的晶体管的区域可包含并非卤素末端的传统虚设介电层。
依据上述的由下而上工艺形成的虚设栅极层62具有许多优点。举例来说，由下而上工艺减少鳍部58弯曲。此工艺也防止了在虚设栅极层62中形成接缝或孔隙。因此，可在形成栅极堆叠之前完全地移除虚设栅极层62，而不留下任何残留物或剩余材料。如此导致装置效能改善，也增加了装置产率。
依据一实施例，一方法包含在从基底延伸出的鳍部上沉积虚设介电层；在虚设介电层上沉积虚设栅极晶种层；将虚设栅极晶种层回焊；蚀刻虚设栅极晶种层；以及在虚设栅极晶种层上方选择性地沉积虚设栅极材料，虚设栅极材料和虚设栅极晶种层形成虚设栅极。在一实施例中，蚀刻虚设栅极晶种层的步骤暴露出虚设介电层的一部分。在一实施例中，蚀刻虚设栅极晶种层的步骤在虚设介电层的暴露部分上形成作用表面。在一实施例中，虚设栅极材料以第一速率沉积于虚设栅极晶种层上，其中虚设栅极材料以第二速率沉积于虚设介电层的作用表面上，且第一速率大于第二速率。在一实施例中，此方法还包含移除虚设栅极以形成凹口，以及在凹口中形成取代栅极。在一实施例中，移除虚设栅极的步骤还包含移除虚设介电层的至少一部分，且在移除虚设栅极之后，虚设介电层的另一部分包含作用表面。在一实施例中，蚀刻虚设栅极晶种层的步骤包含卤素系等离子体蚀刻。在一实施例中，在将虚设栅极晶种层回焊之后，虚设栅极晶种层具有小于2×1020atoms/cm3的氢浓度。在一实施例中，虚设栅极晶种层通过原子层沉积(ALD)或化学气相沉积(CVD)来沉积。在一实施例中，虚设栅极包含非晶硅(a-Si)。在一实施例中，虚设栅极晶种层在大于温度470℃、时间大于3分钟以及压力小于100Torr的条件下回焊。
依据一实施例，一方法包含在从基底延伸出的鳍部上沉积虚设介电层；在虚设介电层上沉积第一虚设栅极材料；将第一虚设栅极材料回焊；蚀刻第一虚设栅极材料和虚设介电层，其中蚀刻虚设介电层之后，形成具有末端基的虚设介电层；以及在第一虚设栅极材料上方沉积第二虚设栅极材料以形成虚设栅极，第二虚设栅极材料选择性地沉积于第一虚设栅极材料上。在一实施例中，此方法还包含蚀刻虚设栅极和虚设介电层以形成凹口，在蚀刻虚设栅极和虚设介电层之后，保留具有末端基的虚设介电层的至少一部分；以及在凹口中形成栅极堆叠。在一实施例中，蚀刻步骤包含卤素基气体蚀刻。在一实施例中，虚设介电层的表面通过蚀刻第一虚设栅极材料而暴露出来，且虚设介电层的暴露的表面通过蚀刻作用而形成具有末端基的虚设介电层。在一实施例中，基底包含多个鳍部，且在形成虚设栅极之后，多个鳍部的从鳍部到鳍部的间距的变异小于约6nm。
依据一实施例，半导体装置包含栅极堆叠，位于半导体基底上方；栅极间隙壁，设置于栅极堆叠的侧壁上；以及介电层，设置于半导体基底与栅极间隙壁之间，介电层包含卤素末端表面。在一实施例中，卤素末端表面包含氯末端二氧化硅。在一实施例中，半导体基底包含一个或多个鳍部。在一实施例中，半导体装置还包含：第二栅极堆叠，位于半导体基底上方；第二栅极间隙壁，设置于第二栅极堆叠的侧壁上；以及第二介电层，设置于半导体基底与第二栅极间隙壁之间，第二介电层不具有卤素末端。
前文概述了许多实施例的特征，使本技术领域中的一般技术人员可以从各个方面更加了解本发明实施例。本技术领域中的一般技术人员应可理解，且可轻易地以本发明实施例为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中的一般技术人员也应了解这些相等的结构并未背离本发明的发明精神与范围。在不背离本发明的发明精神与范围的前提下，可对本发明实施例进行各种改变、置换或修改。

Claims (10)

1.一种半导体装置的制造方法，包括：
在从一基底延伸出的一鳍部上沉积一虚设介电层；
在该虚设介电层上沉积一虚设栅极晶种层；
将该虚设栅极晶种层回焊；
蚀刻该虚设栅极晶种层；以及
在该虚设栅极晶种层上方选择性地沉积一虚设栅极材料，其中该虚设栅极材料和该虚设栅极晶种层构成一虚设栅极。
2.如权利要求1所述的半导体装置的制造方法，其中蚀刻该虚设栅极晶种层的步骤暴露出该虚设介电层的一部分。
3.如权利要求2所述的半导体装置的制造方法，其中蚀刻该虚设栅极晶种层的步骤在该虚设介电层的暴露的该部分上形成一作用表面。
4.如权利要求3所述的半导体装置的制造方法，其中该虚设栅极材料以一第一速率沉积于该虚设栅极晶种层上，其中该虚设栅极材料以一第二速率沉积于该虚设介电层的该作用表面上，且其中该第一速率大于该第二速率。
5.如权利要求3所述的半导体装置的制造方法，还包括：
移除该虚设栅极以形成一凹口；以及
在该凹口中形成一取代栅极。
6.如权利要求1所述的半导体装置的制造方法，其中蚀刻该虚设栅极晶种层的步骤包括一卤素系等离子体蚀刻。
7.一种半导体装置的制造方法，包括：
在从一基底延伸出的一鳍部上沉积一虚设介电层；
在该虚设介电层上沉积一第一虚设栅极材料；
将该第一虚设栅极材料回焊；
蚀刻该第一虚设栅极材料和该虚设介电层，其中蚀刻该虚设介电层之后，形成一具有末端基的虚设介电层；以及
在该第一虚设栅极材料上方沉积一第二虚设栅极材料以形成一虚设栅极，其中该第二虚设栅极材料选择性地沉积于该第一虚设栅极材料上。
8.如权利要求7所述的半导体装置的制造方法，还包括：
蚀刻该虚设栅极和该虚设介电层以形成一凹口，在蚀刻该虚设栅极和该虚设介电层之后，保留具有末端基的该虚设介电层的至少一部分；以及
在该凹口中形成一栅极堆叠。
9.如权利要求7所述的半导体装置的制造方法，其中该虚设介电层的一表面通过蚀刻该第一虚设栅极材料而暴露出来，且其中该虚设介电层的暴露的该表面通过蚀刻作用而形成所述具有末端基的虚设介电层。
10.一种半导体装置，包括：
一栅极堆叠，位于一半导体基底上方；
一栅极间隙壁，设置于该栅极堆叠的侧壁上；以及
一介电层，设置于该半导体基底与该栅极间隙壁之间，该介电层包括一卤素末端表面。
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US11728406B2 (en) 2023-08-15
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