CN110783176B - Preparation method of low-stress semiconductor material - Google Patents
Preparation method of low-stress semiconductor material Download PDFInfo
- Publication number
- CN110783176B CN110783176B CN201911041382.1A CN201911041382A CN110783176B CN 110783176 B CN110783176 B CN 110783176B CN 201911041382 A CN201911041382 A CN 201911041382A CN 110783176 B CN110783176 B CN 110783176B
- Authority
- CN
- China
- Prior art keywords
- insulating substrate
- stress
- etching
- semiconductor
- semiconductor epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to the technical field of semiconductor material preparation, and discloses a preparation method of a low-stress semiconductor material, which comprises the steps of placing an insulating substrate with a mask on the surface in etching gas, ionizing the etching gas under the action of an external electric field and bombarding the upper surface of the insulating substrate with the mask, and carrying out pattern etching on the insulating substrate; and sequentially growing a plurality of epitaxial structures of the semiconductor epitaxial layers on the surface of the insulating substrate with the etching patterns, wherein the semiconductor epitaxial layers with compressive stress and the semiconductor epitaxial layers with tensile stress are in periodic change, and the stress of the whole epitaxial structure is close to zero. The invention generates the etching pattern on the insulating substrate through dry etching, thereby reducing the stress between the insulating substrate and the epitaxial structure, and then the epitaxial structure consisting of a series of semiconductor epitaxial layers with periodically changed compressive stress and tensile stress is grown on the insulating substrate with the etching pattern, so that the stress of the whole epitaxial structure is close to zero, thereby reducing the cracking and linear defect density of the material.
Description
Technical Field
The invention relates to the technical field of semiconductor material preparation, in particular to a preparation method of a low-stress semiconductor material.
Background
Stress is generally an undesirable phenomenon in the manufacture of semiconductor materials and is generally avoided or minimized, e.g., when the semiconductor material is under excessive tensile stress, it can cause cracking; in the case of an excessive compressive stress, wrinkles or peeling may be caused; these stress problems can increase the linear defect density of the semiconductor material, thereby weakening the original insulating, passivating, sealing effects of the semiconductor material, affecting the stability of the device or causing chip failure. In addition, too much stress in the semiconductor material can cause defects, such as slip planes and slip lines. How to reduce the stress of the semiconductor material is a very critical issue.
Disclosure of Invention
Based on the problems, the invention provides a preparation method of a low-stress semiconductor material, which is characterized in that an etching pattern is generated on an insulating substrate through dry etching, so that the stress between the insulating substrate and an epitaxial structure is reduced, and then the epitaxial structure consisting of a series of semiconductor epitaxial layers with periodically changed compressive stress and tensile stress grows on the insulating substrate with the etching pattern, so that the stress of the whole epitaxial structure is close to zero, and the cracking and linear defect density of the material are reduced.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a preparation method of a low-stress semiconductor material comprises the following steps:
s1: covering a layer of mask with a hollowed-out etching pattern on the upper surface of an insulating substrate, placing the insulating substrate in a reactor with two electrode plates, vacuumizing the reactor, arranging the two electrode plates oppositely, placing the insulating substrate between the two electrode plates, and enabling the surface of the insulating substrate with the mask to be parallel to the two electrode plates;
s2: introducing etching gas into the reactor, applying an electric field to two sides of the upper surface and the lower surface of the insulating substrate to ionize the etching gas and bombard the upper surface of the insulating substrate with the mask, and etching the pattern of the insulating substrate;
s3: taking out the etched insulating substrate, and removing the mask on the upper surface of the insulating substrate;
s4: and sequentially growing a plurality of epitaxial structures of the semiconductor epitaxial layers on the surface of the insulating substrate with the etching patterns, wherein the semiconductor epitaxial layers with compressive stress and the semiconductor epitaxial layers with tensile stress are in periodic change, and the stress of the whole epitaxial structure is close to zero.
Further, the insulating substrate is made of a composite substrate of one or more of Si, GaAs, GaN, sapphire, and SiC.
Further, the etching gas in step S2 is any one of H2, NH3, HCl, BCl3, and Ar, or a combination of two or more atmospheres; the temperature of the etching gas in the reactor is 800-2000 ℃.
Furthermore, in step S2, the etching pattern of the insulating substrate is one or more than two of a round bottom, a cylinder, a round hole, a hexagonal hole or a triangular hole, the patterns are periodically distributed, the period is 0.5-3um, and the depth of the patterns is 0.1-10 um.
Further, in step S4, the semiconductor epitaxial layers are grown by vapor deposition in a growth chamber, and during the growth process, gaseous group iii nitride and gaseous group v nitride are simultaneously introduced, the carrier gas is nitrogen, and the gas pressure in the growth chamber is 10-2500 torr.
Further, in the step S4, during the growth of the semiconductor epitaxial layer with compressive stress, the molar ratio of the group v nitride to the group iii nitride is 5-1000, and the growth temperature of the compressive stress layer is adjusted within the range of 200-1100 ℃.
Further, in the step S4, during the growth of the semiconductor epitaxial layer with tensile stress, the molar ratio of the group v nitride to the group iii nitride is 2000-.
Further, before the first semiconductor epitaxial layer is grown in step S4, the surface of the insulating substrate is treated with a high temperature metal-organic source group III element in advance.
Compared with the prior art, the invention has the beneficial effects that: the invention generates the etching pattern on the insulating substrate through dry etching, thereby reducing the stress between the insulating substrate and the epitaxial structure, and then the epitaxial structure consisting of a series of semiconductor epitaxial layers with periodically changed compressive stress and tensile stress is grown on the insulating substrate with the etching pattern, so that the stress of the whole epitaxial structure is close to zero, thereby reducing the cracking and linear defect density of the material.
Drawings
FIG. 1 is a flow chart of a method for fabricating a low stress semiconductor material according to an embodiment;
FIG. 2 is a schematic structural diagram of a low-stress semiconductor material formed by arranging tensile-stress and compressive-stress semiconductor epitaxial layers at intervals in an embodiment;
FIG. 3 is a graph of stress and strain for group III nitrides at different V/III ratios.
FIG. 4 is a schematic diagram of the round bottom of the insulating substrate in FIG. 2;
FIG. 5 is a schematic perspective view of an insulating substrate with circular holes, hexagonal holes and triangular holes;
wherein, 1, insulating substrate; 2. and (5) an epitaxial structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the description of the exemplary embodiments of the present invention is only for explaining the present invention and is not to be construed as limiting the present invention.
Example (b):
referring to fig. 1 and 2, a method for preparing a low stress semiconductor material includes the following steps:
s1: covering a layer of mask with a hollowed-out etching pattern on the upper surface of an insulating substrate 1, placing the insulating substrate 1 in a reactor with two electrode plates, vacuumizing the reactor, oppositely arranging the two electrode plates, placing the insulating substrate 1 between the two electrode plates, and enabling the surface of the insulating substrate 1 with the mask to be parallel to the two electrode plates;
the material of the insulating substrate 1 selected in this embodiment is any one or a composite substrate of two or more of Si, GaAs, GaN, sapphire, and SiC.
S2: introducing etching gas into the reactor, applying electric fields to the two sides of the upper surface and the lower surface of the insulating substrate 1 to ionize the etching gas and bombard the upper surface of the insulating substrate 1 with the mask, and etching the pattern of the insulating substrate 1;
the etching gas in this embodiment is any one of single gas or a combination of two or more of H2, NH3, HCl, BCl3, and Ar; the temperature of etching gas in the reactor is 800-2000 ℃; the surface etching of any one or more than two composite substrates of Si, GaAs, GaN, sapphire and SiC is realized; the etched pattern of the insulating substrate 1 is one or more than two of round bottom, cylinder, round hole, hexagonal hole or triangular hole, the pattern is periodically distributed, the period is 0.5-3um, and the pattern depth is 0.1-10 um. This embodiment uses an insulating substrate with a circular hole and a round bottom as shown in fig. 2 and 4. In addition, the pattern on the insulating substrate can also be an insulating substrate with round holes, hexagonal holes and triangular holes (as shown in fig. 5), and the etching forming of different substrate patterns can be realized only by controlling the etching position of etching gas.
The mask with the hollow pattern covers the surface of the insulating substrate 1, and plays a role in protecting the area of the insulating substrate 1 which does not need to be etched; and adjusting the direction of the external electric field, so that after the external electric field is applied to two sides of the insulating substrate 1, ionized gas moves at a high speed towards the surface of the insulating substrate 1 with the mask, thus bombarding the insulating substrate 1 under the area without the mask coverage or the mask hollow-out area, reacting with the surface molecules of the insulating substrate 1 in the bombarded area, and discharging the reaction product as waste gas, thereby realizing the etching of the surface pattern of the insulating substrate 1.
S3: taking out the etched insulating substrate 1, and removing the mask on the upper surface of the insulating substrate 1;
s4: and sequentially growing a plurality of epitaxial structures 2 of the semiconductor epitaxial layers on the surface of the insulating substrate 1 with the etching patterns, wherein the semiconductor epitaxial layers with compressive stress and the semiconductor epitaxial layers with tensile stress are periodically changed, and the stress of the whole epitaxial structure 2 is close to zero.
Generating an etching pattern on the insulating substrate 1, thereby reducing the stress between the insulating substrate 1 and the epitaxial structure 2; by arranging one or more stress epitaxial layers opposite to the two epitaxial layers with the same stress between the two epitaxial layers, irregular tiny holes (1-20nm in size and 1-50nm in depth) capable of growing and healing are generated, the healing process reduces the densities of the edge dislocation and the screw dislocation simultaneously; line defects at the interface change by 50-90 degrees: under the condition of continuous modulation of the growth mode, the line defects deflect along two stress growth interfaces, and the deflection degree of the line defects is related to the V/III ratio and the thickness and thickness ratio of the tensile stress layer and the compressive stress layer, so that the final stress of the whole epitaxial material tends to zero.
Referring to fig. 2, in order to make the stress of the whole epitaxial structure 2 close to zero, the semiconductor epitaxial layer with compressive stress and the semiconductor epitaxial layer with tensile stress are arranged at intervals, that is, in each growth cycle, the first semiconductor epitaxial layer has either compressive stress or tensile stress, and the second semiconductor epitaxial layer has either tensile stress or stress opposite to the first semiconductor epitaxial layer. The combination of a series of epitaxial periodic structures brings the stress of the overall epitaxial structure 2 close to zero, thereby reducing the cracking and linear defect density of the material.
FIG. 3 is a stress and strain curve of III-nitride at different V/III ratios, which shows that the stress of the grown epitaxial layer of the semiconductor is close to zero when the V/III ratio is about 1500; when the V/III ratio is in the range of 1-1500, the grown semiconductor epitaxial layer shows compressive stress, and when the V/III ratio is more than 1500, the grown semiconductor epitaxial layer shows tensile stress. In the embodiment, before the growth of the first semiconductor epitaxial layer, the surface of the insulating substrate 1 is treated at high temperature by adopting metal organic source III group elements in advance so as to reduce stress and grow a high-quality, low-dislocation and zero-stress III-V semiconductor material; growing each semiconductor epitaxial layer in a growth chamber by vapor deposition, introducing gaseous III-group nitride and V-group nitride during growth, wherein the carrier gas is nitrogen, and the gas pressure in the growth chamber is 10-2500 torr. Wherein, in the growth process of the semiconductor epitaxial layer with the compressive stress, the molar ratio of the V-group nitride to the III-group nitride is 5-1000, and the growth temperature of the compressive stress layer is regulated within the range of 200-1100 ℃; in the growth process of the semiconductor epitaxial layer with tensile stress, the molar ratio of the group V nitride to the group III nitride is 2000-5000, and the regulation range of the growth temperature of the tensile stress layer is 1200-1600 ℃.
The above is an embodiment of the present invention. The embodiments and specific parameters in the embodiments are only for the purpose of clearly illustrating the verification process of the invention and are not intended to limit the scope of the invention, which is defined by the claims, and all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be covered by the scope of the present invention.
Claims (2)
1. A preparation method of a low-stress semiconductor material is characterized by comprising the following steps:
s1: covering a layer of mask with a hollowed-out etching pattern on the upper surface of an insulating substrate, placing the insulating substrate in a reactor with two electrode plates, vacuumizing the reactor, wherein the two electrode plates are oppositely arranged, the insulating substrate is placed between the two electrode plates, and the surface of the insulating substrate with the mask is parallel to the two electrode plates;
s2: introducing etching gas into the reactor, applying an electric field to two sides of the upper surface and the lower surface of the insulating substrate to ionize the etching gas and bombard the upper surface of the insulating substrate with the mask, and etching the pattern of the insulating substrate;
s3: taking out the etched insulating substrate, and removing the mask on the upper surface of the insulating substrate;
s4: sequentially growing a plurality of epitaxial structures of semiconductor epitaxial layers on the surface of the insulating substrate with the etching patterns, wherein the semiconductor epitaxial layers with compressive stress and the semiconductor epitaxial layers with tensile stress are periodically changed, and the stress of the whole epitaxial structure is close to zero;
in the growth process of the semiconductor epitaxial layer with the compressive stress, the molar ratio of the V group to the III group is 5-1000, and the growth temperature of the compressive stress layer is regulated within the range of 200-1100 ℃;
in the growth process of the semiconductor epitaxial layer with tensile stress, the molar ratio of the group V to the group III is 2000-5000, and the growth temperature of the tensile stress layer is adjusted within the range of 1200-1600 ℃;
the insulating substrate is a composite substrate made of any one or more of Si, GaAs, GaN, sapphire and SiC;
the etching gas in the step S2 is any one of H2, NH3, HCl, BCl3, and Ar, or a combination of two or more atmospheres; the temperature of etching gas in the reactor is 800-2000 ℃;
in the step S2, the etching pattern of the insulating substrate is one or more than two of round holes, hexagonal holes or triangular holes, the patterns are distributed periodically, the period is 0.5-3um, and the pattern depth is 0.1-10 um;
in step S4, the respective semiconductor epitaxial layers are grown by vapor deposition in the growth chamber.
2. The method for preparing a low-stress semiconductor material according to claim 1, wherein: before the growth of the first semiconductor epitaxial layer in step S4, the surface of the insulating substrate is treated at a high temperature in advance with a metal-organic source group III element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911041382.1A CN110783176B (en) | 2019-10-30 | 2019-10-30 | Preparation method of low-stress semiconductor material |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911041382.1A CN110783176B (en) | 2019-10-30 | 2019-10-30 | Preparation method of low-stress semiconductor material |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110783176A CN110783176A (en) | 2020-02-11 |
| CN110783176B true CN110783176B (en) | 2022-07-12 |
Family
ID=69387515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911041382.1A Active CN110783176B (en) | 2019-10-30 | 2019-10-30 | Preparation method of low-stress semiconductor material |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110783176B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111948235B (en) * | 2020-08-07 | 2022-09-20 | 广西大学 | Method for measuring semipolar plane III group nitride film defect density and application thereof |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59175087A (en) * | 1983-03-24 | 1984-10-03 | Fujitsu Ltd | Production of magnetic bubble memory element |
| CN1347581A (en) * | 1999-03-26 | 2002-05-01 | 松下电器产业株式会社 | Semiconductor structures having strain compensated layer and method of fabrication |
| CN101140865A (en) * | 2007-09-17 | 2008-03-12 | 高英 | III nitride semi-conductor material and growing method thereof |
| CN102714136A (en) * | 2009-09-10 | 2012-10-03 | 奥普特冈有限公司 | A method for reducing internal mechanical stresses in a semiconductor structure and a low mechanical stress semiconductor structure |
| CN102760794A (en) * | 2011-04-29 | 2012-10-31 | 山东华光光电子有限公司 | Preparation method of low-stress gallium nitride epitaxial layer |
| CN103614769A (en) * | 2013-10-25 | 2014-03-05 | 中国电子科技集团公司第五十五研究所 | Gallium nitride homoepitaxy method based on in situ etching |
| CN105006505A (en) * | 2014-04-15 | 2015-10-28 | 传感器电子技术股份有限公司 | Semiconductor heterostructure with stress management |
| CN106783533A (en) * | 2016-11-11 | 2017-05-31 | 上海芯元基半导体科技有限公司 | Nitride semiconductor structure containing Al and its epitaxial growth method |
| CN107810544A (en) * | 2015-06-03 | 2018-03-16 | 维易科仪器有限公司 | The Stress Control of hetero-epitaxy |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1138192A (en) * | 1997-07-17 | 1999-02-12 | Nikon Corp | Multiple layer film reflection mirror |
| WO2000021121A1 (en) * | 1998-10-05 | 2000-04-13 | Seiko Epson Corporation | Semiconductor device and method for producing the same |
| JP3770014B2 (en) * | 1999-02-09 | 2006-04-26 | 日亜化学工業株式会社 | Nitride semiconductor device |
| JP4975974B2 (en) * | 2005-03-18 | 2012-07-11 | ラピスセミコンダクタ株式会社 | SOS wafer and manufacturing method thereof |
| KR102002898B1 (en) * | 2012-09-04 | 2019-07-23 | 삼성전자 주식회사 | The semiconductor buffer structure and semiconductor device having the same |
| TWI657578B (en) * | 2014-11-07 | 2019-04-21 | 日商住友化學股份有限公司 | Semiconductor substrate and method for examining semiconductor substrate |
| US10510538B2 (en) * | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing EUV-induced material property changes |
| CN109638117B (en) * | 2018-11-29 | 2021-06-11 | 华灿光电（浙江）有限公司 | AlN template, epitaxial wafer structure and manufacturing method |
-
2019
- 2019-10-30 CN CN201911041382.1A patent/CN110783176B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59175087A (en) * | 1983-03-24 | 1984-10-03 | Fujitsu Ltd | Production of magnetic bubble memory element |
| CN1347581A (en) * | 1999-03-26 | 2002-05-01 | 松下电器产业株式会社 | Semiconductor structures having strain compensated layer and method of fabrication |
| CN101140865A (en) * | 2007-09-17 | 2008-03-12 | 高英 | III nitride semi-conductor material and growing method thereof |
| CN102714136A (en) * | 2009-09-10 | 2012-10-03 | 奥普特冈有限公司 | A method for reducing internal mechanical stresses in a semiconductor structure and a low mechanical stress semiconductor structure |
| CN102760794A (en) * | 2011-04-29 | 2012-10-31 | 山东华光光电子有限公司 | Preparation method of low-stress gallium nitride epitaxial layer |
| CN103614769A (en) * | 2013-10-25 | 2014-03-05 | 中国电子科技集团公司第五十五研究所 | Gallium nitride homoepitaxy method based on in situ etching |
| CN105006505A (en) * | 2014-04-15 | 2015-10-28 | 传感器电子技术股份有限公司 | Semiconductor heterostructure with stress management |
| CN107810544A (en) * | 2015-06-03 | 2018-03-16 | 维易科仪器有限公司 | The Stress Control of hetero-epitaxy |
| CN106783533A (en) * | 2016-11-11 | 2017-05-31 | 上海芯元基半导体科技有限公司 | Nitride semiconductor structure containing Al and its epitaxial growth method |
Non-Patent Citations (1)
| Title |
|---|
| 氮化硅薄膜的应力与性能控制;周东等;《电子器件》;20100820(第04期);正文全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110783176A (en) | 2020-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5760426A (en) | Heteroepitaxial semiconductor device including silicon substrate, GaAs layer and GaN layer #13 | |
| KR100518353B1 (en) | Semiconductor substrate made of group III nitride, and process for manufacture thereof | |
| EP2037013B1 (en) | Method for preparing substrate for growing gallium nitride and method for preparing gallium nitride substrate | |
| KR101380717B1 (en) | Semi-conductor substrate and method and masking layer for producing a free-standing semi-conductor substrate by means of hydride-gas phase epitaxy | |
| US20090087937A1 (en) | Method for manufacturing nitride based single crystal substrate and method for manufacturing nitride based light emitting diode using the same | |
| KR20100092932A (en) | Semiconductor substrate and method for manufacturing semiconductor substrate | |
| EP1298709B1 (en) | Method for producing a iii nitride element comprising a iii nitride epitaxial substrate | |
| KR20000005908A (en) | Multilayered indium-containing nitride buffer layer for nitride epitaxy | |
| KR100569796B1 (en) | Recovery of surface-ready silicon carbide substrates | |
| US5356510A (en) | Method for the growing of heteroepitaxial layers | |
| KR20140107797A (en) | Method of fabricating nitride substrate | |
| WO2001059819A1 (en) | Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby | |
| CN110783176B (en) | Preparation method of low-stress semiconductor material | |
| KR100331447B1 (en) | Method for fabricating a thick GaN film | |
| KR100450781B1 (en) | Method for manufacturing GaN single crystal | |
| KR19990083174A (en) | Method for growing nitride compound semiconductor | |
| WO2004019390A3 (en) | Mbe growth of an algan layer or algan multilayer structure | |
| US20050211988A1 (en) | Method for production of a layer of silicon carbide or a nitride of a group III element on a suitable substrate | |
| Maruyama et al. | Domain structures of CdTe layers grown by MOCVD on offset-angle sapphire substrates | |
| JP6795123B1 (en) | Semiconductor wafer and its manufacturing method | |
| CN106784228A (en) | Nonpolar a faces AlN films based on r faces SiC graph substrates and preparation method thereof | |
| KR100643155B1 (en) | Method of preparing silicon substrate-gallium nitride thin film laminated body | |
| EP1658394B1 (en) | Method to manufacture indium nitride quantum dots and product containing these dots | |
| JP3743013B2 (en) | Epitaxial wafer manufacturing method | |
| JP2001288000A (en) | Method for producing semiconductor thin film crystal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |