CN110780840A - Method and system for implementing multi-path sequencer - Google Patents
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/06—Arrangements for sorting, selecting, merging, or comparing data on individual record carriers
- G06F7/08—Sorting, i.e. grouping record carriers in numerical or other ordered sequence according to the classification of at least some of the information they carry
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Abstract
The application discloses a method and a system for realizing a multi-channel sequencer, wherein the method comprises the following steps: respectively putting data to be sorted into different registers; respectively reading data in the registers; solving the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data; respectively storing the minimum value data and the positions corresponding to the minimum value data to a shift register; judging whether the cycle number is smaller than a preset value, wherein the cycle number is the number of times of solving the minimum value data; if the cycle number is smaller than the preset value, excluding the register where the minimum data is located, and continuously solving the minimum value in the data; and if the circulation times are larger than or equal to the preset value, stopping circulation to obtain the sequenced data. The method adopts the minimum value to replace the actual sequencing operation, and the shift register carries out shift register on the minimum value obtained each time, so that the method consumes less logic resources, well balances the calculation delay and the logic resources, and greatly reduces the cost.
Description
Technical Field
The present application relates to the field of electronic circuits and semiconductor technologies, and in particular, to a method and a system for implementing a multi-way sequencer.
Background
Sorting is an operation that arranges a string of records in ascending or descending order according to the size of some keyword or keywords, and is widely used in automatic control, web searching, office document operation and the like. A sorting algorithm is how to make the records arranged as desired.
Classical sorting algorithms are bubble sorting, selection sorting, insertion sorting, etc., wherein bubble sorting is a simple sorting algorithm that repeatedly walks through the series to be sorted, compares two elements at a time, swaps them if their order is wrong, and repeats the task of walking through the series until no more elements need to be swapped, i.e., the series has been sorted; the selection sorting is one of the most stable sorting algorithms, and the working principle is as follows: firstly, finding the minimum (large) element in the unsorted sequence, storing the minimum (large) element to the initial position of the sorted sequence, then continuously searching the minimum (large) element from the rest unsorted elements, then placing the minimum (large) element to the tail of the sorted sequence, and so on until all the elements are sorted; the insert sorting is a simple and intuitive sorting algorithm, and the working principle of the insert sorting is as follows: by constructing an ordered sequence, for the data that is not ordered, the data is scanned from back to front in the ordered sequence, and the corresponding position is found and inserted.
However, most of these sorting algorithms are suitable for being implemented by software, and if these algorithms are implemented by an RTL hardware circuit, a contradiction between processing delay and logic resources occurs, that is, the sorting algorithm with a small computation delay consumes very large logic resources, and the sorting algorithm with a small computation delay consumes very large computation delay, so that the classical sorting algorithm cannot achieve a good balance between logic resources and computation delay.
Disclosure of Invention
The application provides a method and a system for realizing a multi-path sequencer, which are used for solving the problem that the conventional sequencing algorithm cannot achieve good balance between logic resources and calculation delay.
In order to solve the technical problem, the embodiment of the application discloses the following technical scheme:
in a first aspect, an embodiment of the present application discloses a method for implementing a multi-way sequencer, where the method includes:
s1: respectively putting data to be sorted into different registers;
s2: respectively reading the data in the registers;
s3: solving the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data;
s4: storing the positions corresponding to the minimum value data and the minimum value data to a shift register respectively;
s5: judging whether the cycle number is smaller than a preset value, if so, executing step S6; if not, go to step S7; wherein the cycle number is the number of times of obtaining minimum value data;
s6: excluding the register where the minimum data is located, and continuing to execute S2, S3, S4 and S5;
s7: and stopping circulation to obtain the sequenced data.
Optionally, the obtaining of the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data includes:
acquiring the minimum value of the data in the register;
and acquiring the position corresponding to the minimum data according to the minimum data.
Optionally, storing the minimum value data and the corresponding positions of the minimum value data to a shift register respectively includes:
acquiring cycle times corresponding to the minimum data;
and respectively storing the minimum value data and the positions corresponding to the minimum value data to a first shift register and a second shift register according to the cycle times.
Optionally, the excluding processing is performed on the register where the minimum value data is located, and includes:
and replacing the data in the register where the minimum value data is located with an infinite value.
Optionally, the excluding processing is performed on the register where the minimum value data is located, and includes:
and deleting the data in the register of the minimum data.
In a second aspect, an embodiment of the present application further discloses an implementation system of a multi-way sequencer, including:
the register is used for storing data to be sorted;
the minimum value acquisition module is used for solving the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data;
the shift register is used for respectively storing the minimum value data and the position corresponding to the minimum value data;
the judging module is used for judging whether the cycle number is smaller than a preset value, wherein the cycle number is the number of times of solving minimum value data;
the exclusion processing module is used for excluding the register where the minimum data is located when the cycle number is smaller than the preset value;
and the circulation stopping module is used for stopping circulation when the circulation times are greater than or equal to the preset value to obtain the sequenced data.
Optionally, the shift register includes:
the first shift register is used for storing the minimum value data according to the cycle number corresponding to the minimum value data;
and the second shift register is used for storing the position corresponding to the minimum value data according to the cycle number corresponding to the minimum value data.
Optionally, the excluding processing module includes:
and the replacing module is used for replacing the data in the register where the minimum value data is located with an infinite value.
Optionally, the excluding processing module includes:
and the deleting module is used for deleting the data in the register where the minimum data is located.
Compared with the prior art, the beneficial effect of this application is:
the implementation method of the multi-way sequencer provided by the embodiment of the application comprises the following steps: respectively putting data to be sorted into different registers; respectively reading data in the registers; solving the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data; storing the minimum value data and the positions corresponding to the minimum value data to a register respectively; judging whether the cycle number is smaller than a preset value, wherein the cycle number is the number of times of solving minimum value data; if the cycle number is smaller than the preset value, excluding the register where the minimum value data is located, and continuously obtaining the minimum value data and other operations; and if the circulation times are larger than or equal to the preset value, stopping circulation to obtain the sequenced data. The implementation method of the multi-channel sequencer provided by the application adopts the multi-channel minimum value acquisition to replace the actual sequencing operation, and the minimum value acquired each time is subjected to shift register by the shift register, so that the method consumes less logic resources, has moderate logic processing delay, can well balance the calculation delay and the logic resources, and greatly reduces the cost.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly explain the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of an implementation method of a multi-way sequencer according to an embodiment of the present application;
fig. 2 is a block diagram of an implementation system of a multi-way sequencer according to an embodiment of the present application;
fig. 3 is a block diagram of an implementation system of another multi-way sequencer according to an embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, a flowchart of an implementation method of a multi-way sequencer according to an embodiment of the present application is provided.
As shown in fig. 1, an implementation method of a multi-way sequencer provided in the embodiment of the present application includes:
s1: and respectively putting the data to be sorted into different registers.
The present application is explained with a 64-way sequencer, and 64 data1-data64 are respectively temporarily stored in 64 registers.
S2: the data in the registers are read separately.
And reading the data in the registers as required, and if 64 data are required to be sequenced, respectively reading 64 data from the 64 registers.
S3: and calculating the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data.
The read data (64 data) are input to the minimum value obtainer, and the minimum value data min _ data and the position min _ data _ id corresponding to the minimum value data in the 64 data are obtained, and if the minimum value is 2, the minimum value is located in the 15 th register.
S4: and respectively storing the positions corresponding to the minimum value data and the minimum value data to the shift register.
After the positions corresponding to the minimum value data and the minimum value data in the 64 data are obtained, the positions are respectively stored into a shift register, the positions can be stored to the first bit or the last bit of the shift register according to the sorting requirement, and if 64 paths of data are sorted from large to small, the positions corresponding to the minimum value data and the minimum value data in the 64 paths of data are respectively stored to the last bit of the shift register; and sequencing the 64 paths of data from small to large, and respectively storing the positions corresponding to the minimum value data and the minimum value data in the 64 paths of data to the first bit of the shift register.
In this example, the minimum value data and the position corresponding to the minimum value data can be respectively stored in the first shift register and the second shift register through the cycle number corresponding to the minimum value data, if the cycle number corresponding to the minimum value data obtained this time is 2, that is, the minimum value of the data is obtained for the second time, if 64-channel data are sorted from large to small, the minimum value data is stored to the 2 nd bit on the right of the first shift register, and the position corresponding to the minimum value data is stored to the 2 nd bit on the right of the second shift register; if 64-path data are sorted from small to large, the minimum value data is stored to the 2 nd bit on the left side of the first shift register, and the position corresponding to the minimum value data is stored to the 2 nd bit on the left side of the second shift register.
S5: judging whether the cycle number is smaller than a preset value, if so, executing step S6; if not, go to step S7; the number of cycles is the number of times of obtaining the minimum value data.
Adding 1 to the cycle number each time the minimum value data and the position corresponding to the minimum value data are obtained, if 64 data are to be sequenced, setting the preset value to 64, and judging whether the cycle number is smaller than 64; if the data does not need to be sorted, only a part of the data needs to be selected to obtain the minimum value, for example, 24 data, the preset value is only required to be set to 24. If the cycle number is less than the preset value, executing S6; if the number of cycles is greater than or equal to the preset value, S7 is executed.
S6: the exclusion processing is performed on the register where the minimum value data is located, and the execution continues to S2, S3, S4, and S5.
If the cycle number of the minimum value data is less than the preset value, if the minimum value is first obtained for 64 paths of data, namely the cycle number is less than the preset value 64, the register where the minimum value data is located is excluded, S2, S3, S4 and S5 are continuously executed, namely the data in the register are read again, the minimum value in the data is obtained, the position corresponding to the minimum value data and the position corresponding to the minimum value data are obtained, the positions corresponding to the minimum value data and the position corresponding to the minimum value data are respectively stored in the first shift register and the second shift register, and whether the cycle number is less than the preset value or not is judged.
When the exclusion processing is performed on the register in which the minimum value data is located, the data in the register in which the minimum value data is located may be replaced with an infinite value. If the data in the register where the minimum value data is obtained for the first time is replaced by the infinite value, then 64 paths of data containing the infinite value in the register are read, the minimum value in the 64 paths of data is obtained again, the position corresponding to the minimum value data and the minimum value data for the second time is obtained, and the position corresponding to the minimum value data and the minimum value data for the second time is respectively stored to the second bit or the second last bit of the first shift register and the second shift register according to the sorting requirement.
When the exclusion processing is performed on the register in which the minimum value data is located, the data in the register in which the minimum value data is located may be deleted. If the data in the register where the minimum value data is obtained for the first time is deleted, only 63 registers have data, then the data in the 63 registers are read, the minimum value in 63 paths of data is obtained, the positions corresponding to the minimum value data and the minimum value data for the second time are obtained, and the positions corresponding to the minimum value data and the minimum value data for the second time are respectively stored to the second bit or the last but one bit of the first shift register and the second shift register according to the sorting requirement.
And performing 64 cycles on S2, S3, S4, S5 and S6 according to the method to obtain 64 minimum value data and positions corresponding to the minimum value data, and storing the 64 minimum value data and the minimum value data into the first shift register and the second shift register respectively according to the sorting requirement.
The method for acquiring the minimum value data and the corresponding position of the minimum value data64 times is not limited to the above method, and the method only needs to circularly obtain the minimum value data and the corresponding position of the minimum value data each time, and all the methods belong to the protection scope of the embodiment of the present application.
S7: and stopping circulation to obtain the sequenced data.
If the cycle number of the acquired minimum value data is larger than or equal to a preset value, stopping the cycle, and at the moment, the content in the shift register is the sequenced data, thus finishing the sequencing of 64 paths of data.
The implementation method of the multi-channel sequencer provided by the embodiment of the application adopts the mode of obtaining 64 paths of minimum values to replace actual sequencing operation, only the minimum value in 64 paths of data is obtained each time, the minimum value obtained each time is subjected to shift register by a shift register, the content of the corresponding position of the register is required to be modified in time (the data in the corresponding register is replaced or deleted by infinity) after the minimum value is obtained each time, so that consumed logic resources are few, only 64 registers, 1 64 paths of minimum value obtainers and 2 rows of shift registers are needed, the logic processing delay is moderate, the calculation delay and the logic resources are well balanced, the structure is novel and simple, the area is saved, and the cost is greatly reduced.
Based on the implementation method of the multi-way sorter described in the above embodiment, the embodiment of the present application further provides an implementation system of the multi-way sorter.
As shown in fig. 2 and fig. 3, an implementation system of a multi-way sequencer provided in the embodiment of the present application includes:
and the register is used for storing the data to be sorted. In this example, 64 registers are needed to temporarily store 64 data1-data64 respectively.
And the minimum value acquisition module is used for solving the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data.
And the shift register is used for respectively storing the minimum value data and the position corresponding to the minimum value data. In this example, the shift register includes a first shift register and a second shift register, wherein,
and the first shift register is used for storing the minimum value data according to the cycle number corresponding to the minimum value data. In this example, after the cycle number corresponding to the minimum value data is obtained, the minimum value data is stored in the first shift register according to the cycle number, and if 64-way data is sorted from small to large, the minimum value data is stored in a corresponding position on the left side of the first shift register according to the cycle number. If 64-path data are sorted from large to small, the minimum value data are stored to the corresponding position on the right side of the first shift register according to the cycle times.
And the second shift register is used for storing the position corresponding to the minimum value data according to the cycle number corresponding to the minimum value data. In this example, after the cycle number corresponding to the minimum value data is obtained, the position corresponding to the minimum value data is stored in the second shift register according to the cycle number, and if 64-way data is sorted from small to large, the position corresponding to the minimum value data is stored in the corresponding position on the left side of the second shift register according to the cycle number. And if the 64-path data are sorted from large to small, storing the position corresponding to the minimum data to the corresponding position on the right side of the second shift register according to the cycle times.
And the judging module is used for judging whether the cycle number is smaller than a preset value, wherein the cycle number is the number of times of solving the minimum value data.
And the exclusion processing module is used for performing exclusion processing on the register where the minimum data is located when the cycle number is smaller than a preset value. The exclusion processing module may include a replacement module or a deletion module.
And the replacing module is used for replacing the data in the register with the minimum value data into an infinite value, namely replacing the data in the register with the minimum value data into the infinite value according to the obtained minimum value data, then reading the data in the replaced register, re-obtaining the minimum value in the data, obtaining the positions corresponding to the minimum value data and the minimum value data, and respectively storing the positions corresponding to the minimum value data and the minimum value data into the first shift register and the second shift register.
And the deleting module is used for deleting the data in the register in which the minimum value data is located, namely deleting the data in the register in which the minimum value data is located according to the obtained minimum value data, reading the data in the rest registers, re-obtaining the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data, and respectively storing the positions corresponding to the minimum value data and the minimum value data to the first shift register and the second shift register.
The implementation system of the multi-channel sequencer provided by the embodiment of the application consumes less logic resources, only a plurality of registers, 1 minimum value acquirer and 2 rows of shift registers are needed, the logic processing delay is moderate, the delay and the logic resources can be well balanced and calculated, and the cost is greatly reduced.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
The above-described embodiments of the present application do not limit the scope of the present application.
Claims (9)
1. A method for implementing a multi-way sequencer, the method comprising:
s1: respectively putting data to be sorted into different registers;
s2: respectively reading the data in the registers;
s3: solving the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data;
s4: storing the positions corresponding to the minimum value data and the minimum value data to a shift register respectively;
s5: judging whether the cycle number is smaller than a preset value, if so, executing step S6; if not, go to step S7; wherein the cycle number is the number of times of obtaining minimum value data;
s6: excluding the register where the minimum data is located, and continuing to execute S2, S3, S4 and S5;
s7: and stopping circulation to obtain the sequenced data.
2. The method of claim 1, wherein obtaining the minimum value in the data to obtain the minimum value data and a position corresponding to the minimum value data comprises:
acquiring the minimum value of the data in the register;
and acquiring the position corresponding to the minimum data according to the minimum data.
3. The method according to claim 1, wherein storing the positions corresponding to the minimum value data and the minimum value data in shift registers, respectively, comprises:
acquiring cycle times corresponding to the minimum data;
and respectively storing the minimum value data and the positions corresponding to the minimum value data to a first shift register and a second shift register according to the cycle times.
4. The method of claim 1, wherein excluding the register in which the minimum value data is located comprises:
and replacing the data in the register where the minimum value data is located with an infinite value.
5. The method of claim 1, wherein excluding the register in which the minimum value data is located comprises:
and deleting the data in the register of the minimum data.
6. A system for implementing a multi-way sequencer, comprising:
the register is used for storing data to be sorted;
the minimum value acquisition module is used for solving the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data;
the shift register is used for respectively storing the minimum value data and the position corresponding to the minimum value data;
the judging module is used for judging whether the cycle number is smaller than a preset value, wherein the cycle number is the number of times of solving minimum value data;
the exclusion processing module is used for excluding the register where the minimum data is located when the cycle number is smaller than the preset value;
and the circulation stopping module is used for stopping circulation when the circulation times are greater than or equal to the preset value to obtain the sequenced data.
7. The system of claim 6, wherein the shift register comprises:
the first shift register is used for storing the minimum value data according to the cycle number corresponding to the minimum value data;
and the second shift register is used for storing the position corresponding to the minimum value data according to the cycle number corresponding to the minimum value data.
8. The system of claim 6, wherein the exclusion processing module comprises:
and the replacing module is used for replacing the data in the register where the minimum value data is located with an infinite value.
9. The system of claim 6, wherein the exclusion processing module comprises:
and the deleting module is used for deleting the data in the register where the minimum data is located.
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