CN110780840B - Method and system for realizing multipath sequencer - Google Patents
Method and system for realizing multipath sequencer Download PDFInfo
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- CN110780840B CN110780840B CN201911047883.0A CN201911047883A CN110780840B CN 110780840 B CN110780840 B CN 110780840B CN 201911047883 A CN201911047883 A CN 201911047883A CN 110780840 B CN110780840 B CN 110780840B
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- 230000008030 elimination Effects 0.000 claims description 8
- 238000003379 elimination reaction Methods 0.000 claims description 8
- 230000007717 exclusion Effects 0.000 claims description 5
- 238000004364 calculation method Methods 0.000 abstract description 5
- 238000012163 sequencing technique Methods 0.000 abstract description 4
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/06—Arrangements for sorting, selecting, merging, or comparing data on individual record carriers
- G06F7/08—Sorting, i.e. grouping record carriers in numerical or other ordered sequence according to the classification of at least some of the information they carry
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a method and a system for realizing a multipath sequencer, wherein the method comprises the following steps: respectively placing the data to be sequenced into different registers; respectively reading data in the registers; obtaining the minimum value in the data, and obtaining the minimum value data and the position corresponding to the minimum value data; storing the positions corresponding to the minimum value data to the shift register respectively; judging whether the cycle number is smaller than a preset value, wherein the cycle number is the number of times of obtaining minimum value data; if the cycle times are smaller than the preset value, eliminating the register where the minimum value data are located, and continuously obtaining the minimum value in the data; if the cycle times are greater than or equal to the preset value, stopping the cycle to obtain the ordered data. The method adopts the obtained minimum value to replace the actual sequencing operation, and the shift register is used for carrying out shift register on the obtained minimum value each time, so that the method consumes less logic resources, well balances the calculation delay and the logic resources and greatly reduces the cost.
Description
Technical Field
The present application relates to the field of electronic circuits and semiconductor technologies, and in particular, to a method and a system for implementing a multi-way sequencer.
Background
Ranking is an operation of arranging a series of records in increments or decrements according to the size of one or more keywords therein, which is used in a large number of automatic controls, web page searches, office document operations, and the like. A ranking algorithm is a method of how records are ranked as desired.
Classical sorting algorithms are bubble sorting, select sorting, insert sorting, etc., wherein bubble sorting is a simple sorting algorithm that repeatedly walks through the columns to be sorted, compares two elements at a time, swaps them if their order is wrong, and walks through the work of the columns repeatedly until no more elements need to be swapped, i.e. the columns have been sorted; the selection ordering is one of the ordering algorithms which are the most stable in performance, and the working principle is as follows: firstly, finding the smallest (big) element in an unordered sequence, storing the smallest (big) element in the initial position of the ordered sequence, then continuously searching the smallest (big) element from the rest unordered elements, then placing the smallest (big) element at the end of the ordered sequence, and the like until all the elements are ordered; the insertion ordering is a simple and visual ordering algorithm, and the working principle is as follows: by constructing an ordered sequence, for the unordered data, scan back-to-front in the ordered sequence, find the corresponding position and insert.
However, most of these sorting algorithms are suitable for being implemented in a software manner, if these algorithms are implemented by using RTL hardware circuits, contradiction between processing delay and logic resources will occur, that is, the sorting algorithm with small computing delay consumes very large logic resources, the sorting algorithm with small computing delay consumes very large computing delay, and the classical sorting algorithm cannot achieve very good balance between logic resources and computing delay.
Disclosure of Invention
The application provides a method and a system for realizing a multipath sequencer, which are used for solving the problem that the conventional classical sequencing algorithm cannot achieve good balance between logic resources and calculation delay.
In order to solve the technical problems, the embodiment of the application discloses the following technical scheme:
in a first aspect, an embodiment of the present application discloses a method for implementing a multi-way sequencer, where the method includes:
s1: respectively placing the data to be sequenced into different registers;
s2: respectively reading the data in the registers;
s3: obtaining the minimum value in the data to obtain minimum value data and the position corresponding to the minimum value data;
s4: storing the positions corresponding to the minimum value data to a shift register respectively;
s5: judging whether the cycle times are smaller than a preset value, if yes, executing a step S6; if not, executing the step S7; wherein the cycle number is the number of times of obtaining minimum value data;
s6: performing elimination processing on a register where the minimum value data is located, and continuously executing S2, S3, S4 and S5;
s7: and stopping the circulation to obtain the ordered data.
Optionally, the calculating the minimum value in the data to obtain the minimum value data and the position corresponding to the minimum value data includes:
acquiring the minimum value of the data in the register;
and acquiring the position corresponding to the minimum value data according to the minimum value data.
Optionally, storing the minimum value data and the positions corresponding to the minimum value data in a shift register respectively includes:
acquiring the circulation times corresponding to the minimum value data;
and respectively storing the minimum value data and the positions corresponding to the minimum value data into a first shift register and a second shift register according to the cycle times.
Optionally, the excluding the register where the minimum value data is located includes:
and replacing the data in the register where the minimum value data is located with an infinite value.
Optionally, the excluding the register where the minimum value data is located includes:
and deleting the data in the register where the minimum value data is located.
In a second aspect, an embodiment of the present application further discloses a system for implementing a multi-way sequencer, including:
a register for storing data to be ordered;
the minimum value acquisition module is used for obtaining the minimum value in the data to obtain minimum value data and the position corresponding to the minimum value data;
the shift register is used for respectively storing the minimum value data and the positions corresponding to the minimum value data;
the judging module is used for judging whether the cycle number is smaller than a preset value, wherein the cycle number is the number of times of obtaining minimum value data;
the elimination processing module is used for eliminating the register where the minimum value data is located when the cycle times are smaller than the preset value;
and the circulation stopping module is used for stopping circulation when the circulation times are greater than or equal to the preset value, and obtaining ordered data.
Optionally, the shift register includes:
the first shift register is used for storing the minimum value data according to the cycle times corresponding to the minimum value data;
and the second shift register is used for storing the position corresponding to the minimum value data according to the cycle times corresponding to the minimum value data.
Optionally, the exclusion processing module includes:
and the replacing module is used for replacing the data in the register where the minimum value data is located with an infinite value.
Optionally, the exclusion processing module includes:
and the deleting module is used for deleting the data in the register where the minimum value data are located.
Compared with the prior art, the application has the beneficial effects that:
the implementation method of the multipath sequencer provided by the embodiment of the application comprises the following steps: respectively placing the data to be sequenced into different registers; respectively reading data in the registers; obtaining the minimum value in the data, and obtaining the minimum value data and the position corresponding to the minimum value data; storing the positions corresponding to the minimum value data to the register respectively; judging whether the cycle number is smaller than a preset value, wherein the cycle number is the number of times of obtaining minimum value data; if the cycle times are smaller than the preset value, eliminating the register where the minimum value data are located, and continuing to obtain the minimum value data and other operations; if the cycle times are greater than or equal to the preset value, stopping the cycle to obtain the ordered data. The realization method of the multipath sequencer provided by the application adopts the acquisition of multipath minimum values to replace the actual sequencing operation, and the shift register is used for carrying out shift register on the minimum values acquired each time, so that the method has the advantages of less consumed logic resources, moderate logic processing delay, capability of well balancing calculation delay and logic resources and greatly reducing the cost.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
In order to more clearly illustrate the technical solution of the present application, the drawings that are needed in the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flow chart of a method for implementing a multi-way sequencer according to an embodiment of the present application;
FIG. 2 is a block diagram of a system for implementing a multi-way sequencer according to an embodiment of the present application;
fig. 3 is a block diagram of another implementation system of a multi-way sequencer according to an embodiment of the present application.
Detailed Description
In order to make the technical solution of the present application better understood by those skilled in the art, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
Referring to fig. 1, a flowchart of a method for implementing a multi-way sequencer according to an embodiment of the present application is provided.
As shown in fig. 1, the implementation method of the multi-path sequencer provided by the embodiment of the application includes:
s1: and respectively placing the data to be sequenced into different registers.
The application is illustrated with a 64-way sequencer, with 64 data1-data64 being respectively stored in 64 registers.
S2: the data in the registers are read separately.
If the data in the registers are read as required and the 64 data are ordered as required, the 64 data are read from the 64 registers respectively.
S3: and obtaining the minimum value in the data, and obtaining the minimum value data and the position corresponding to the minimum value data.
The read data (64 data) is input into a minimum value acquirer, so as to obtain minimum value data min_data in the 64 data and a position min_data_id corresponding to the minimum value data, if the minimum value is 2, the minimum value data min_data_id is located in a 15 th register.
S4: and storing the minimum value data and the positions corresponding to the minimum value data into a shift register respectively.
After the minimum value data and the positions corresponding to the minimum value data in the 64 data are obtained, respectively storing the minimum value data and the positions corresponding to the minimum value data in the shift register, and storing the minimum value data and the positions corresponding to the minimum value data in the 64 data in the last position of the shift register according to the sorting requirement, if the 64 paths of data are sorted from big to small; and sorting the 64 paths of data from small to large, and respectively storing the minimum value data and the positions corresponding to the minimum value data in the 64 paths of data to the first bit of the shift register.
In this example, the positions corresponding to the minimum value data and the minimum value data may be stored in the first shift register and the second shift register respectively through the cycle times corresponding to the minimum value data, if the cycle times corresponding to the minimum value data obtained in this time is 2, that is, the minimum value of the data is obtained in the second time, if the 64 routes of data are ordered from big to small, the minimum value data is stored in the right 2 th bit of the first shift register, and the positions corresponding to the minimum value data are stored in the right 2 nd bit of the second shift register; and if the 64 routes of data are ordered from small to large, storing the minimum value data to the left 2 nd bit of the first shift register, and storing the position corresponding to the minimum value data to the left 2 nd bit of the second shift register.
S5: judging whether the cycle times are smaller than a preset value, if yes, executing a step S6; if not, executing the step S7; the cycle number is the number of times of obtaining the minimum value data.
Every time the minimum value data and the position corresponding to the minimum value data are obtained, the circulation times are increased by 1, if the 64 data are to be ordered, the preset value is set to be 64, and whether the circulation times are smaller than 64 is judged; if the data are not ordered as much as needed, but only a part of the data is selected to obtain the minimum value, for example, 24 data, the preset value is set to 24 data. If the cycle number is smaller than the preset value, S6 is executed; if the number of loops is greater than or equal to the preset value, S7 is executed.
S6: and (3) performing elimination processing on the register where the minimum value data is located, and continuing to execute S2, S3, S4 and S5.
If the cycle number of the minimum value data is smaller than the preset value, if the cycle number of the 64 paths of data is smaller than the preset value 64, the register where the minimum value data is located is eliminated, S2, S3, S4 and S5 are continuously executed, namely the data in the register is read again, the minimum value in the data is obtained, the positions corresponding to the minimum value data and the minimum value data are respectively stored in the first shift register and the second shift register, and whether the cycle number is smaller than the preset value is judged.
When the register in which the minimum value data is located is subjected to elimination processing, the data in the register in which the minimum value data is located can be replaced by an infinite value. If the data in the register where the minimum value data is found for the first time is replaced by an infinite value, then 64 paths of data containing the infinite value in the register are read, the minimum value in the 64 paths of data is found again, the minimum value data and the position corresponding to the minimum value data for the second time are obtained, and the minimum value data and the position corresponding to the minimum value data for the second time are respectively stored in the second bit or the second last bit of the first shift register and the second shift register according to the ordering requirement.
When the register in which the minimum value data is located is subjected to the elimination processing, the data in the register in which the minimum value data is located can be deleted. If deleting the data in the register where the minimum value data is found for the first time, only 63 registers are provided with the data, then reading the data in the 63 registers, finding the minimum value in the 63 paths of data, obtaining the minimum value data and the position corresponding to the minimum value data for the second time, and storing the minimum value data and the position corresponding to the minimum value data for the second time into the second bit or the second last bit of the first shift register and the second shift register respectively according to the ordering requirement.
And (3) carrying out 64 cycles on the S2, the S3, the S4, the S5 and the S6 according to the method to obtain 64 minimum value data and positions corresponding to the minimum value data, and respectively storing the 64 minimum value data and the minimum value data into the first shift register and the second shift register according to the ordering requirement.
The method for acquiring the 64 times of minimum value data and the positions corresponding to the minimum value data is not limited to the method, and the method is only required to circularly acquire the minimum value data and the positions corresponding to the minimum value data each time, and belongs to the protection scope of the embodiment of the application.
S7: and stopping the circulation to obtain the ordered data.
If the number of times of cycle of the minimum value data is greater than or equal to a preset value, stopping the cycle, wherein the content in the shift register is the ordered data, and thus the ordering of 64 paths of data is completed.
The implementation method of the multi-path sequencer provided by the embodiment of the application adopts the mode of acquiring 64 paths of minimum values to replace actual sequencing operation, only acquires the minimum value in 64 paths of data each time, carries out shift register by a shift register for each acquired minimum value, and modifies the content of the corresponding position of the register (replaces or deletes the data in the corresponding register by infinity) in time after each acquired minimum value, thus consuming less logic resources, only needing 64 registers, 1 64 paths of minimum value acquirers and 2 rows of shift registers, having moderate logic processing delay, well balancing calculation delay and logic resources, having novel and simple structure, saving area and greatly reducing cost.
Based on the implementation method of the multi-path sequencer described in the above embodiment, the embodiment of the present application further provides an implementation system of the multi-path sequencer.
As shown in fig. 2 and fig. 3, a system for implementing a multi-path sequencer according to an embodiment of the present application includes:
and the register is used for storing the data to be sequenced. In this example, 64 registers are required to temporarily store 64 data1-data64, respectively.
The minimum value acquisition module is used for obtaining the minimum value in the data and obtaining the minimum value data and the position corresponding to the minimum value data.
And the shift register is used for respectively storing the minimum value data and the positions corresponding to the minimum value data. In this example, the shift register includes a first shift register and a second shift register, wherein,
and the first shift register is used for storing the minimum value data according to the cycle times corresponding to the minimum value data. In this example, after the cycle number corresponding to the minimum value data is obtained, the minimum value data is stored in the first shift register according to the cycle number, for example, when the 64 paths of data are ordered from small to large, the minimum value data is stored in the corresponding position on the left side of the first shift register according to the cycle number. When the 64 paths of data are ordered from big to small, the minimum value data are stored to the right corresponding position of the first shift register according to the circulation times.
And the second shift register is used for storing the position corresponding to the minimum value data according to the cycle times corresponding to the minimum value data. In this example, after the cycle number corresponding to the minimum value data is obtained, the position corresponding to the minimum value data is stored in the second shift register according to the cycle number, for example, when the 64 paths of data are ordered from small to large, the position corresponding to the minimum value data is stored in the corresponding position on the left side of the second shift register according to the cycle number. And if the 64 paths of data are ordered from big to small, storing the position corresponding to the minimum value data to the corresponding position on the right of the second shift register according to the cycle times.
The judging module is used for judging whether the circulation times are smaller than a preset value, wherein the circulation times are times for obtaining minimum value data.
And the elimination processing module is used for eliminating the register where the minimum value data is located when the cycle number is smaller than a preset value. The exclusion processing module may include a replacement module and may also include a deletion module.
And the replacement module is used for replacing the data in the register where the minimum value data is located with an infinite value, namely replacing the data in the register where the minimum value data is located with the infinite value according to the obtained minimum value data, then reading the data in the replaced register, obtaining the minimum value in the data again, obtaining the minimum value data and the positions corresponding to the minimum value data, and storing the positions corresponding to the minimum value data and the minimum value data in the first shift register and the second shift register respectively.
And the deleting module is used for deleting the data in the register where the minimum value data is located, namely deleting the data in the register where the minimum value data is located according to the obtained minimum value data, then reading the data in the rest registers, obtaining the minimum value in the data again, obtaining the minimum value data and the positions corresponding to the minimum value data, and storing the positions corresponding to the minimum value data and the minimum value data in the first shift register and the second shift register respectively.
The implementation system of the multipath sequencer provided by the embodiment of the application consumes less logic resources, only needs a plurality of registers, 1 minimum value acquirer and 2 rows of shift registers, has moderate logic processing delay, can well balance calculation delay and logic resources, and greatly reduces cost.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure of the application herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
The embodiments of the present application described above do not limit the scope of the present application.
Claims (8)
1. A method for implementing a multi-way sorter, the method comprising:
s1: respectively placing the data to be sequenced into different registers;
s2: respectively reading the data in the registers;
s3: inputting the read data into a minimum value acquirer, and obtaining the minimum value in the data through the minimum value acquirer to obtain minimum value data and the position corresponding to the minimum value data;
s4: respectively storing the minimum value data and the positions corresponding to the minimum value data to the corresponding positions of the shift register according to the cycle times; wherein the cycle number is the number of times of obtaining minimum value data;
s5: judging whether the cycle times are smaller than a preset value, if yes, executing a step S6; if not, executing the step S7;
s6: performing elimination processing on a register where the minimum value data is located, and continuously executing S2, S3, S4 and S5;
s7: and stopping the circulation to obtain the ordered data.
2. The method according to claim 1, wherein storing the minimum value data and the positions corresponding to the minimum value data to the corresponding positions of the shift register according to the number of cycles, respectively, comprises:
acquiring the circulation times corresponding to the minimum value data;
and respectively storing the minimum value data and the positions corresponding to the minimum value data to the corresponding positions of the first shift register and the second shift register according to the cycle times.
3. The method of claim 1, wherein excluding the register in which the minimum value data is located comprises:
and replacing the data in the register where the minimum value data is located with an infinite value.
4. The method of claim 1, wherein excluding the register in which the minimum value data is located comprises:
and deleting the data in the register where the minimum value data is located.
5. A system for implementing a multi-way sorter, comprising:
a register for storing data to be ordered;
the minimum value acquisition module is used for obtaining the minimum value in the data to obtain minimum value data and the position corresponding to the minimum value data;
the shift register is used for respectively storing the minimum value data and the positions corresponding to the minimum value data at the corresponding positions according to the cycle times; wherein the cycle number is the number of times of obtaining minimum value data;
the judging module is used for judging whether the cycle times are smaller than a preset value or not;
the elimination processing module is used for eliminating the register where the minimum value data is located when the cycle times are smaller than the preset value;
and the circulation stopping module is used for stopping circulation when the circulation times are greater than or equal to the preset value, and obtaining ordered data.
6. The system of claim 5, wherein the shift register comprises:
the first shift register is used for storing the minimum value data according to the cycle times corresponding to the minimum value data;
and the second shift register is used for storing the position corresponding to the minimum value data according to the cycle times corresponding to the minimum value data.
7. The system of claim 5, wherein the exclusion processing module comprises:
and the replacing module is used for replacing the data in the register where the minimum value data is located with an infinite value.
8. The system of claim 5, wherein the exclusion processing module comprises:
and the deleting module is used for deleting the data in the register where the minimum value data are located.
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