CN110765727A - Filling method of layout graph - Google Patents
Filling method of layout graph Download PDFInfo
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- CN110765727A CN110765727A CN201910986336.2A CN201910986336A CN110765727A CN 110765727 A CN110765727 A CN 110765727A CN 201910986336 A CN201910986336 A CN 201910986336A CN 110765727 A CN110765727 A CN 110765727A
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Abstract
The application discloses a filling method of layout graphs, which comprises the following steps: providing a design layout comprising an auxiliary active layer, a redundant active layer, an auxiliary gate layer and a redundant gate layer; selecting an auxiliary active layer with the line width within a first preset line width range and a redundant active layer with the line width within a second preset line width range; for the auxiliary active layer with the line width within a first preset line width range, adding an auxiliary silicon-germanium layer on the auxiliary active layer with the line width smaller than the first preset line width, and adding an auxiliary silicon-germanium layer on at least one auxiliary active layer with the line width larger than the first preset line width; and determining the pattern of the redundant silicon-germanium layer to be added according to the pattern around the redundant active layer for the redundant active layer with the line width within the second preset line width range. The substrate patterns in the germanium-silicon pattern growth area are classified, different filling modes are adopted according to the substrate patterns with different line widths, and the problem of defects caused by a pattern load effect is solved to a certain extent.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a filling method of layout patterns in the manufacturing process of a semiconductor device.
Background
With the continuous reduction of technical nodes in semiconductor manufacturing, the process is increasingly complex, and in order to enable a silicon germanium (SiGe) pattern to be epitaxially grown on a substrate better, the effective density of the SiGe pattern needs to meet the on-line process requirements, so that a SiGe redundant pattern and a device auxiliary pattern are introduced in the manufacturing process of a semiconductor device.
However, the applicant found that in the actual manufacturing process of the semiconductor device, on the substrate pattern with a large growth area, due to the influence of the pattern growth loading effect, the silicon germanium can not be uniformly grown on the substrate surface effectively, so that the finally generated silicon germanium pattern can generate pit defects in the middle area.
Disclosure of Invention
The application provides a filling method of a layout graph, which can solve the problem that a silicon germanium graph of a semiconductor device manufactured on the basis of a layout generated by the filling method of the layout graph provided in the related technology has defects.
In one aspect, an embodiment of the present application provides a method for filling a layout pattern, including:
providing a design layout comprising an auxiliary active layer, a redundant active layer, an auxiliary gate layer and a redundant gate layer;
selecting an auxiliary active layer with the line width within a first preset line width range and a redundant active layer with the line width within a second preset line width range;
for an auxiliary active layer with a line width within a first predetermined line width range, adding an auxiliary silicon-germanium layer on the auxiliary active layer smaller than the first predetermined line width, and adding an auxiliary silicon-germanium layer on at least one auxiliary active layer larger than the first predetermined line width, wherein the first predetermined line width is within the first predetermined line width range;
for the redundant active layer with the line width within a second preset line width range, adding a redundant silicon-germanium layer on the first type of redundant active layer, determining the pattern of the redundant silicon-germanium layer to be added according to the pattern around the second type of redundant active layer, and adding the redundant silicon-germanium layer with the determined pattern on the second type of redundant active layer, wherein the first type of redundant active layer is a redundant active layer on which a redundant gate layer is superposed, and the second type of redundant active layer is a redundant active layer on which the redundant gate layer is not superposed.
Optionally, the adding an auxiliary sige layer on the auxiliary active layer with a line width smaller than the first predetermined line width includes:
selecting an auxiliary active layer with the line width smaller than a first preset line width from the auxiliary active layers with the line width within a first preset line width range through logic operation;
adding an auxiliary SiGe layer on the auxiliary active layer smaller than the first predetermined line width.
Optionally, the adding an auxiliary sige layer on at least one auxiliary active layer with a line width greater than the first predetermined line width includes:
selecting an auxiliary active layer with the line width larger than a first preset line width from the auxiliary active layers with the line width within a first preset line width range through logic operation;
adding an auxiliary SiGe layer on at least one auxiliary active layer having a width greater than the first predetermined linewidth.
Optionally, the line width of the superimposed region of the added auxiliary sige layer and the auxiliary active layer is within a third predetermined line width range, and the third predetermined line width range is within the first predetermined line width range.
Optionally, a distance between an edge of the added auxiliary silicon germanium layer and an edge of the auxiliary active layer is within a first predetermined distance range, and the first predetermined distance range is within the first predetermined line width range.
Optionally, the third predetermined line width is in a range from 50 nm to 100 nm, and the first distance is in a range from 50 nm to 70 nm.
Optionally, the determining the pattern of the redundant sige layer to be added according to the pattern around the second type of redundant active layer includes:
when the first type redundant active layer and the second type redundant active layer do not exist on two sides of the second type redundant active layer, determining that a redundant silicon-germanium layer needing to be added covers an overlapping area with the second type redundant active layer;
when the second type of redundant active layer exists on one side of the second type of redundant active layer, determining that a redundant silicon-germanium layer needing to be added covers a gap between two adjacent redundant active layers and an overlapping area exists between the two adjacent redundant active layers;
when the first type redundant active layer exists on one side of the second type redundant active layer, determining that a redundant silicon germanium layer which needs to be added covers a gap between the adjacent first type redundant active layer and the second type redundant active layer and the first type redundant active layer, and an overlapping area exists between the first type redundant active layer and the second type redundant active layer.
Optionally, the line width of the superimposed region of the added redundant sige layer and the redundant active layer is within a fourth predetermined line width range, and the fourth predetermined line width range is within the second predetermined line width range.
Optionally, a distance between an edge of the added redundant sige layer and an edge of the redundant active layer is within a second predetermined distance range, and the second predetermined distance range is within the second predetermined line width range.
Optionally, the fourth predetermined line width is in a range from 100 nm to 150 nm, and the second distance is in a range from 50 nm to 70 nm.
Optionally, a value range of the first predetermined line width is 100 nm to 150 nm.
Optionally, the first predetermined line width range is 90 nm to 200 nm.
Optionally, the second predetermined line width is in a range of 200 nm to 300 nm.
The technical scheme at least comprises the following advantages:
by classifying the substrate patterns in the germanium-silicon pattern growth area and adopting different filling modes of redundant patterns and auxiliary patterns according to the substrate patterns with different line widths, the requirement of a semiconductor manufacturing process on the density of the germanium-silicon patterns is met on the premise of not violating layout design rules, and the defect problem caused by pattern load effect is solved to a certain extent.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flowchart of a layout pattern filling method according to an exemplary embodiment of the present application;
fig. 2 is a schematic view of an auxiliary active region filled with an auxiliary silicon germanium layer provided by an exemplary embodiment of the present application;
fig. 3-5 are schematic diagrams of redundant active regions filled with redundant silicon germanium layers provided by an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Example 1:
referring to fig. 1, a flowchart of a filling method of layout graphics provided in an exemplary embodiment of the present application is shown, where the method includes:
step S1, providing a design layout including an auxiliary Active layer (AA DAF), a redundant Active layer (AA Dummy), an auxiliary gate layer (PO DAF), and a redundant gate layer (PODummy).
In step S2, an auxiliary active layer having a line width within a first predetermined line width range and a redundant active layer having a line width within a second predetermined line width range are selected.
In step S3, for the auxiliary active layer having a line width within a first predetermined line width range, an auxiliary silicon germanium layer (SiGe DAF) is added on the auxiliary active layer smaller than the first predetermined line width, and an auxiliary silicon germanium layer is added on at least one auxiliary active layer larger than the first predetermined line width.
Wherein the first predetermined line width is within a value range of the first predetermined line width range.
For example, the first predetermined line width range is 90 nm to 200 nm, the first predetermined line width is 120 nm, the auxiliary active layer with the line width of 90 nm to 200 nm is selected in the design layout, the auxiliary sige layer is added to all the auxiliary active layers with the line width of less than 120 nm in the auxiliary active layer with the line width of 90 nm to 200 nm, and the auxiliary sige layer is added to the part of the auxiliary active layer with the line width of more than 120 nm in the auxiliary active layer with the line width of 90 nm to 200 nm.
And step S4, adding redundant silicon germanium layers on the redundant active layer of the first type for the redundant active layer with the line width within the second preset line width range, determining the pattern of the redundant silicon germanium layers needing to be added according to the pattern around the redundant active layer of the second type, and adding the redundant silicon germanium layers with the determined pattern on the redundant active layer of the second type.
Wherein the first type of redundant active layer is a redundant active layer (AA PO) on which a redundant gate layer is superimposed, and the second type of redundant active layer is a redundant active layer on which a redundant gate layer is not superimposed.
For example, the second predetermined line width range is 200 nm to 300 nm, the redundant active layers with the line width of 200 nm to 300 nm are selected in the design layout, the redundant silicon germanium layers are added to the first type of redundant active layers in the redundant active layers with the line width of 200 nm to 300 nm, and the redundant active layers of the second type are added after the pattern of the redundant silicon germanium layers needing to be added is determined according to the surrounding patterns.
In summary, in the embodiment, the substrate patterns in the growth region of the sige pattern are classified, and different filling manners of the redundant pattern and the auxiliary pattern are adopted according to the substrate patterns with different line widths, so that the requirement of the semiconductor manufacturing process on the density of the sige pattern is met on the premise of not violating the layout design rule, and the problem of the defect caused by the pattern loading effect is solved to a certain extent.
Example 2:
referring to example 1, example 2 differs from example 1 in that: in step S3, the adding an auxiliary sige layer on the auxiliary active layer with a line width smaller than the first predetermined line width includes: selecting an auxiliary active layer with the line width smaller than a first preset line width from the auxiliary active layers with the line width within a first preset line width range through logic operation, and adding an auxiliary silicon-germanium layer on the auxiliary active layer with the line width smaller than the first preset line width.
Example 3:
referring to example 2, example 3 differs from example 2 in that: in step S3, the "adding an auxiliary sige layer on at least one auxiliary active layer with a line width greater than the first predetermined line width" includes: selecting an auxiliary active layer with the line width larger than a first preset line width from the auxiliary active layers with the line width within a first preset line width range through logic operation; an auxiliary silicon germanium layer is added on at least one auxiliary active layer having a width greater than the first predetermined line width.
Example 4:
referring to examples 1 to 3, example 4 differs from the above examples in that: the line width of the superimposed region of the auxiliary sige layer and the auxiliary active layer added in the above embodiments is within a third predetermined line width range. Optionally, a distance between an edge of the added auxiliary silicon germanium layer and an edge of the auxiliary active layer is within a first predetermined distance range. Wherein the third predetermined line width range and the first predetermined distance range are within the first predetermined line width range. Optionally, the third predetermined line width is in a range of 50 nm to 100 nm, and the first distance is in a range of 50 nm to 70 nm.
Illustratively, referring to fig. 2, a line width W1 of an overlapping region of the auxiliary sige layer 210 and the auxiliary active layer 220 is within a third predetermined line width range, and a distance a1 of the auxiliary sige layer 210 from an edge of the auxiliary active layer 220 is within a first predetermined distance range.
Wherein the third predetermined linewidth range is within the first predetermined linewidth range. For example, a center line may be formed at the center of the auxiliary active layer, and then the center line may be stretched up, down, left, and right so that the line width of the auxiliary active layer overlapping the auxiliary sige layer satisfies a third predetermined line width range.
Example 5:
referring to examples 1 to 4, example 5 differs from the above examples in that: in step S4, the "determining the pattern of the redundant sige layer to be added according to the pattern around the second type of redundant active layer" includes:
and S41, when the first type redundant active layer and the second type redundant active layer do not exist on two sides of the second type redundant active layer, determining that the redundant silicon germanium layer needing to be added covers the area overlapped with the second type redundant active layer.
Illustratively, referring to fig. 3, there are no other redundant active layers on both sides of the second type of redundant active layer 322, and thus the pattern of the redundant silicon germanium layer 311 added on the second type of redundant active layer 322 is such that there is an overlap region with the second type of redundant active layer 320.
And S42, when the second-type redundant active layer exists on one side of the second-type redundant active layer, determining that the redundant silicon germanium layer which needs to be added covers the gap between two adjacent redundant active layers and has an overlapped area with the two adjacent redundant active layers.
Exemplarily, referring to fig. 4, another redundant active layer 322 of the second type exists at one side of the redundant active layer 322 of the second type, and thus the pattern of the redundant silicon germanium layer 312 added on the redundant active layer 322 of the second type is such that it covers a gap between two adjacent redundant active layers 322 and there is an overlap region with the two adjacent redundant active layers 322.
And S43, when the first type redundant active layer exists on one side of the second type redundant active layer, determining that the redundant silicon germanium layer which needs to be added covers the gap between the adjacent first type redundant active layer and the second type redundant active layer and the first type redundant active layer, and an overlapped area exists with the second type redundant active layer.
Illustratively, referring to fig. 5, if a first type of redundant active layer 321 is present on one side of a second type of redundant active layer 322 (the redundant active layer 321 is overlapped by a redundant gate 330), the redundant sige layer 313 is required to be added in a pattern covering the gap between the adjacent first type of redundant active layer 321 and the second type of redundant active layer 322 and the first type of redundant active layer 321, and an overlapping region exists with the second type of redundant active layer 322.
Example 6:
referring to example 5, example 6 differs from example 5 in that: the line width of the added redundant silicon-germanium layer and the overlapped area of the redundant active layer is within a fourth preset line width range; optionally, the distance between the edge of the added redundant silicon germanium layer and the edge of the redundant active layer is within a second preset distance range. The fourth preset line width range is within the second preset line width range, and the second preset distance range is within the second preset line width range. Optionally, the fourth predetermined line width is in a range from 100 nm to 150 nm, and the second distance is in a range from 50 nm to 70 nm.
Illustratively, referring to fig. 3 through 5, the line width W2 of the superimposed region of the added redundant sige layer (311, 312, and 313) and the redundant active layer 322 is within a fourth predetermined line width range, and the distance a2 of the redundant sige layer from the edge of the redundant active layer 322 is within a second predetermined distance range.
Optionally, in this embodiment of the application, a value range of the first predetermined line width is 100 nm to 150 nm. Preferably, the first predetermined line width is 120 nm.
Optionally, in this embodiment of the application, after performing any of the above embodiments, it is detected whether the added auxiliary sige layer and redundant sige layer meet requirements of a manufacturing process of a semiconductor device, and if not, selecting an auxiliary active layer and a redundant active layer with other line width ranges, and performing the method provided in any of the above embodiments again.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (13)
1. A filling method of layout patterns is characterized by comprising the following steps:
providing a design layout comprising an auxiliary active layer, a redundant active layer, an auxiliary gate layer and a redundant gate layer;
selecting an auxiliary active layer with the line width within a first preset line width range and a redundant active layer with the line width within a second preset line width range;
for an auxiliary active layer with a line width within a first predetermined line width range, adding an auxiliary silicon-germanium layer on the auxiliary active layer smaller than the first predetermined line width, and adding an auxiliary silicon-germanium layer on at least one auxiliary active layer larger than the first predetermined line width, wherein the first predetermined line width is within the first predetermined line width range;
for the redundant active layer with the line width within a second preset line width range, adding a redundant silicon-germanium layer on the first type of redundant active layer, determining the pattern of the redundant silicon-germanium layer to be added according to the pattern around the second type of redundant active layer, and adding the redundant silicon-germanium layer with the determined pattern on the second type of redundant active layer, wherein the first type of redundant active layer is a redundant active layer on which a redundant gate layer is superposed, and the second type of redundant active layer is a redundant active layer on which the redundant gate layer is not superposed.
2. The method of claim 1, wherein adding an auxiliary sige layer on the auxiliary active layer less than the first predetermined linewidth comprises:
selecting an auxiliary active layer with the line width smaller than a first preset line width from the auxiliary active layers with the line width within a first preset line width range through logic operation;
adding an auxiliary SiGe layer on the auxiliary active layer smaller than the first predetermined line width.
3. The method of claim 2, wherein adding an auxiliary sige layer on at least one auxiliary active layer greater than the first predetermined linewidth comprises:
selecting an auxiliary active layer with the line width larger than a first preset line width from the auxiliary active layers with the line width within a first preset line width range through logic operation;
adding an auxiliary SiGe layer on at least one auxiliary active layer having a width greater than the first predetermined linewidth.
4. The method of claim 3, wherein the line width of the superimposed region of the added auxiliary SiGe layer and the auxiliary active layer is within a third predetermined line width range, the third predetermined line width range being within the first predetermined line width range.
5. The method of claim 4, wherein a distance between an edge of the added auxiliary SiGe layer and an edge of the auxiliary active layer is within a first predetermined distance range, the first predetermined distance range being within the first predetermined line width range.
6. The method of claim 5, wherein the third predetermined line width is in a range of 50 nm to 100 nm and the first distance is in a range of 50 nm to 70 nm.
7. The method of claim 1, wherein determining the pattern of redundant silicon germanium layers to be added according to the pattern around the second type of redundant active layer comprises:
when the first type redundant active layer and the second type redundant active layer do not exist on two sides of the second type redundant active layer, determining that a redundant silicon-germanium layer needing to be added covers an overlapping area with the second type redundant active layer;
when the second type of redundant active layer exists on one side of the second type of redundant active layer, determining that a redundant silicon-germanium layer needing to be added covers a gap between two adjacent redundant active layers and an overlapping area exists between the two adjacent redundant active layers;
when the first type redundant active layer exists on one side of the second type redundant active layer, determining that a redundant silicon germanium layer which needs to be added covers a gap between the adjacent first type redundant active layer and the second type redundant active layer and the first type redundant active layer, and an overlapping area exists between the first type redundant active layer and the second type redundant active layer.
8. The method of claim 7, wherein the line width of the superimposed region of the added redundant SiGe layer and the redundant active layer is within a fourth predetermined range of line widths, the fourth predetermined range of line widths being within the second predetermined range of line widths.
9. The method of claim 8, wherein a distance between an edge of the added redundant silicon germanium layer and an edge of a redundant active layer is within a second predetermined range of distances, the second predetermined range of distances being within the second predetermined range of line widths.
10. The method of claim 9, wherein the fourth predetermined line width is in a range of 100 nm to 150 nm and the second distance is in a range of 50 nm to 70 nm.
11. The method according to any one of claims 1 to 10, wherein the first predetermined line width has a value in a range of 100 nm to 150 nm.
12. The method of claim 11, wherein the first predetermined line width is in a range of 90 nm to 200 nm.
13. The method of claim 12, wherein the second predetermined line width is in a range of 200 nm to 300 nm.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103886153A (en) * | 2014-03-27 | 2014-06-25 | 上海华力微电子有限公司 | Drawing method for polycrystalline silicon layer device auxiliary graphs |
| CN103902789A (en) * | 2014-04-22 | 2014-07-02 | 上海华力微电子有限公司 | Filling method of redundant graphs |
| CN109614705A (en) * | 2018-12-12 | 2019-04-12 | 上海华力集成电路制造有限公司 | The generation method of metal layer device secondary graphics |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103886153A (en) * | 2014-03-27 | 2014-06-25 | 上海华力微电子有限公司 | Drawing method for polycrystalline silicon layer device auxiliary graphs |
| CN103902789A (en) * | 2014-04-22 | 2014-07-02 | 上海华力微电子有限公司 | Filling method of redundant graphs |
| CN109614705A (en) * | 2018-12-12 | 2019-04-12 | 上海华力集成电路制造有限公司 | The generation method of metal layer device secondary graphics |
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