CN110752859B - Twisted pair carrier data communication circuit - Google Patents
Twisted pair carrier data communication circuit Download PDFInfo
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- CN110752859B CN110752859B CN201911254773.1A CN201911254773A CN110752859B CN 110752859 B CN110752859 B CN 110752859B CN 201911254773 A CN201911254773 A CN 201911254773A CN 110752859 B CN110752859 B CN 110752859B
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- 238000004891 communication Methods 0.000 title claims abstract description 17
- 230000008878 coupling Effects 0.000 claims abstract description 26
- 238000010168 coupling process Methods 0.000 claims abstract description 26
- 238000005859 coupling reaction Methods 0.000 claims abstract description 26
- 239000003990 capacitor Substances 0.000 claims description 27
- 239000013078 crystal Substances 0.000 claims description 7
- 230000010355 oscillation Effects 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
Abstract
The invention discloses a twisted pair carrier data communication circuit, which comprises an MCU processing module, a power supply circuit, a modulation circuit connected with the MCU processing module and used for modulating a transmitting signal of the MCU processing module, a transformer coupling circuit connected with the modulation circuit and used for receiving and transmitting the signal, and a front-stage amplifying and demodulating circuit connected with the transformer coupling circuit and used for amplifying and demodulating the received signal, wherein the front-stage amplifying and demodulating circuit is connected with the MCU processing module, the MCU processing module is also connected with the front-stage amplifying and demodulating circuit through a logic circuit used for controlling the signal processing of the front-stage amplifying and demodulating circuit, the modulation circuit is also connected with an oscillating circuit, and the MCU processing module, the modulation circuit, the oscillating circuit, the transformer coupling circuit and the front-stage amplifying and demodulating circuit are respectively connected with the power supply circuit. The invention can realize convenient and quick data communication and save cost.
Description
Technical Field
The invention relates to the field of electronic communication, in particular to a twisted pair carrier data communication circuit.
Background
The current system technology for realizing automatic meter reading comprises a twisted pair carrier communication technology circuit, wherein a circuit transmitting part of the circuit forms a modulation signal for transmitting a 50KHz carrier, and a band-pass filter and an operational amplifier circuit with an enabling function are used in the modulation process. The receiving circuit part is that the signal is processed completely through a 50KHz band-pass filter circuit, a full-wave rectifier circuit and a hysteresis comparison output circuit.
Therefore, the existing processing method is complex in technology, a transmitting circuit is driven by an operational amplifier, an RC operational amplifier oscillating circuit method is used for an oscillating circuit, so that the accuracy is low, a 50KHz band-pass filter is additionally added to the RC operational amplifier oscillating circuit, and the complexity and the cost are increased; when the receiving circuit part has no logic control function, communication echo phenomenon can occur during communication. In the existing processing method, the data echo signal is eliminated by using an output pin of an MCU program, so that the cost is high.
Disclosure of Invention
The invention aims to provide a twisted pair carrier data communication circuit which can realize convenient and quick data communication and save cost.
In order to achieve the purpose, the twisted pair carrier data communication circuit comprises an MCU processing module, a power supply circuit, a modulation circuit connected with the MCU processing module and used for modulating a transmission signal of the MCU processing module, a transformer coupling circuit connected with the modulation circuit and used for receiving and transmitting the signal, and a front-stage amplifying and demodulating circuit connected with the transformer coupling circuit and used for amplifying and demodulating the received signal, wherein the front-stage amplifying and demodulating circuit is connected with the MCU processing module, the MCU processing module is further connected with the front-stage amplifying and demodulating circuit through a logic circuit used for controlling signal processing of the front-stage amplifying and demodulating circuit, the modulation circuit is further connected with an oscillating circuit, and the MCU processing module, the modulation circuit, the oscillating circuit, the transformer coupling circuit and the front-stage amplifying and demodulating circuit are respectively connected with the power supply circuit.
Preferably, the modulation circuit comprises an analog switch circuit connected with the oscillation circuit, and the output end of the MCU processing module is connected with the enabling end of the analog switch circuit through a first inverter and a second inverter in sequence; the first output end of the analog switch circuit is connected with the base electrode of a second triode, the collector electrode of the second triode is connected with the power supply circuit through a ninth resistor and is also connected with the base electrode of a first triode, the emitter electrode of the first triode is connected with the power supply circuit and the collector electrode of the first triode is connected with the second modulation output end, the emitter electrode of the second triode is connected with the ground wire through an eleventh resistor and is also connected with the base electrode of a third triode, the collector electrode of the third triode is connected with the first modulation output end through a tenth resistor, the second output end of the analog switch circuit is connected with the base electrode of a fifth triode, the collector electrode of the fifth triode is connected with the power supply circuit through a twelfth resistor and is also connected with the base electrode of a fourth triode, the emitter electrode of the fourth triode is connected with the power supply circuit and is also connected with the base electrode of the first modulation output end, the emitter electrode of the fifth triode is connected with the ground wire through a thirteenth resistor and is also connected with the base electrode of the sixth triode, the second output end of the fourth triode is connected with the ground wire of the fourth triode, and the fourth modulation output end of the fourth triode is connected with the ground wire through a fourth modulator.
Preferably, the oscillation circuit is composed of a time base chip oscillation circuit and a 50KHz crystal oscillator circuit, and the time base chip circuit and the crystal oscillator circuit are respectively connected with an analog switch circuit.
Preferably, the transformer coupling circuit comprises a voltage device and input and output connectors connected with two ends of a secondary side of the voltage device, two ends of a primary side of the voltage device are respectively connected with a first modulation output end and a second modulation output end, two ends of the primary side of the voltage device are sequentially connected with a seventh diode through a sixth diode and a seventeenth diode and are also connected with a seventeenth resistor in parallel, the positive poles of the sixth diode and the positive poles of the seventh diode are connected to form a voltage limiting circuit, the connecting end of the primary side of the voltage device and the first modulation output end are sequentially connected with a ground wire through an eleventh capacitor and an eighteenth resistor, two ends of the eighteenth resistor are connected with a twenty-second resistor in parallel, and the other end of the primary side of the voltage device is sequentially connected with a pre-stage amplifying and demodulating circuit through a twelfth capacitor and a nineteenth resistor.
Preferably, the pre-stage amplifying and demodulating circuit comprises a first operational amplifier comparator and a second operational amplifier comparator which are connected with the transformer coupling circuit, wherein the output end of the first operational amplifier comparator is connected with the inverting input end of the second operational amplifier comparator through a ninth diode, the positive electrode of the ninth diode is connected with the output end of the first operational amplifier comparator through a twenty-fifth resistor and a fifteenth capacitor respectively, the negative end of the ninth diode is connected with the ground wire through a thirteenth capacitor, the inverting input end of the first operational amplifier comparator is connected with the transformer coupling circuit through a thirteenth capacitor, the connecting end of the thirteenth capacitor is connected with the ground wire through a fourteenth capacitor and is also connected with the output end of the first operational amplifier comparator through a fourteenth capacitor, the other end of the thirteenth capacitor is connected with the output end of the first operational amplifier comparator through a twenty-fourth resistor and is connected with the power supply circuit through a twenty-third resistor, the inverting input end of the second operational amplifier is connected with the inverting input end of the second operational amplifier through a twenty-fourth resistor and is also connected with the inverting input end of the twenty-third resistor and the output end of the second operational amplifier, and the inverting input end of the second operational amplifier is also connected with the twenty-fourth resistor and the output end of the second operational amplifier is connected with the inverting input end of the second operational amplifier.
Preferably, the logic circuit is provided with a third NAND gate, wherein two input ends of the third NAND gate are connected with the output end of the first inverter, the output end of the third NAND gate is connected with the front-stage amplifying and demodulating circuit through a fourth diode and a fifteenth resistor respectively, the negative electrode of the fourth diode is connected with the output end of the third NAND gate, and the positive electrode of the fourth diode is connected with the ground wire through a ninth capacitor.
Compared with the prior art, the invention has the beneficial effects that:
the invention generates signals through the modulation circuit and the oscillation circuit, receives signals through the pre-amplification and demodulation circuit and the logic circuit, ensures that the line is well received and stably transmitted, can realize convenient and quick data communication, and saves cost. The logic circuit solves the problem of crosstalk between the isolation transmission and the reception, does not need an MCU output pin, saves chip resources, and simultaneously can disconnect an echo signal of a transmission signal passing through a transformer from a NOT gate circuit of a pre-stage amplifying and demodulating circuit, effectively distinguish the signals transmitted and received by a secondary stage of the transformer, and avoid the MCU from receiving chaotic data. The oscillating circuit in the invention can effectively ensure the stable frequency. In the present invention
Drawings
FIG. 1 is a block diagram of a circuit configuration of the present invention;
FIG. 2 is a schematic diagram of a modulation circuit according to the present invention;
FIG. 3 is a schematic diagram of a transformer coupling circuit according to the present invention;
FIG. 4 is a schematic diagram of a pre-stage amplifying and demodulating circuit according to the present invention;
FIG. 5 is a schematic diagram of a logic circuit according to the present invention;
FIG. 6 is a schematic diagram of a 50KHz crystal oscillator circuit according to the present invention;
FIG. 7 is a schematic diagram of oscillation structure of a time base chip according to the present invention;
fig. 8 is a schematic diagram of a power circuit according to the present invention.
Detailed Description
The invention is further described below in connection with the examples, which are not to be construed as limiting the invention in any way, but rather as a limited number of modifications which are within the scope of the appended claims.
As shown in fig. 1 to 8, the invention provides a twisted pair carrier data communication circuit, which comprises an MCU processing module 1, a power supply circuit 7, a modulation circuit 3 connected with the MCU processing module 1 and used for modulating a transmission signal of the MCU processing module 1, a transformer coupling circuit 4 connected with the modulation circuit 3 and used for receiving and transmitting signals and connected with external equipment, and a front-stage amplifying and demodulating circuit 5 connected with the transformer coupling circuit 4 and used for amplifying and demodulating the received signals, wherein the front-stage amplifying and demodulating circuit 5 is connected with the MCU processing module 1, the MCU processing module 1 is also connected with the front-stage amplifying and demodulating circuit 5 through a logic circuit 6 used for controlling signal processing of the front-stage amplifying and demodulating circuit 5, the modulation circuit 3 is also connected with an oscillating circuit 2, and the MCU processing module 1, the modulation circuit 3, the oscillating circuit 2, the transformer coupling circuit 4 and the front-stage amplifying and demodulating circuit 5 are respectively connected with the power supply circuit 7.
The modulation circuit 3 comprises an analog switch circuit U3 connected with the oscillation circuit 2, and the output end of the MCU processing module 1 is connected with the enabling end of the analog switch circuit U3 through a first inverter U2E and a second inverter U2D in sequence; the first output end DRIVE_A of the analog switch circuit U3 is connected with the base electrode of a second triode Q2, the collector electrode of the second triode Q2 is connected with the power supply circuit 7 through a ninth resistor R9 and is also connected with the base electrode of a first triode Q1, the emitter electrode of the first triode Q1 is connected with the power supply circuit 7, the collector electrode of the first triode Q1 is connected with a second modulation output end OUT_B, the emitter electrode of the second triode Q2 is connected with the ground wire through an eleventh resistor R11 and is also connected with the base electrode of a third triode Q3, the collector electrode of the third triode Q3 is connected with the first modulation output end OUT_A, the emitter electrode of the third triode Q3 is connected with the ground wire through a tenth resistor R10, the second output end DRIVE_B of the analog switch circuit U3 is connected with the base electrode of a fifth triode Q5, the collector of the fifth triode Q5 is connected with the power supply circuit 7 through a twelfth resistor R12 and is also connected with the base of a fourth triode Q4, the emitter of the fourth triode Q4 is connected with the power supply circuit 7, the collector of the fourth triode Q4 is connected with the first modulation output end OUT_A, the emitter of the fifth triode Q5 is connected with the ground wire through a thirteenth resistor R13 and is also connected with the base of a sixth triode Q6, the collector of the sixth triode Q6 is connected with the second modulation output end OUT_B, the emitter of the sixth triode Q6 is connected with the ground wire through a fourteenth resistor R14, and the first modulation output end OUT_A and the second modulation output end OUT_B are respectively connected with the transformer coupling circuit 4, so that the triode modulation circuit is formed.
The oscillating circuit 2 is composed of a time base chip oscillating circuit and a 50KHz crystal oscillator circuit, and the time base chip circuit and the crystal oscillator circuit are respectively connected with the analog switch circuit U3.
In this embodiment, the first transistor Q1 and the fourth transistor Q4 are PNP transistors, and the second transistor Q2, the third transistor Q3, the fifth transistor Q5 and the sixth transistor Q6 are NPN transistors. The power circuit 7 is connected with the power connector J1 by 12V direct current. The first output end drive_a and the second output end drive_b of the analog switch circuit U3 output two paths of forward and reverse signals, the signal output by the first output end drive_a is amplified by switching current through a first triode Q1, a second triode Q2 and a third triode Q3, the signal output by the second output end drive_b is amplified by switching current through a fourth triode Q4, a fifth triode Q5 and a sixth triode Q6, and then the signals are respectively sent to the output end of the transformer coupling circuit 4.
The transformer coupling circuit 4 comprises a voltage device T1 and an input and output connector J3 connected with two ends of a secondary side of the voltage device T1, two ends of a primary side of the voltage device T1 are respectively connected with a first modulation output end OUT_A and a second modulation output end OUT_B, two ends of the primary side of the voltage device T1 are sequentially connected through a sixth diode D6 and a seventh diode D7 and are also connected with a seventeenth resistor R17 in parallel, and the positive electrode of the sixth diode D6 and the positive electrode of the seventh diode D7 are connected to form a voltage limiting circuit so that input overvoltage is clamped in a safe interval. The primary side of the voltage device T1 is connected with a first modulation output end OUT_A through an eleventh capacitor C11 and an eighteenth resistor R18 in sequence and is connected with a ground wire, twenty-second resistors R22 are connected in parallel at two ends of the eighteenth resistor R18, and the other end of the primary side of the voltage device T1 is connected with a front-stage amplifying and demodulating circuit 5 through a twelfth capacitor C12 and a nineteenth resistor R19 in sequence.
The front-stage amplifying and demodulating circuit 5 comprises a first operational amplifier comparator U5A and a second operational amplifier comparator U5B which are connected with the transformer coupling circuit 4, wherein the output end of the first operational amplifier comparator U5A is connected with the inverting input end of the first operational amplifier comparator U5B through a ninth diode D9, the positive electrode of the ninth diode D9 is connected with the output end of the first operational amplifier comparator U5A, the negative end of the ninth diode D9 is also connected with the ground wire through a twenty-fifth resistor R25 and a fifteenth capacitor C15 respectively, the inverting input end of the first operational amplifier comparator U5A is connected with the transformer coupling circuit 4 through a thirteenth capacitor C13, the connecting end of the thirteenth capacitor C13 is connected with the ground wire through a twenty-first resistor R20 and is also connected with the output end of the first operational amplifier comparator U5A through a twenty-first resistor R21, the inverting input end of the first operational amplifier U5A is connected with the inverting input end of the twenty-first operational amplifier U7 through a twenty-first resistor R24 and is also connected with the inverting input end of the twenty-first operational amplifier U4B through a twenty-first resistor R24 and the inverting input end of the twenty-first operational amplifier U4B, the inverting input end of the thirteenth capacitor C13 is also connected with the twenty-first operational amplifier U5B through a twenty-first resistor R24 and the twenty-first output end of the twenty-first operational amplifier U4B is also connected with the twenty-first output end of the twenty-first operational amplifier U5B, the inverting input end of the twenty-third comparator U4B is also connected with the twenty-first output end of the twenty-first capacitor C4B 4, the twenty-first output end is also connected with the twenty-first output end of the twenty-first output end 4C is connected with the twenty-first output end.
In this embodiment, the first op-amp comparator U5A is configured to amplify the received signal to a level that can be compared by the second op-amp comparator U5B, and then the signal forms a detection and op-amp inverted output demodulation signal through the ninth diode D9, the twenty-fifth resistor R25 and the fifteenth capacitor C15.
The logic circuit 6 is provided with a third nand gate U4B, the two input ends of which are connected with the output end of the first inverter U2E, the output end of the third nand gate U4B is connected with the front-stage amplifying and demodulating circuit 5 through a fourth diode D4 and a fifteenth resistor R15, the negative electrode of the fourth diode D4 is connected with the output end of the third nand gate U4B, and the positive electrode is connected with the ground through a ninth capacitor C9.
In this embodiment, when the MCU processing module 1 transmits data, the transmission signal passes through the logic circuit 6 and the first nand gate U4C of the pre-amplifying and demodulating circuit 5, and the transmitted signal can be disconnected from the echo signal formed by the transformer T1 and the pre-amplifying and demodulating circuit 5, so that the external signal transmitted and received by the transformer T1 can be effectively distinguished, thereby avoiding the MCU from receiving the data signal stably, and improving the working stability.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and improvements can be made by those skilled in the art without departing from the structure of the present invention, and these do not affect the effect of the implementation of the present invention and the utility of the patent.
Claims (3)
1. The utility model provides a paired line carrier data communication circuit, includes MCU processing module (1) and power supply circuit (7), its characterized in that: the device further comprises a modulation circuit (3) connected with the MCU processing module (1) and used for modulating a transmission signal of the MCU processing module (1), a transformer coupling circuit (4) connected with the modulation circuit (3) and used for receiving and transmitting the signal, and a front-stage amplifying and demodulating circuit (5) connected with the transformer coupling circuit (4) and used for amplifying and demodulating the received signal, wherein the front-stage amplifying and demodulating circuit (5) is connected with the MCU processing module (1), the MCU processing module (1) is further connected with the front-stage amplifying and demodulating circuit (5) through a logic circuit (6) used for controlling signal processing of the front-stage amplifying and demodulating circuit (5), the modulation circuit (3) is further connected with the oscillating circuit (2), and the MCU processing module (1), the modulation circuit (3), the oscillating circuit (2), the transformer coupling circuit (4) and the front-stage amplifying and demodulating circuit (5) are respectively connected with the power supply circuit (7); the modulation circuit (3) comprises an analog switch circuit (U3) connected with the oscillation circuit (2), and the output end of the MCU processing module (1) is connected with the enabling end of the analog switch circuit (U3) through a first inverter (U2E) and a second inverter (U2D) in sequence; the first output end (DRIVE_A) of the analog switch circuit (U3) is connected with the base electrode of a second triode (Q2), the collector electrode of the second triode (Q2) is connected with the power supply circuit (7) through a ninth resistor (R9) and is also connected with the base electrode of the first triode (Q1), the emitter electrode of the first triode (Q1) is connected with the power supply circuit (7) and the collector electrode of the first triode (Q1) is connected with a second modulation output end (OUT_B), the emitter electrode of the second triode (Q2) is connected with the ground wire through an eleventh resistor (R11) and is also connected with the base electrode of a third triode (Q3), the collector electrode of the third triode (Q3) is connected with the ground wire through a tenth resistor (R10), the second output end (DRIVE_B) of the analog switch circuit (U3) is connected with the second modulation output end (OUT_B), the emitter electrode of the second triode (Q2) is connected with the ground wire through an eleventh resistor (R11) and is also connected with the base electrode of the third triode (Q3), the collector electrode of the third triode (Q3) is connected with the fourth triode (Q4) is connected with the base electrode of the fourth triode (Q4), the emitter of the fifth triode (Q5) is connected with the ground wire through a thirteenth resistor (R13) and is also connected with the base electrode of a sixth triode (Q6), the collector electrode of the sixth triode (Q6) is connected with a second modulation output end (OUT_B), the emitter of the sixth triode (Q6) is connected with the ground wire through a fourteenth resistor (R14), and the first modulation output end (OUT_A) and the second modulation output end (OUT_B) are respectively connected with a transformer coupling circuit (4) so as to form a triode modulation circuit; the front-stage amplifying and demodulating circuit (5) comprises a first operational amplifier comparator (U5A) and a second operational amplifier comparator (U5B) which are connected with a transformer coupling circuit (4), the output end of the first operational amplifier comparator (U5A) is connected with the inverting input end of the second operational amplifier comparator (U5B) through a ninth diode (D9), the positive electrode of the ninth diode (D9) is connected with the output end of the first operational amplifier comparator (U5A), the negative end of the ninth diode (D9) is also connected with the ground wire through a twenty-fifth resistor (R25) and a fifteenth capacitor (C15) respectively, the inverting input end of the first operational amplifier comparator (U5A) is connected with the transformer coupling circuit (4) through a thirteenth capacitor (C13), the connecting end of the thirteenth capacitor (C13) and the transformer coupling circuit (4) is connected with the ground wire through a twenty-fourth resistor (R20) and is also connected with the output end of the first operational amplifier comparator (U5A) through a fourteenth capacitor (C14), the other end of the thirteenth capacitor (C13) is connected with the output end of the first operational amplifier comparator (U5A) through a twenty-first resistor (R21), the non-inverting input end of the first operational amplifier comparator (U5A) is connected with the ground wire through a twenty-fourth resistor (R24) and is connected with the power circuit (7) through a twenty-third resistor (R23), the non-inverting input end of the second operational amplifier comparator (U5B) is connected with the output end of the second operational amplifier comparator (U5B) through a twenty-eighth resistor (R28), the non-inverting input end of the second operational amplifier comparator (U5B) is also connected with a ground wire through a twenty-seventh resistor (R27) and is also connected with a power supply circuit (7) through a twenty-sixth resistor (R26), the output end of the second operational amplifier comparator (U5B) is also connected with the ground wire through a twenty-ninth resistor (R29) and is also connected with two input ends of a first NAND gate (U4C), the output end of the first NAND gate (U4C) is connected with one input end of a second NAND gate (U4A), the other input end of the second NAND gate (U4A) is connected with a logic circuit (6), and the output end of the second NAND gate (U4A) is connected with the MCU processing module (1); the logic circuit (6) is provided with a third NAND gate (U4B) with two input ends connected with the output end of the first inverter (U2E), the output end of the third NAND gate (U4B) is connected with the front-stage amplifying and demodulating circuit (5) through a fourth diode (D4) and a fifteenth resistor (R15) respectively, the negative electrode of the fourth diode (D4) is connected with the output end of the third NAND gate (U4B), and the positive electrode is connected with the ground wire through a ninth capacitor (C9).
2. A twisted pair carrier data communication circuit as set forth in claim 1, wherein: the oscillating circuit (2) consists of a time base chip oscillating circuit and a 50KHz crystal oscillator circuit, and the time base chip oscillating circuit and the crystal oscillator circuit are respectively connected with an analog switch circuit (U3).
3. A twisted pair carrier data communication circuit as set forth in claim 1, wherein: the transformer coupling circuit (4) comprises a voltage device (T1) and input and output connectors (J3) connected with two ends of a secondary side of the voltage device (T1), two ends of a primary side of the voltage device (T1) are respectively connected with a first modulation output end (OUT_A) and a second modulation output end (OUT_B), two ends of the primary side of the voltage device (T1) are sequentially connected with a seventh diode (D6) and a seventeenth resistor (R17) in parallel, the positive electrode of the sixth diode (D6) and the positive electrode of the seventh diode (D7) are connected to form a voltage limiting circuit, the connection end of the primary side of the voltage device (T1) and the first modulation output end (OUT_A) are sequentially connected with a ground wire through an eleventh capacitor (C11) and an eighteenth resistor (R18), two ends of the eighteenth resistor (R18) are sequentially connected with a twenty-second resistor (R22) in parallel, and the other end of the primary side of the voltage device (T1) is sequentially connected with a nineteenth resistor (R19) and a ninth amplifier circuit (5) through a twelfth capacitor (C12).
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911254773.1A CN110752859B (en) | 2019-12-07 | 2019-12-07 | Twisted pair carrier data communication circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911254773.1A CN110752859B (en) | 2019-12-07 | 2019-12-07 | Twisted pair carrier data communication circuit |
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| CN110752859B true CN110752859B (en) | 2024-04-16 |
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| CN2406295Y (en) * | 2000-02-01 | 2000-11-15 | 四川银海经济技术有限公司 | Device for centralized taking-down numble of meter |
| CN201374695Y (en) * | 2009-03-09 | 2009-12-30 | 青岛大荣实业有限公司 | Embedded low-voltage power line carrier communication module |
| KR101257210B1 (en) * | 2012-07-05 | 2013-04-23 | 주식회사 리모텍 | Circuit for transmitting/receiving digital signal using power line |
| CN105827130A (en) * | 2016-05-26 | 2016-08-03 | 阳光电源股份有限公司 | Cascaded multi-level inverter system |
| CN210867679U (en) * | 2019-12-07 | 2020-06-26 | 广州鲁邦通物联网科技有限公司 | Twisted-pair carrier data communication circuit |
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2019
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2406295Y (en) * | 2000-02-01 | 2000-11-15 | 四川银海经济技术有限公司 | Device for centralized taking-down numble of meter |
| CN201374695Y (en) * | 2009-03-09 | 2009-12-30 | 青岛大荣实业有限公司 | Embedded low-voltage power line carrier communication module |
| KR101257210B1 (en) * | 2012-07-05 | 2013-04-23 | 주식회사 리모텍 | Circuit for transmitting/receiving digital signal using power line |
| CN105827130A (en) * | 2016-05-26 | 2016-08-03 | 阳光电源股份有限公司 | Cascaded multi-level inverter system |
| CN210867679U (en) * | 2019-12-07 | 2020-06-26 | 广州鲁邦通物联网科技有限公司 | Twisted-pair carrier data communication circuit |
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