CN110752859A - Twisted-pair carrier data communication circuit - Google Patents
Twisted-pair carrier data communication circuit Download PDFInfo
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- CN110752859A CN110752859A CN201911254773.1A CN201911254773A CN110752859A CN 110752859 A CN110752859 A CN 110752859A CN 201911254773 A CN201911254773 A CN 201911254773A CN 110752859 A CN110752859 A CN 110752859A
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- 238000004891 communication Methods 0.000 title claims abstract description 20
- 230000008878 coupling Effects 0.000 claims abstract description 29
- 238000010168 coupling process Methods 0.000 claims abstract description 29
- 238000005859 coupling reaction Methods 0.000 claims abstract description 29
- 230000010355 oscillation Effects 0.000 claims abstract description 28
- 230000003321 amplification Effects 0.000 claims abstract description 19
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 19
- 230000005540 biological transmission Effects 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 25
- 239000013078 crystal Substances 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
Abstract
The invention discloses a twisted pair carrier data communication circuit, which comprises an MCU processing module and a power circuit, and also comprises a modulation circuit connected with the MCU processing module and used for modulating a transmission signal of the MCU processing module, a transformer coupling circuit connected with the modulation circuit and used for being connected with external equipment to receive and transmit signals, and a preceding stage amplification and demodulation circuit connected with the transformer coupling circuit and used for amplifying and demodulating the received signals, the pre-amplification and demodulation circuit is connected with the MCU processing module, the MCU processing module also controls the signal processing of the pre-amplification and demodulation circuit through a logic circuit and the pre-amplification and demodulation circuit, the modulation circuit is further connected with an oscillation circuit, and the MCU processing module, the modulation circuit, the oscillation circuit, the transformer coupling circuit and the preceding stage amplifying and demodulating circuit are respectively connected with the power supply circuit. The invention can realize convenient and quick data communication and save cost.
Description
Technical Field
The invention relates to the field of electronic communication, in particular to a twisted pair carrier data communication circuit.
Background
The current system technology for realizing automatic meter reading has a twisted pair carrier communication technology circuit, a circuit sending part of the circuit forms and sends a 50KHz carrier modulation signal, and a band-pass filter and an operational amplifier circuit with an enabling function are used in the modulation process. The receiving circuit part is that the signal is processed completely by a 50KHz band-pass filter circuit, a full-wave rectifier circuit and a hysteresis comparison output circuit.
Therefore, the existing processing method is complex in technology, the sending circuit is driven by the operational amplifier, the oscillating circuit of the sending circuit is low in precision by using the RC operational amplifier oscillating circuit method, a 50KHz band-pass filter needs to be additionally added to the RC operational amplifier oscillating circuit, and complexity and cost are increased; when the receiving circuit part has no logic control function, communication echo can occur during communication. In the existing processing method, the elimination of the data echo signal needs to be controlled by an output pin of an MCU program, so that the cost is high.
Disclosure of Invention
The invention aims to provide a twisted pair carrier data communication circuit which can realize convenient and quick data communication and save cost.
In order to achieve the purpose, the twisted pair carrier data communication circuit comprises an MCU processing module and a power supply circuit, and also comprises a modulation circuit which is connected with the MCU processing module and is used for modulating a transmission signal of the MCU processing module, a transformer coupling circuit which is connected with the modulation circuit and is used for being connected with external equipment to receive and transmit signals, and a preceding stage amplification and demodulation circuit which is connected with the transformer coupling circuit and is used for amplifying and demodulating the received signals, the pre-amplification and demodulation circuit is connected with the MCU processing module, the MCU processing module also controls the signal processing of the pre-amplification and demodulation circuit through a logic circuit and the pre-amplification and demodulation circuit, the modulation circuit is further connected with an oscillation circuit, and the MCU processing module, the modulation circuit, the oscillation circuit, the transformer coupling circuit and the preceding stage amplifying and demodulating circuit are respectively connected with the power supply circuit.
Preferably, the modulation circuit comprises an analog switch circuit connected with the oscillation circuit, and the output end of the MCU processing module is connected with the enable end of the analog switch circuit sequentially through a first inverter and a second inverter; the first output end of the analog switch circuit is connected with the base electrode of the second triode, the collector electrode of the second triode is connected with the power circuit through a ninth resistor and is also connected with the base electrode of the first triode, the emitter electrode of the first triode is connected with the power circuit and the collector electrode of the first triode is connected with the second modulation output end, the emitter electrode of the second triode is connected with the ground wire through an eleventh resistor and is also connected with the base electrode of the third triode, the collector electrode of the third triode is connected with the first modulation output end, the emitter electrode of the third triode is connected with the ground wire through a tenth resistor, the second output end of the analog switch circuit is connected with the base electrode of the fifth triode, the collector electrode of the fifth triode is connected with the power circuit through a twelfth resistor and is also connected with the base electrode of the fourth triode, the emitter electrode of the fourth triode is connected with the power circuit and the collector electrode of the fourth triode is connected with the first modulation output end The output end of the transformer is connected with the output end of the triode, the emitter of the fifth triode is connected with the ground wire through a thirteenth resistor and is also connected with the base of a sixth triode, the collector of the sixth triode is connected with the second modulation output end, the emitter of the sixth triode is connected with the ground wire through a fourteenth resistor, and the first modulation output end and the second modulation output end are respectively connected with the transformer coupling circuit, so that the triode modulation circuit is formed.
Preferably, the oscillation circuit is composed of a time-base chip oscillation circuit and a 50KHz crystal oscillation circuit, and the time-base chip oscillation circuit and the crystal oscillation circuit are respectively connected with the analog switch circuit.
Preferably, the transformer coupling circuit includes a transformer and an input/output connector connected to two ends of a secondary side of the transformer, two ends of a primary side of the transformer are respectively connected to the first modulation output terminal and the second modulation output terminal, two ends of a primary side of the transformer are sequentially connected to the sixth diode and the seventh diode and are further connected to the seventeenth resistor in parallel, an anode of the sixth diode and an anode of the seventh diode are connected to form a voltage limiting circuit, a connection end of the primary side of the transformer and the first modulation output terminal is sequentially connected to the ground through the eleventh capacitor and the eighteenth resistor, two ends of the eighteenth resistor are connected to the twenty-second resistor in parallel, and the other end of the primary side of the transformer is sequentially connected to the twelfth capacitor and the nineteenth resistor and is connected to the preceding stage amplifying and demodulating.
Preferably, the pre-amplification and demodulation circuit comprises a first operational amplifier comparator and a second operational amplifier comparator which are connected with a transformer coupling circuit, an output end of the first operational amplifier comparator is connected with an inverting input end of the second operational amplifier comparator through a ninth diode, an anode of the ninth diode is connected with an output end of the first operational amplifier comparator, a cathode end of the ninth diode is further connected with a ground wire through a twenty-fifth resistor and a fifteenth capacitor respectively, an inverting input end of the first operational amplifier comparator is connected with the transformer coupling circuit through a thirteenth capacitor, a connecting end of the thirteenth capacitor and the transformer coupling circuit is connected with the ground wire through a twentieth resistor and is further connected with an output end of the first operational amplifier comparator through a fourteenth capacitor, and the other end of the thirteenth capacitor is connected with an output end of the first operational amplifier comparator through a twenty-first resistor, the in-phase input end of the first operational amplifier comparator is connected with a ground wire through a twenty-fourth resistor and is connected with a power circuit through a twenty-third resistor, the in-phase input end of the second operational amplifier comparator is connected with the output end of the second operational amplifier comparator through a twenty-eighth resistor, the in-phase input end of the second operational amplifier comparator is further connected with the ground wire through a twenty-seventh resistor and is further connected with the power circuit through a twenty-sixth resistor, the output end of the second operational amplifier comparator is further connected with the ground wire through a twenty-ninth resistor and is further connected with two input ends of a first NAND gate, the output end of the first NAND gate is connected with one input end of a second NAND gate, the other input end of the second NAND gate is connected with a logic circuit, and the output end of the second NAND gate is connected with an MCU processing module.
Preferably, the logic circuit is provided with a third nand gate, two input ends of the input end of the third nand gate are connected with the output end of the first inverter, the output end of the third nand gate is connected with the preceding stage amplifying and demodulating circuit through a fourth diode and a fifteenth resistor respectively, the cathode of the fourth diode is connected with the output end of the third nand gate, and the anode of the fourth diode is connected with the ground through a ninth capacitor.
Compared with the prior art, the invention has the beneficial effects that:
the invention generates signals through the modulation circuit and the oscillation circuit, receives the signals through the pre-amplification and demodulation circuit and the logic circuit, ensures that the line receiving and sending are stable, can realize convenient and quick data communication, and saves the cost. The logic circuit solves the problem of crosstalk of isolated transmission and reception, does not need an output pin of the MCU, saves chip resources, and simultaneously can cut off an echo signal of a transmission signal passing through the transformer by the NOT circuit of the logic circuit and the preceding stage amplifying and demodulating circuit, effectively distinguishes signals transmitted and received by the secondary stage of the transformer, and prevents the MCU from receiving disordered data. The oscillating circuit in the invention can effectively ensure the frequency stability. In the present invention
Drawings
FIG. 1 is a block diagram of the circuit configuration of the present invention;
FIG. 2 is a schematic diagram of a modulation circuit according to the present invention;
FIG. 3 is a schematic diagram of a transformer coupling circuit according to the present invention;
FIG. 4 is a schematic diagram of a pre-stage amplifying and demodulating circuit according to the present invention;
FIG. 5 is a schematic diagram of a logic circuit according to the present invention;
FIG. 6 is a schematic structural diagram of a 50KHz crystal oscillator circuit according to the present invention;
FIG. 7 is a schematic diagram of the structure of the time-base chip oscillation according to the present invention;
fig. 8 is a schematic structural diagram of a power supply circuit according to the present invention.
Detailed Description
The invention will now be further described with reference to the following examples, which are not to be construed as limiting the invention in any way, and any limited number of modifications which can be made within the scope of the claims of the invention are still within the scope of the claims of the invention.
As shown in fig. 1 to 8, the present invention provides a twisted pair carrier data communication circuit, which comprises an MCU processing module 1 and a power circuit 7, and further comprises a modulation circuit 3 connected to the MCU processing module 1 for modulating a transmission signal of the MCU processing module 1, a transformer coupling circuit 4 connected to the modulation circuit 3 for receiving and transmitting a signal, a pre-amplification and demodulation circuit 5 connected to the transformer coupling circuit 4 for amplifying and demodulating the received signal, the pre-amplification and demodulation circuit 5 connected to the MCU processing module 1, the MCU processing module 1 further comprises a logic circuit 6 for controlling signal processing of the pre-amplification and demodulation circuit 5, the modulation circuit 3 is further connected to the oscillation circuit 2, the MCU processing module 1, the modulation circuit 3, and the oscillation circuit 2, The transformer coupling circuit 4 and the preceding stage amplifying and demodulating circuit 5 are connected to a power supply circuit 7, respectively.
The modulation circuit 3 comprises an analog switch circuit U3 connected with the oscillation circuit 2, and the output end of the MCU processing module 1 is connected with the enabling end of the analog switch circuit U3 through a first inverter U2E and a second inverter U2D in sequence; the first output terminal DRIVE _ a of the analog switch circuit U3 is connected to the base of the second transistor Q2, the collector of the second transistor Q2 is connected to the power supply circuit 7 via a ninth resistor R9 and also to the base of the first transistor Q1, the emitter of the first transistor Q1 is connected to the power supply circuit 7 and the collector of the first transistor Q1 is connected to the second modulation output terminal OUT _ B, the emitter of the second transistor Q2 is connected to ground via an eleventh resistor R11 and also to the base of the third transistor Q3, the collector of the third transistor Q3 is connected to the first modulation output terminal OUT _ a, the emitter of the third transistor Q3 is connected to ground via a tenth resistor R10, the second output terminal DRIVE _ B of the analog switch circuit U3 is connected to the base of the fifth transistor Q5, the collector of the fifth transistor Q5 is connected to the power supply circuit 7 via a twelfth resistor R12 and also to the base of the fourth transistor Q4, an emitter of the fourth transistor Q4 is connected to the power supply circuit 7 and a collector of the fourth transistor Q4 is connected to the first modulation output terminal OUT _ a, an emitter of the fifth transistor Q5 is connected to ground through a thirteenth resistor R13 and is also connected to a base of the sixth transistor Q6, a collector of the sixth transistor Q6 is connected to the second modulation output terminal OUT _ B, an emitter of the sixth transistor Q6 is connected to ground through a fourteenth resistor R14, and the first modulation output terminal OUT _ a and the second modulation output terminal OUT _ B are respectively connected to the transformer coupling circuit 4, thereby forming a triode modulation circuit.
The oscillation circuit 2 is composed of a time-base chip oscillation circuit and a 50KHz crystal oscillation circuit, and the time-base chip oscillation circuit and the crystal oscillation circuit are respectively connected with the analog switch circuit U3.
In this embodiment, the first transistor Q1 and the fourth transistor Q4 are PNP transistors, and the second transistor Q2, the third transistor Q3, the fifth transistor Q5 and the sixth transistor Q6 are NPN transistors. The power circuit 7 and the power connector J1 are connected with 12V direct current. The first output end DRIVE _ a and the second output end DRIVE _ B of the analog switch circuit U3 output two positive and negative signals, the signal output by the first output end DRIVE _ a is amplified by the switching current of the first triode Q1, the second triode Q2 and the third triode Q3, the signal output by the second output end DRIVE _ B is amplified by the switching current of the fourth triode Q4, the fifth triode Q5 and the sixth triode Q6, and then is respectively sent to the output end of the transformer coupling circuit 4.
The transformer coupling circuit 4 comprises a voltage transformer T1 and an input/output connector J3 connected with two secondary sides of a voltage transformer T1, two primary sides of the voltage transformer T1 are respectively connected with a first modulation output end OUT _ A and a second modulation output end OUT _ B, two primary sides of the voltage transformer T1 are sequentially connected with a sixth diode D6 and a seventh diode D7 in parallel and are also connected with a seventeenth resistor R17 in parallel, and the positive electrode of the sixth diode D6 and the positive electrode of the seventh diode D7 are connected to form a voltage limiting circuit so that the input overvoltage is clamped in a safety interval. The connection end of the primary side of the voltage device T1 and the first modulation output end OUT _ a is connected with the ground line through the eleventh capacitor C11 and the eighteenth resistor R18 in sequence, the two ends of the eighteenth resistor R18 are connected in parallel with the twenty-second resistor R22, and the other end of the primary side of the voltage device T1 is connected with the preceding stage amplification and demodulation circuit 5 through the twelfth capacitor C12 and the nineteenth resistor R19 in sequence.
The pre-stage amplifying and demodulating circuit 5 comprises a first operational amplifier comparator U5A and a second operational amplifier comparator U5B connected with the transformer coupling circuit 4, the output end of the first operational amplifier comparator U5A is connected with the inverting input end of the second operational amplifier comparator U5B through a ninth diode D9, the anode of the ninth diode D9 is connected with the output end of the first operational amplifier comparator U5A, the cathode of the ninth diode D9 is also connected with the ground through a twenty-fifth resistor R25 and a fifteenth capacitor C15 respectively, the inverting input end of the first operational amplifier comparator U5A is connected with the transformer coupling circuit 4 through a thirteenth capacitor C13, the connecting end of the thirteenth capacitor C13 and the transformer coupling circuit 4 is connected with the ground through a twentieth resistor R20 and is also connected with the output end of the first operational amplifier comparator U5A through a fourteenth capacitor C14, the other end of the thirteenth capacitor C13 is connected with the output end of the first operational amplifier comparator U5A through a first resistor R21, the non-inverting input terminal of the first operational amplifier comparator U5A is connected to the ground through a twenty-fourth resistor R24 and to the power supply circuit 7 through a twenty-third resistor R23, the non-inverting input terminal of the second operational amplifier comparator U5B is connected to the output terminal of the second operational amplifier comparator U5B through a twenty-eighth resistor R28, the non-inverting input terminal of the second operational amplifier comparator U5B is further connected to the ground through a twenty-seventh resistor R27 and to the power supply circuit 7 through a twenty-sixth resistor R26, the output terminal of the second operational amplifier comparator U5B is further connected to the ground through a twenty-ninth resistor R29 and to both input terminals of the first nand gate U4C, the output terminal of the first nand gate U4C is connected to one input terminal of the second nand gate U4A, the other input terminal of the second nand gate U4A is connected to the logic circuit 6, and the output terminal of the second nand gate U4A is connected to the MCU processing module 1.
In this embodiment, the first operational amplifier comparator U5A is used to amplify the received signal to a level that the second operational amplifier comparator U5B can compare, and then the signal is passed through the ninth diode D9, the twenty-fifth resistor R25 and the fifteenth capacitor C15 to form a demodulation signal of the demodulation and operational amplifier inverting output.
The logic circuit 6 is provided with a third nand gate U4B, two input ends of the input end of the third nand gate U4B are connected with the output end of the first inverter U2E, the output end of the third nand gate U4B is connected with the preceding stage amplifying and demodulating circuit 5 through a fourth diode D4 and a fifteenth resistor R15, the cathode of the fourth diode D4 is connected with the output end of the third nand gate U4B, and the anode is connected with the ground through a ninth capacitor C9.
In this embodiment, when the MCU processing module 1 transmits data, the transmitting signal passes through the logic circuit 6 and the first nand gate U4C of the preceding stage amplifying and demodulating circuit 5, so as to disconnect the echo signal formed by the transmitting signal via the transformer T1 and the preceding stage amplifying and demodulating circuit 5, thereby effectively distinguishing the external signal transmitted and received by the transformer T1, and preventing the MCU from receiving stable data signals, thereby improving the stability of operation.
The above is only a preferred embodiment of the present invention, and it should be noted that it is obvious to those skilled in the art that several variations and modifications can be made without departing from the structure of the present invention, which will not affect the effect of the implementation of the present invention and the utility of the patent.
Claims (6)
1. The utility model provides a twisted pair carrier data communication circuit, includes MCU processing module (1) and power supply circuit (7), its characterized in that: the signal processing device is characterized by further comprising a modulation circuit (3) which is connected with the MCU processing module (1) and is used for modulating a transmission signal of the MCU processing module (1), a transformer coupling circuit (4) which is connected with the modulation circuit (3) and is used for receiving and transmitting a signal and a preceding stage amplification and demodulation circuit (5) which is connected with the transformer coupling circuit (4) and is used for amplifying and demodulating a received signal, wherein the preceding stage amplification and demodulation circuit (5) is connected with the MCU processing module (1), the MCU processing module (1) is further connected with the preceding stage amplification and demodulation circuit (5) through a logic circuit (6) which is used for controlling signal processing of the preceding stage amplification and demodulation circuit (5), the modulation circuit (3) is further connected with the oscillation circuit (2), and the MCU processing module (1), the modulation circuit (3), the oscillation circuit (2), The transformer coupling circuit (4) and the pre-stage amplifying and demodulating circuit (5) are respectively connected with a power circuit (7).
2. The twisted-pair carrier data communication circuit of claim 1, wherein: the modulation circuit (3) comprises an analog switch circuit (U3) connected with the oscillation circuit (2), and the output end of the MCU processing module (1) is connected with the enabling end of the analog switch circuit (U3) through a first inverter (U2E) and a second inverter (U2D) in sequence; a first output terminal (DRIVE _ A) of the analog switching circuit (U3) is connected to a base of a second transistor (Q2), a collector of the second transistor (Q2) is connected to the power supply circuit (7) via a ninth resistor (R9) and is also connected to a base of a first transistor (Q1), an emitter of the first transistor (Q1) is connected to the power supply circuit (7) and a collector of a first transistor (Q1) is connected to a second modulation output terminal (OUT _ B), an emitter of the second transistor (Q2) is connected to ground via an eleventh resistor (R11) and is also connected to a base of a third transistor (Q3), a collector of the third transistor (Q3) is connected to the first modulation output terminal (OUT _ A), an emitter of the third transistor (Q3) is connected to ground via a tenth resistor (R10), a second output terminal (DRIVE _ B) of the analog switching circuit (U3) is connected to a base of a fifth transistor (Q5), the collector of the fifth triode (Q5) is connected with the power circuit (7) through a twelfth resistor (R12) and is also connected with the base of the fourth triode (Q4), the emitter of the fourth transistor (Q4) is connected to the power supply circuit (7) and the collector of the fourth transistor (Q4) is connected to the first modulation output (OUT _ A), the emitter of the fifth triode (Q5) is connected with the ground wire through a thirteenth resistor (R13) and is also connected with the base of the sixth triode (Q6), the collector of the sixth transistor (Q6) is connected to the second modulation output (OUT _ B), the emitter of the sixth triode (Q6) is connected with the ground wire through a fourteenth resistor (R14), the first modulation output end (OUT _ A) and the second modulation output end (OUT _ B) are respectively connected with a transformer coupling circuit (4), so that a triode modulation circuit is formed.
3. A twisted pair carrier data communication circuit according to claim 1 or 2, wherein: the oscillation circuit (2) consists of a time-base chip oscillation circuit and a 50KHz crystal oscillation circuit, and the time-base chip oscillation circuit and the crystal oscillation circuit are respectively connected with the analog switch circuit (U3).
4. The twisted-pair carrier data communication circuit of claim 1, wherein: the transformer coupling circuit (4) comprises a transformer (T1) and an input/output connector (J3) connected with two ends of a secondary side of the transformer (T1), two ends of a primary side of the transformer (T1) are respectively connected with a first modulation output end (OUT _ A) and a second modulation output end (OUT _ B), two ends of a primary side of the transformer (T1) are sequentially connected with a sixth diode (D6) and a seventh diode (D7) and are also connected with a seventeenth resistor (R17) in parallel, an anode of the sixth diode (D6) and an anode of the seventh diode (D7) are connected to form a voltage limiting circuit, a primary side of the transformer (T1) and a primary side of the first modulation output end (OUT _ A) are sequentially connected with an eleventh capacitor (C11) and an eighteenth resistor (R18) and a ground wire, two ends of the eighteenth resistor (R38) are connected with a twenty-second resistor (R22) in parallel, a secondary side of the other end of the transformer (T1) is sequentially connected with a twelfth capacitor (C3629) and a nineteenth resistor (R12) and the amplifying and demodulating circuit (5) is connected.
5. The twisted-pair carrier data communication circuit according to claim 1 or 4, wherein: the pre-amplification and demodulation circuit (5) comprises a first operational amplifier comparator (U5A) and a second operational amplifier comparator (U5B) which are connected with a transformer coupling circuit (4), the output end of the first operational amplifier comparator (U5A) is connected with the inverted input end of the second operational amplifier comparator (U5B) through a ninth diode (D9), the anode of the ninth diode (D9) is connected with the output end of the first operational amplifier comparator (U5A), the cathode end of the ninth diode (D9) is also connected with the ground through a twenty-fifth resistor (R25) and a fifteenth capacitor (C15) respectively, the inverted input end of the first operational amplifier comparator (U5A) is connected with the transformer coupling circuit (4) through a thirteenth capacitor (C13), the thirteenth capacitor (C13) is connected with the transformer coupling circuit (4) through a twentieth resistor (R20) and the output end of the fourteenth capacitor (C14) is also connected with the output end of the first operational amplifier comparator (U5A), the other end of the thirteenth capacitor (C13) is connected with the output end of the first operational amplifier comparator (U5A) through a twenty-first resistor (R21), the non-inverting input end of the first operational amplifier comparator (U5A) is connected with the ground through a twenty-fourteen resistor (R24) and is connected with the power supply circuit (7) through a twenty-third resistor (R23), the non-inverting input end of the second operational amplifier comparator (U5B) is connected with the output end of the second operational amplifier comparator (U5B) through a twenty-eighteen resistor (R28), the non-inverting input end of the second operational amplifier comparator (U5B) is further connected with the ground through a twenty-seventh resistor (R27) and is further connected with the power supply circuit (7) through a twenty-sixth resistor (R26), the output end of the second operational amplifier comparator (U5B) is further connected with the ground through a twenty-ninth resistor (R29) and is further connected with the input end of the first NAND gate (U4), the output end of the first NAND gate (U4C) is connected with one input end of a second NAND gate (U4A), the other input end of the second NAND gate (U4A) is connected with a logic circuit (6), and the output end of the second NAND gate (U4A) is connected with the MCU processing module (1).
6. The twisted-pair carrier data communication circuit according to claim 1 or 4, wherein: the logic circuit (6) is provided with a third NAND gate (U4B) of which two input ends are connected with the output end of the first inverter (U2E), the output end of the third NAND gate (U4B) is connected with the preceding stage amplifying and demodulating circuit (5) through a fourth diode (D4) and a fifteenth resistor (R15) respectively, the cathode of the fourth diode (D4) is connected with the output end of the third NAND gate (U4B), and the anode is connected with the ground through a ninth capacitor (C9).
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| CN201911254773.1A CN110752859B (en) | 2019-12-07 | 2019-12-07 | Twisted pair carrier data communication circuit |
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| CN201911254773.1A CN110752859B (en) | 2019-12-07 | 2019-12-07 | Twisted pair carrier data communication circuit |
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| KR101257210B1 (en) * | 2012-07-05 | 2013-04-23 | 주식회사 리모텍 | Circuit for transmitting/receiving digital signal using power line |
| CN105827130A (en) * | 2016-05-26 | 2016-08-03 | 阳光电源股份有限公司 | Cascaded multi-level inverter system |
| CN210867679U (en) * | 2019-12-07 | 2020-06-26 | 广州鲁邦通物联网科技有限公司 | Twisted-pair carrier data communication circuit |
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2019
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2406295Y (en) * | 2000-02-01 | 2000-11-15 | 四川银海经济技术有限公司 | Device for centralized taking-down numble of meter |
| CN201374695Y (en) * | 2009-03-09 | 2009-12-30 | 青岛大荣实业有限公司 | Embedded low-voltage power line carrier communication module |
| KR101257210B1 (en) * | 2012-07-05 | 2013-04-23 | 주식회사 리모텍 | Circuit for transmitting/receiving digital signal using power line |
| CN105827130A (en) * | 2016-05-26 | 2016-08-03 | 阳光电源股份有限公司 | Cascaded multi-level inverter system |
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