CN110752275A - Light emitting diode chip and preparation method thereof - Google Patents
Light emitting diode chip and preparation method thereof Download PDFInfo
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- CN110752275A CN110752275A CN201911118780.9A CN201911118780A CN110752275A CN 110752275 A CN110752275 A CN 110752275A CN 201911118780 A CN201911118780 A CN 201911118780A CN 110752275 A CN110752275 A CN 110752275A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 207
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 175
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 59
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 59
- 238000010438 heat treatment Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 230000003247 decreasing effect Effects 0.000 claims description 4
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
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- 229910052739 hydrogen Inorganic materials 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
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Abstract
The application provides a light-emitting diode chip and a preparation method thereof. The surface of the buffer layer, which is far away from the substrate, is provided with a plurality of three-dimensional island-shaped structures. The second undoped gallium nitride sublayer is arranged on the surfaces of the three-dimensional island-shaped structures and covers the three-dimensional island-shaped structures. The second undoped gallium nitride sublayer is a two-dimensional layered structure. At this time, a three-dimensional/two-dimensional alternating structure may be formed by the plurality of three-dimensional island-like structures and the second undoped gallium nitride sub-layer. Therefore, the non-radiative defects are subjected to direction turning at the alternate interface of the three-dimensional island structure and the two-dimensional layered structure, and then part of the defects are turned, merged and annihilated. And the undoped gallium nitride layer comprises a plurality of sub-gallium nitride layers, so that a multi-level three-dimensional/two-dimensional alternate structure can be realized, most non-radiative defects are turned in direction and combined and annihilated, the defects of the bottom layer are reduced to a great extent, the high-crystal quality epitaxial wafer is obtained, and the luminous efficiency of the chip is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a light emitting diode chip and a method for manufacturing the same.
Background
A Light-Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. The LED lamp is popular due to the advantages of small volume, low energy consumption, long service life, low driving voltage and the like, and is widely applied to the fields of indicator lamps, display screens and the like. The crystal quality of the epitaxial wafer is the key point influencing the brightness of the chip, so that the crystal quality is improved, the luminous efficiency of the chip is improved, and the method is the key point for preparing the high-brightness and high-luminous-efficiency LED device at present.
The traditional GaN-based epitaxial wafer growth method is to use a chemical vapor deposition method to sequentially grow a Buffer-Buffer layer, an undoped uGaN layer, an N-type nGaN layer, a multi-quantum well light-emitting layer and a P-type pGaN layer on a substrate layer. The conventional light emitting diode chip structure has a large number of non-radiative defects due to lattice mismatch and thermal mismatch of a substrate and an epitaxial layer (GaN). The non-radiative defects extend to the luminescent quantum wells to form deep recombination centers, which causes non-radiative luminescence, thereby affecting the luminous efficiency, and causing the luminous efficiency of the conventional light emitting diode chip to be low.
Disclosure of Invention
Therefore, it is necessary to provide a light emitting diode chip with high light emitting efficiency and a method for manufacturing the same, aiming at the problem of low light emitting efficiency of the conventional light emitting diode chip.
The application provides a light emitting diode chip, which comprises a substrate, a buffer layer and an undoped gallium nitride layer. The buffer layer is arranged on the surface of the substrate. The undoped gallium nitride layer is arranged on the surface of the buffer layer, which is far away from the substrate. The undoped gallium nitride layer includes a plurality of sub-gallium nitride layers. The plurality of sub gallium nitride layers are sequentially arranged on the surface, far away from the substrate, of the buffer layer. Each sub gallium nitride layer comprises a first undoped gallium nitride sublayer and a second undoped gallium nitride sublayer. The first undoped gallium nitride sublayer is arranged on the surface, far away from the substrate, of the buffer layer. The second undoped gallium nitride sublayer is arranged on the surface, far away from the buffer layer, of the first undoped gallium nitride sublayer. The first undoped gallium nitride sublayer includes a plurality of three-dimensional island-like structures. The plurality of three-dimensional island-shaped structures are sequentially arranged on the surface, far away from the substrate, of the buffer layer. The second undoped gallium nitride sublayer is arranged on the surface, away from the buffer layer, of the plurality of three-dimensional island-shaped structures.
In one embodiment, the second undoped gallium nitride sublayer is a two-dimensional layered structure and is disposed on a surface of the plurality of three-dimensional island-shaped structures away from the buffer layer.
In one embodiment, each of the sub-gallium nitride layers further comprises a silicon nitride layer. The silicon nitride layer is arranged on the surface of the second undoped gallium nitride sublayer far away from the first undoped gallium nitride sublayer.
In one embodiment, each of the sub-gallium nitride layers further comprises a third undoped gallium nitride sub-layer. The third undoped gallium nitride sublayer is arranged on the surface of the silicon nitride layer far away from the second undoped gallium nitride sublayer.
In one embodiment, each of the sub-gallium nitride layers further comprises a heat treatment layer. The heat treatment layer is arranged on the surface of the third undoped gallium nitride sublayer far away from the silicon nitride layer.
In one embodiment, the first undoped gallium nitride sublayer of two adjacent sub-gallium nitride layers in the plurality of sub-gallium nitride layers is disposed on a surface of the heat treatment layer away from the third undoped gallium nitride sublayer.
In one embodiment, the undoped gallium nitride layer includes 5 to 50 of the sub-gallium nitride layers.
In one embodiment, a method for manufacturing a light emitting diode chip includes:
s10, providing a substrate, and preparing a buffer layer on the surface of the substrate;
s20, preparing a first undoped gallium nitride sublayer on the surface of the buffer layer away from the substrate according to a first preset temperature and a first preset pressure in an environment with the temperature of 1070-1110 ℃ and the pressure of 250-450 torr;
s30, preparing a second undoped gallium nitride sublayer on the surface of the first undoped gallium nitride sublayer far away from the buffer layer in a temperature and pressure changing environment with the temperature of 1100-1140 ℃ and the pressure of 100-250 torr;
s40, preparing a silicon nitride layer on the surface of the second undoped gallium nitride sublayer, which is far away from the first undoped gallium nitride sublayer, according to a second preset temperature and a second preset pressure in the environment of 1100-1140 ℃ and 100-250 torr pressure;
s50, preparing a third undoped gallium nitride sublayer on the surface of the silicon nitride layer far away from the second undoped gallium nitride sublayer according to a third preset temperature and a third preset pressure in the environment of 1100-1140 ℃ and 100-250 torr pressure;
s60, preparing a heat treatment layer on the surface of the third undoped gallium nitride sublayer far away from the silicon nitride layer according to a fourth preset temperature and a fourth preset pressure in the environment of 1130-1170 ℃ and 100-250 torr pressure.
In one embodiment, the method for manufacturing a light emitting diode chip further includes:
and S70, according to the steps S20-S60, circularly preparing the first undoped gallium nitride sublayer, the second undoped gallium nitride sublayer, the silicon nitride layer, the third undoped gallium nitride sublayer and the heat treatment layer on the surface of the heat treatment layer far away from the third undoped gallium nitride sublayer in sequence.
In one embodiment, in the step S30, the second undoped gallium nitride sublayer is prepared on the surface of the first undoped gallium nitride sublayer away from the buffer layer in an environment with a temperature of 1100 ℃ to 1140 ℃ and a pressure of 100torr to 250torr and in an environment with a temperature varying and pressure varying environment with a gradually increasing temperature and a gradually decreasing pressure.
The application provides an above-mentioned emitting diode chip. The surface, far away from the substrate, of the buffer layer is provided with the plurality of three-dimensional island-shaped structures, and meanwhile, the second undoped gallium nitride sub-layer is arranged on the surfaces of the plurality of three-dimensional island-shaped structures and covers the plurality of three-dimensional island-shaped structures. The second undoped gallium nitride sublayer is of a two-dimensional layered structure. At this time, a three-dimensional/two-dimensional alternating structure, i.e., alternating from an island-like to a layered growth form, may be formed by the plurality of three-dimensional island-like structures and the second undoped gallium nitride sub-layer. Therefore, the non-radiative defects can be directionally turned at the alternate interface between the three-dimensional island structure and the two-dimensional layered structure, so that part of the defects are turned, merged and annihilated, an LED structure with higher crystal quality is obtained, and the luminous efficiency of the LED chip is increased.
And the undoped gallium nitride layer comprises a plurality of sub gallium nitride layers, so that a multi-level three-dimensional/two-dimensional alternate structure can be realized, most non-radiative defects are turned in direction and combined and annihilated, the defects of the bottom layer are reduced to a great extent, the epitaxial wafer with high crystal quality is obtained, and the luminous efficiency of the chip is improved.
Drawings
Fig. 1 is a schematic structural diagram of an undoped gallium nitride layer of a light emitting diode chip provided in the present application;
FIG. 2 is a schematic cross-sectional structure of a three-dimensional island structure provided herein;
FIG. 3 is a schematic top view of a three-dimensional island structure provided herein;
fig. 4 is a schematic process flow diagram of a method for manufacturing a light emitting diode chip according to the present application;
fig. 5 is a schematic structural diagram of an undoped gallium nitride layer in an embodiment provided in the present application.
Description of the reference numerals
The light emitting diode comprises a light emitting diode chip, a substrate 10, a buffer layer 20, an undoped gallium nitride layer 30, a sub gallium nitride layer 310, a first undoped gallium nitride sublayer 311, a second undoped gallium nitride sublayer 312, a three-dimensional island-shaped structure 3111, a silicon nitride layer 313, a third undoped gallium nitride sublayer 314, a heat treatment layer 315, an N-type semiconductor layer 40, a multi-quantum well layer 50 and a P-type semiconductor layer 60.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below by way of embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Referring to fig. 1, the present application provides a light emitting diode chip including a substrate 10, a buffer layer 20, and an undoped gallium nitride layer 30. The buffer layer 20 is disposed on the surface of the substrate 10. The undoped gallium nitride layer 30 is disposed on the surface of the buffer layer 20 away from the substrate 10. The undoped gallium nitride layer 30 includes a plurality of sub-gallium nitride layers 310. The plurality of sub gallium nitride layers 310 are sequentially disposed on the surface of the buffer layer 20 away from the substrate 10. Each of the sub-gan layers 310 includes a first undoped gan sublayer 311 and a second undoped gan sublayer 312. The first undoped gallium nitride sublayer 311 is disposed on the surface of the buffer layer 20 away from the substrate 10. The second undoped gallium nitride sublayer 312 is disposed on the surface of the first undoped gallium nitride sublayer 311 away from the buffer layer 20. The first undoped gallium nitride sublayer 311 includes a plurality of three-dimensional island-like structures 3111. The plurality of three-dimensional island-shaped structures 3111 are sequentially arranged on the surface of the buffer layer 20 away from the substrate 10. The second undoped gallium nitride sublayer 312 is disposed on the surfaces of the plurality of three-dimensional island-shaped structures 3111 away from the buffer layer 20.
The surface of the buffer layer 20 away from the substrate 10 is provided with the plurality of three-dimensional island-shaped structures 3111, and the second undoped gallium nitride sublayer 312 is provided on the surface of the plurality of three-dimensional island-shaped structures 3111 to cover the plurality of three-dimensional island-shaped structures 3111. The second undoped gallium nitride sublayer 312 is a two-dimensional layered structure. At this time, a three-dimensional/two-dimensional alternating structure, i.e., alternating from an island-like to a layered growth form, may be formed by the plurality of three-dimensional island-like structures 3111 and the second undoped gallium nitride sub-layer 312. Therefore, the non-radiative defects can be directionally turned at the alternate interface between the three-dimensional island structure and the two-dimensional layered structure, so that part of the defects are turned, merged and annihilated, an LED structure with higher crystal quality is obtained, and the luminous efficiency of the LED chip is increased.
Moreover, the undoped gallium nitride layer 30 comprises a plurality of sub gallium nitride layers 310, so that a multi-level three-dimensional/two-dimensional alternate structure can be realized, most non-radiative defects are turned in direction and combined and annihilated, the defects of the bottom layer are reduced to a great extent, the high-crystal quality epitaxial wafer is obtained, and the luminous efficiency of the chip is improved.
Referring to fig. 2-3, in one embodiment, the second undoped gan sublayer 312 is a two-dimensional layered structure disposed on the surface of the plurality of three-dimensional island-shaped structures 3111 away from the buffer layer 20.
Here, the three-dimensional island-like structure 3111 may be understood as a frustum structure. The two-dimensional layered structure may be understood as a film layer having a certain thickness. When the second undoped gallium nitride sublayer 312 is disposed on the surface of the plurality of three-dimensional island-shaped structures 3111 away from the buffer layer 20, the plurality of three-dimensional island-shaped structures 3111 may be covered. At this time, a plurality of voids are formed between the second undoped gallium nitride sublayer 312 and the plurality of three-dimensional island-shaped structures 3111. Further, the non-radiative defects are turned in a plurality of directions at the interface where the three-dimensional island structure and the two-dimensional layer structure alternate, so that the non-radiative defects are turned in the direction and are gradually merged and annihilated. Therefore, the LED structure with higher crystal quality can be obtained through the three-dimensional/two-dimensional alternating structure, and the luminous efficiency of the LED chip is improved.
In one embodiment, each of the sub-gallium nitride layers 310 further includes a silicon nitride layer 313. The silicon nitride layer 313 is disposed on the surface of the second undoped gallium nitride sublayer 312 away from the first undoped gallium nitride sublayer 311.
Wherein the silicon nitride (SiN) layer 313 may be provided as a layer of a mesh structure. The silicon nitride (SiN) layer 313 is disposed on the surface of the second undoped gallium nitride sublayer 312 away from the first undoped gallium nitride sublayer 311, and can prevent a portion of the defect from extending upward. Moreover, when part of the defects penetrate through the mesh holes of the silicon nitride (SiN) layer 313, the direction can be turned, so that merging and annihilation are realized, the defects can be further reduced, the crystal quality is improved, and the luminous efficiency of the light-emitting diode chip is improved.
In one embodiment, each of the sub-gallium nitride layers 310 further includes a third undoped gallium nitride sub-layer 314. The third undoped gallium nitride sublayer 314 is disposed on the surface of the silicon nitride layer 313 away from the second undoped gallium nitride sublayer 312.
The third undoped gallium nitride sublayer 314 is disposed on the surface of the silicon nitride layer 313, and may cover the mesh structure formed by the silicon nitride (SiN) layer 313. Thereby, a plurality of mesh-like gaps are formed at the interface of the third undoped gallium nitride sub-layer 314 and the silicon nitride (SiN) layer 313. Meanwhile, a plurality of mesh-like gaps are also formed at the interface between the second undoped gallium nitride sub-layer 312 and the silicon nitride (SiN) layer 313. At this time, the direction of partial defects can be turned by the mesh-shaped gap structure at the interface position, and the merging and annihilation are realized, so that the luminous efficiency of the light emitting diode chip is improved.
In one embodiment, each of the sub-gallium nitride layers 310 further includes a thermal treatment layer 315. The thermal treatment layer 315 is disposed on a surface of the third undoped gallium nitride sublayer 314 away from the silicon nitride layer 313.
The heat-treated layer 315 is formed by high temperatureHigh H2The atmosphere is formed by treating the interface of the third undoped gallium nitride sublayer 314. At this time, the heat treatment layer 315 is formed by treating the surface of the third undoped gallium nitride sublayer 314 away from the silicon nitride layer 313. The surface of the third undoped gallium nitride sublayer 314 away from the silicon nitride layer 313 is made smoother by the heat treatment layer 315, so that the defects formed by the whole layer of grown crystals not being flattened are covered, and further, an LED structure with higher crystal quality is obtained, thereby improving the light emitting efficiency of the light emitting diode chip.
Referring to fig. 5, in an embodiment, the first undoped gallium nitride sub-layer 311 of two adjacent sub-gallium nitride layers 310 in the plurality of sub-gallium nitride layers 310 is disposed on a surface of the heat treatment layer 315 away from the third undoped gallium nitride sub-layer 314.
The undoped gallium nitride layer 30 includes a plurality of sub gallium nitride layers 310, and the plurality of sub gallium nitride layers 310 are sequentially stacked and disposed on the surface of the buffer layer 20 away from the substrate 10. At this time, the first undoped gallium nitride sublayer 311 in each adjacent sub-gallium nitride layer 310 is in contact with the heat treatment layer 315. Since each of the sub-gan layers 310 includes a three-dimensional/two-dimensional alternating structure and a mesh structure, the undoped gan layer 30 may include a plurality of three-dimensional/two-dimensional alternating structures and mesh structures. Therefore, most defects can be turned in multiple directions through a plurality of three-dimensional/two-dimensional alternating structures and a plurality of net structures, so that the defects are transferred in the directions and then are combined and annihilated slowly, an LED structure with higher crystal quality is obtained, and the luminous efficiency of the LED chip is improved.
In one embodiment, the undoped gallium nitride layer 30 includes 5 to 50 of the sub-gallium nitride layers 310.
The number of the plurality of sub gallium nitride layers 310 included in the undoped gallium nitride layer 30 may be 5 to 50. Within this range, 5 to 50 sub-gallium nitride layers 310 can eliminate most defects, and the number of sub-gallium nitride layers 310 is limited, thereby reducing the cost.
In one embodiment, the light emitting diode chip further includes an N-type semiconductor layer 40. The N-type semiconductor layer 40 is disposed on the surface of the undoped gallium nitride layer 30 away from the buffer layer 20.
In one embodiment, the light emitting diode chip further includes a multiple quantum well layer 50. The mqw layer 50 is disposed on the surface of the N-type semiconductor layer 40 away from the undoped gan layer 30.
The MQW layer 50 is disposed on the surface of the N-type semiconductor layer 40 away from the undoped GaN layer 30, so that defects formed at the position of the substrate 10 can be prevented from extending to the MQW layer 50, and non-radiative light emission caused by the defects can be avoided.
In one embodiment, the light emitting diode chip further includes a P-type semiconductor layer 60. The P-type semiconductor layer 60 is disposed on a surface of the mqw layer 50 away from the N-type semiconductor layer 40.
By the three-dimensional/two-dimensional alternating structure and the net structure included in the undoped gallium nitride layer 30, a large number of defects are eliminated, and the crystal quality is improved. Moreover, the problem of poor electric leakage and antistatic capability of a leakage channel caused by defects is solved through the undoped gallium nitride layer 30, and the defects are prevented from extending to the multiple quantum well layer 50to generate defective non-radiative luminescence. Therefore, the light emitting efficiency of the light emitting diode chip is improved by the undoped gallium nitride layer 30.
Referring to fig. 4, in an embodiment, a method for manufacturing a light emitting diode chip includes:
s10, providing a substrate 10, and preparing a buffer layer 20 on the surface of the substrate 10;
s20, preparing a first undoped gan sublayer 311 on the surface of the buffer layer 20 away from the substrate 10 according to a first predetermined temperature and a first predetermined pressure in an environment with a temperature of 1070 ℃ to 1110 ℃ and a pressure of 250torr to 450 torr;
s30, preparing a second undoped gallium nitride sublayer 312 on the surface of the first undoped gallium nitride sublayer 311 away from the buffer layer 20 under the variable temperature and pressure environment of 1100 ℃ to 1140 ℃ and the pressure of 100torr to 250 torr;
s40, preparing a silicon nitride layer 313 on the surface of the second undoped gallium nitride sublayer 312 away from the first undoped gallium nitride sublayer 311 according to a second preset temperature and a second preset pressure in an environment with a temperature of 1100 ℃ to 1140 ℃ and a pressure of 100torr to 250 torr;
s50, preparing a third undoped gallium nitride sublayer 314 on the surface of the silicon nitride layer 313 away from the second undoped gallium nitride sublayer 312 according to a third preset temperature and a third preset pressure in an environment with a temperature of 1100 ℃ to 1140 ℃ and a pressure of 100torr to 250 torr;
s60, under the environment of 1130-1170 ℃ and 100-250 torr, a thermal treatment layer 315 is formed on the surface of the third undoped gan sublayer 314 away from the silicon nitride layer 313 according to a fourth predetermined temperature and a fourth predetermined pressure.
In the step S20, the first undoped gallium nitride sublayer 311 is grown by growth in a Metal Organic Chemical Vapor Deposition (MOCVD) machine, and reaction by introducing TMGA source in a mixed atmosphere of nitrogen, hydrogen and ammonia. Wherein, a first preset temperature is set within the range of 1070 ℃ to 1110 ℃, and a first preset pressure is set within the range of 250torr to 450 torr. The first preset temperature is a fixed value within the range of 1070-1110 ℃, and the first preset pressure is a fixed value within the range of 250-450 torr. And setting a constant temperature and constant pressure environment according to the first preset temperature and the first preset pressure, and preparing a first undoped gallium nitride sublayer 311 on the surface of the buffer layer 20 away from the substrate 10.
The thickness of the first undoped gallium nitride sublayer 311 may be 0.05um to 0.5 um. By preparing the thickness of the first undoped gallium nitride sublayer 311 to be 0.05 um-0.5 um, it is possible to ensure that the thickness can fill the substrate pattern and the defects can be reduced to a proper range on the basis of minimizing the cost. The crystal growth quality and the crystal growth speed can be optimized within the temperature of 1070-1110 ℃, the problems of poor crystal growth quality and low crystal growth speed are solved, and the manufacturing efficiency and the chip quality can be improved.
In step S30, the second undoped gallium nitride sublayer 312 is prepared on the surface of the first undoped gallium nitride sublayer 311 away from the buffer layer 20 by temperature and pressure variation in a range of 1100 ℃ to 1140 ℃ and a range of 100torr to 250 torr.
The temperature and pressure changing is a mode that the temperature is gradually increased and the pressure is gradually decreased. In the step S20, the pressure range is set to 250torr to 450torr, and the temperature is set to 1100 ℃ to 1140 ℃, so that a variation space is provided for the variation of the temperature variation and the pressure variation in the range of 1100 ℃ to 1140 ℃ and the range of 100torr to 250torr in the step S30 while the limit pressure of the cavity is satisfied. At this time, the temperature range and the pressure range in the step S30 and the temperature range and the pressure range in the step S20 can satisfy the change of the temperature and the pressure without bringing the pressure and the temperature to the limit values. Thus, through the steps S30 and S20, the second undoped gallium nitride sublayer 312 may be prepared through a temperature and pressure swing preparation method. The thickness of the second undoped gallium nitride sublayer 312 may be 0.05um to 0.5um, and the thickness is ensured in this range to reduce defects to a suitable range on the basis of minimizing the cost.
Therefore, the preparation method of the light-emitting diode chip utilizes a temperature and pressure changing growth mode to shorten the growth time and increase the probability of defect combination and annihilation, thereby reducing the defects and improving the luminous efficiency of the light-emitting diode chip.
In the step S40, SiH is independently introduced into a Metal Organic Chemical Vapor Deposition (MOCVD) tool4The silicon nitride layer 313(SiN layer) is prepared by gas under the conditions of 1100-1140 ℃ and 100-250 torr pressure. The second preset temperature is a fixed value within the range of 1100-1140 ℃, and the second preset pressure is a fixed value within the range of 100-250 torr. Setting a constant temperature according to the second preset temperature and the second preset pressureIn a constant pressure environment, the silicon nitride layer 313(SiN layer) is prepared on the surface of the second undoped gallium nitride sublayer 312 away from the first undoped gallium nitride sublayer 311.
The thickness of the silicon nitride layer 313(SiN layer) can be 0.01 um-0.05 um, and the thickness can be ensured to play a leveling role in the range on the basis of cost minimization, and the defects are reduced to be in a proper range. Meanwhile, the growth environment of the SiN layer can affect the tightness of the SiN net, so that the silicon nitride layer 313(SiN layer) can form a net-shaped uniform net-shaped structure in the constant-temperature and constant-pressure environment set by the second preset temperature and the second preset pressure.
In the step S50, the third undoped gallium nitride sublayer 314 is grown by growth in a Metal Organic Chemical Vapor Deposition (MOCVD) machine, and reaction by introducing a TMGA source in a nitrogen-hydrogen-ammonia mixed atmosphere. The third preset temperature is a fixed value within the range of 1100-1140 ℃, and the third preset pressure is a fixed value within the range of 100-250 torr. Setting a constant temperature and constant pressure environment according to the third preset temperature and the third preset pressure, and preparing the third undoped gallium nitride sublayer 314 on the surface of the silicon nitride layer 313 away from the second undoped gallium nitride sublayer 312.
The thickness of the third undoped gallium nitride sublayer 314 may be 0.01um to 0.1um, and the thickness can be ensured to play a leveling role in this range on the basis of cost minimization, and the defects can be reduced to a proper range.
In the step S60, the fourth preset temperature is a fixed value within a range of 1130 to 1170 ℃, and the fourth preset pressure is a fixed value within a range of 100to 250 torr. Setting a constant temperature and constant pressure environment according to the fourth preset temperature and the fourth preset pressure, and preparing the heat treatment layer 315 on the surface of the third undoped gallium nitride sublayer 314 away from the silicon nitride layer 313. The heat treatment layer 315 can facilitate treatment of the interface to planarize the surface and thereby cover the entire layer of defects that may be formed due to the non-planarity of the grown crystals.
Therefore, the growth form of the first undoped gallium nitride sublayer 311 is changed into a three-dimensional island-like growth under the high-pressure low-temperature condition by the step S20. In step S30, the pressure gradually decreases and the temperature gradually increases, i.e., the temperature and pressure change growth gradually changes to the two-dimensional layered growth, and a three-dimensional/two-dimensional alternate growth mode is formed, i.e., the three-dimensional island growth and the two-dimensional layered growth are alternated. At this time, the direction of the defect is reversed at the interface where the island shape and the layer shape alternate, so that part of the defects are merged and annihilated. The time required by the chamber stabilization can be saved through the temperature and pressure change and the relative constant temperature and pressure, the interface can be clearer, and the probability of defect combination and annihilation can be increased by using a multi-pair circulation mode.
Subsequently, in step S40, the SiN layer grows at constant temperature and constant pressure to form a mesh structure, so that on one hand, part of the defects are blocked and extend upwards, and on the other hand, part of the defects penetrate through the mesh holes, so that the defects are turned in direction and merged and annihilated. In step S50, the third undoped gan sublayer 314 is grown at constant temperature and pressure and in the form of two-dimensional layer growth, which serves as a re-filling function. Finally, in step S60, the heat treatment layer 315 does not grow crystal any more, and the temperature is simply increased to increase H2And (4) flow rate. By high temperature and high H2The atmosphere is favorable for processing the interface to flatten the surface, thereby covering the defects formed by the whole layer of the grown crystal which is not paved.
In one embodiment, the method for manufacturing a light emitting diode chip further includes:
s70, according to the steps S20 to S60, the first undoped gallium nitride sublayer 311, the second undoped gallium nitride sublayer 312, the silicon nitride layer 313, the third undoped gallium nitride sublayer 314, and the heat treatment layer 315 are sequentially and cyclically prepared on the surface of the heat treatment layer 315 away from the third undoped gallium nitride sublayer 314.
Through the steps S20 to S60, the growth conditions are controlled by setting the chamber temperature and pressure, and a loop (the first undoped gallium nitride sublayer 311/the second undoped gallium nitride sublayer 312/the three-dimensional island-shaped structure 3111/the silicon nitride layer 313/the third undoped gallium nitride sublayer 314/the heat treatment layer 315) cyclically grows for 5 to 50 cycles. The defects can be turned, combined and annihilated with high probability by a three-dimensional/two-dimensional alternate growth mode, temperature and pressure change at the interface and multiple times of cyclic growth. Meanwhile, the third undoped gallium nitride sublayer 314 (filling layer), the silicon nitride layer 313 and the heat treatment layer 315 also serve as defects blocking layers. Therefore, the LED structure with high crystal quality can be prepared by the preparation method of the LED, and the luminous efficiency of the LED is improved.
In one embodiment, in the step S30, the second undoped gallium nitride sublayer 312 is prepared on the surface of the first undoped gallium nitride sublayer 311 away from the buffer layer 20 in a temperature varying and pressure varying environment with a gradually increasing temperature and a gradually decreasing pressure under the environment with a temperature of 1100 ℃ to 1140 ℃ and a pressure of 100torr to 250 torr.
In one embodiment, in the step S10, the substrate 10 may be a sapphire substrate, a Si substrate, or a SiC substrate. And, the buffer layer 20 is grown on the surface of the substrate 10 at about 550 °, the buffer layer 20 being GaN. The buffer layer 20 has a thickness of 25nm to 35 nm.
In the step S20, the first undoped gallium nitride sublayer 311(uGaN0 layer) with a thickness of 0.05 μm is prepared on the surface of the buffer layer 20 away from the substrate 10 under a constant temperature and pressure environment with a temperature of 1090 ℃ and a pressure of 350 torr.
In the step S30, the temperature 1090 ℃ in the step S20 is gradually raised to 1120 ℃, and the pressure 350torr in the step S20 is gradually reduced to 150torr in the variable temperature and pressure environment, so that the second undoped gallium nitride sublayer 312 (the uGaN1 layer) with a thickness of 0.05 μm is prepared on the surface of the first undoped gallium nitride sublayer 311 away from the buffer layer 20.
In the step S40, SiH is introduced as the gas4Under the constant temperature and pressure environment with the growth temperature of 1120 ℃ and the growth pressure of 150torr, the second undoped gallium nitride sublayer 312 is far away from the first undoped nitrogenThe surface of the gallium nitride sublayer 311 is prepared with the silicon nitride layer 313(SiN layer) having a thickness of 0.01 um.
In the step S50, under the constant temperature and pressure environment with the growth temperature of 1120 ℃ and the growth pressure of 150torr, the third undoped gallium nitride sublayer 314 (the ugn 2 layer) with the thickness of 0.02um is prepared on the surface of the silicon nitride layer 313 away from the second undoped gallium nitride sublayer 312.
In the step S60, H is introduced2And rapidly raising the growth temperature to 1150 ℃ by using gas 12L and under the constant temperature and pressure environment with the growth pressure of 150torr, and preparing the heat treatment layer 315 on the surface of the third undoped gallium nitride sublayer 314 far away from the silicon nitride layer 313.
And growing the undoped gallium nitride layer 30 on the surface of the buffer layer 20 according to the steps S20-S60 and the cycle growth period set as 10 periods. The undoped gallium nitride layer 30 prepared by the light emitting diode preparation method includes 10 sub gallium nitride layers 310 (a first undoped gallium nitride sub-layer 311, a second undoped gallium nitride sub-layer 312, a silicon nitride layer 313, a third undoped gallium nitride sub-layer 314, and a heat treatment layer 315).
The preparation method of the light-emitting diode further comprises the following steps:
s70, growing the high-temperature N-type semiconductor layer 40(N-GaN layer) at the growth temperature of 1070-1110 ℃, wherein the Si doping concentration is 1.00E19-4.00E19, and the thickness is 0.5-2.0 μm.
S80, fabricating the mqw layer 50 on the surface of the N-type semiconductor layer 40 away from the undoped gan layer 30. Wherein the number of cycles is 8 to 15 when the MQW well layer 50 is prepared. The multiple quantum well layer 50 is composed of an InxGa (1-x) N (x is 0.20-0.22) quantum well layer and a GaN barrier layer doped with Si. The thickness of the single-layer quantum well is 20 nm-40 nm, and the thickness of the single-quantum barrier layer is 100 nm-140 nm.
S90, preparing the high-temperature P-type semiconductor layer 60 (P-type GaN layer) with the Mg being doped at the wavelength of 100nm to 120nm on the surface of the multiple quantum well layer 50 far away from the N-type semiconductor layer 40 at the growth temperature of 900 ℃ to 1000 ℃.
By the preparation method of the light-emitting diode, a large number of defects can be eliminated, the quality of a crystal is improved, the problems of electric leakage of a leakage channel and poor antistatic capability caused by the defects are solved, non-radiative light emission with the defects generated by the defects extending to the multi-quantum well layer 50 is avoided, and the light-emitting efficiency of the light-emitting diode chip is improved.
In one embodiment, the method for manufacturing the light emitting diode may employ a Metal-organic Chemical Vapor Deposition (MOCVD) method, a MOVPE (Metal-organic Chemical Vapor-Phase epitoxy) method, or the like.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A light emitting diode chip, comprising:
the device comprises a substrate (10), wherein a buffer layer (20) is arranged on the surface of the substrate (10);
the undoped gallium nitride layer (30) is arranged on the surface, far away from the substrate (10), of the buffer layer (20);
the undoped gallium nitride layer (30) comprises a plurality of sub gallium nitride layers (310), and the plurality of sub gallium nitride layers (310) are sequentially arranged on the surface, far away from the substrate (10), of the buffer layer (20);
each sub-gallium nitride layer (310) comprises a first undoped gallium nitride sub-layer (311) and a second undoped gallium nitride sub-layer (312), wherein the first undoped gallium nitride sub-layer (311) is arranged on the surface of the buffer layer (20) far away from the substrate (10), and the second undoped gallium nitride sub-layer (312) is arranged on the surface of the first undoped gallium nitride sub-layer (311) far away from the buffer layer (20);
the first undoped gallium nitride sublayer (311) comprises a plurality of three-dimensional island-shaped structures (3111), the three-dimensional island-shaped structures (3111) are sequentially arranged and arranged on the surface of the buffer layer (20) far away from the substrate (10), and the second undoped gallium nitride sublayer (312) is arranged on the surface of the three-dimensional island-shaped structures (3111) far away from the buffer layer (20).
2. The light emitting diode chip of claim 1, wherein the second undoped gallium nitride sublayer (312) is a two-dimensional layered structure disposed on a surface of the plurality of three-dimensional island-shaped structures (3111) away from the buffer layer (20).
3. The light emitting diode chip of claim 1, wherein each said sub-gallium nitride layer (310) further comprises:
and the silicon nitride layer (313) is arranged on the surface of the second undoped gallium nitride sublayer (312) far away from the first undoped gallium nitride sublayer (311).
4. The light emitting diode chip of claim 3, wherein each said sub-gallium nitride layer (310) further comprises:
a third undoped gallium nitride sublayer (314) disposed on a surface of the silicon nitride layer (313) away from the second undoped gallium nitride sublayer (312).
5. The light emitting diode chip of claim 4, wherein each said sub-gallium nitride layer (310) further comprises:
and the heat treatment layer (315) is arranged on the surface of the third undoped gallium nitride sublayer (314) far away from the silicon nitride layer (313).
6. The light emitting diode chip of claim 5, wherein the first undoped gallium nitride sub-layer (311) of two adjacent sub-gallium nitride layers (310) of the plurality of sub-gallium nitride layers (310) is disposed on a surface of the heat treatment layer (315) away from the third undoped gallium nitride sub-layer (314).
7. The light emitting diode chip of claim 1, wherein said undoped gallium nitride layer (30) comprises between 5 and 50 of said sub-gallium nitride layers (310).
8. A preparation method of a light-emitting diode chip is characterized by comprising the following steps:
s10, providing a substrate (10), and preparing a buffer layer (20) on the surface of the substrate (10);
s20, preparing a first undoped gallium nitride sublayer (311) on the surface of the buffer layer (20) far away from the substrate (10) according to a first preset temperature and a first preset pressure under the environment of 1070-1110 ℃ and 250-450 torr of pressure;
s30, preparing a second undoped gallium nitride sublayer (312) on the surface of the first undoped gallium nitride sublayer (311) far away from the buffer layer (20) in a temperature and pressure changing environment with the temperature of 1100-1140 ℃ and the pressure of 100-250 torr;
s40, preparing a silicon nitride layer (313) on the surface of the second undoped gallium nitride sublayer (312) far away from the first undoped gallium nitride sublayer (311) according to a second preset temperature and a second preset pressure under the environment of 1100-1140 ℃ and 100-250 torr pressure;
s50, preparing a third undoped gallium nitride sublayer (314) on the surface of the silicon nitride layer (313) far away from the second undoped gallium nitride sublayer (312) according to a third preset temperature and a third preset pressure in the environment with the temperature of 1100-1140 ℃ and the pressure of 100-250 torr;
s60, preparing a heat treatment layer (315) on the surface of the third undoped gallium nitride sublayer (314) far away from the silicon nitride layer (313) according to a fourth preset temperature and a fourth preset pressure under the environment of 1130-1170 ℃ and 100-250 torr pressure.
9. The method for manufacturing a light-emitting diode chip as claimed in claim 8, further comprising:
s70, according to the steps S20-S60, the first undoped gallium nitride sublayer (311), the second undoped gallium nitride sublayer (312), the silicon nitride layer (313), the third undoped gallium nitride sublayer (314) and the heat treatment layer (315) are sequentially and circularly prepared on the surface of the heat treatment layer (315) far away from the third undoped gallium nitride sublayer (314).
10. The method for fabricating a light emitting diode chip as claimed in claim 8, wherein in the step S30, under the environment of temperature 1100 ℃ -1140 ℃ and pressure 100 torr-250 torr, and under the environment of temperature variation and pressure variation with gradually increasing temperature and gradually decreasing pressure, the second undoped gallium nitride sublayer (312) is fabricated on the surface of the first undoped gallium nitride sublayer (311) away from the buffer layer (20).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038461A (en) * | 2020-07-17 | 2020-12-04 | 华灿光电(苏州）有限公司 | Light emitting diode epitaxial wafer, light emitting diode chip and preparation method of light emitting diode epitaxial wafer |
| CN114657640A (en) * | 2020-12-23 | 2022-06-24 | 中国科学院苏州纳米技术与纳米仿生研究所 | High-quality gallium nitride single crystal and growth method and preparation system thereof |
| CN116978991A (en) * | 2023-09-22 | 2023-10-31 | 江西兆驰半导体有限公司 | LED epitaxial wafer, preparation method thereof and LED |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038461A (en) * | 2020-07-17 | 2020-12-04 | 华灿光电(苏州）有限公司 | Light emitting diode epitaxial wafer, light emitting diode chip and preparation method of light emitting diode epitaxial wafer |
| CN114657640A (en) * | 2020-12-23 | 2022-06-24 | 中国科学院苏州纳米技术与纳米仿生研究所 | High-quality gallium nitride single crystal and growth method and preparation system thereof |
| CN116978991A (en) * | 2023-09-22 | 2023-10-31 | 江西兆驰半导体有限公司 | LED epitaxial wafer, preparation method thereof and LED |
| CN116978991B (en) * | 2023-09-22 | 2023-12-12 | 江西兆驰半导体有限公司 | LED epitaxial wafer, preparation method thereof and LED |
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