CN110752161A - Manufacturing process of basic circuit board and basic circuit board - Google Patents
Manufacturing process of basic circuit board and basic circuit board Download PDFInfo
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- CN110752161A CN110752161A CN201911145198.1A CN201911145198A CN110752161A CN 110752161 A CN110752161 A CN 110752161A CN 201911145198 A CN201911145198 A CN 201911145198A CN 110752161 A CN110752161 A CN 110752161A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 266
- 229910052802 copper Inorganic materials 0.000 claims abstract description 265
- 239000010949 copper Substances 0.000 claims abstract description 265
- 239000000758 substrate Substances 0.000 claims abstract description 138
- 239000000919 ceramic Substances 0.000 claims abstract description 66
- 238000004806 packaging method and process Methods 0.000 claims abstract description 66
- 230000017525 heat dissipation Effects 0.000 claims abstract description 63
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 238000009713 electroplating Methods 0.000 claims description 50
- 238000007747 plating Methods 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 43
- 229920005989 resin Polymers 0.000 claims description 19
- 239000011347 resin Substances 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000005429 filling process Methods 0.000 claims description 7
- 239000007787 solid Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 239000000835 fiber Substances 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920003192 poly(bis maleimide) Polymers 0.000 description 4
- 229920001955 polyphenylene ether Polymers 0.000 description 4
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- -1 allyl compound Chemical class 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to a basic circuit board manufacturing process and a basic circuit board, comprising the following steps: a through hole which is communicated up and down is arranged at a chip bonding pad of the packaging substrate, a silicon chip is welded on the upper part of the chip bonding pad, and a heat conduction copper pad is arranged at the bottom of the chip bonding pad part of the packaging substrate; manufacturing a copper pad clamping groove and a clamping copper column on a ceramic substrate, wherein more than 3 clamping holes are formed in the thickness direction of the packaging substrate, the diameter of the clamping copper column is 95% -99% of the aperture of the clamping hole, the clamping copper column is assembled with the clamping hole, a heat dissipation copper pad is positioned in the copper pad clamping groove, and gaps of 3-20 microns are formed between the periphery and the bottom of the heat dissipation copper pad and the copper pad clamping groove; through the copper facing technology, fill the week side of heat dissipation copper pad and the clearance between bottom and the copper pad draw-in groove, fill the clearance between joint copper post and the joint hole simultaneously, realize packaging substrate and ceramic substrate's assembly, packaging substrate acts as the intermediary, utilizes the copper facing technology to realize that chip and ceramic substrate's heat dissipation copper pad draw-in groove integration are connected, can improve the radiating efficiency greatly.
Description
Technical Field
The invention relates to the technical field of electronic components, in particular to a manufacturing process of a basic circuit board and the manufactured basic circuit board.
Background
Electronic components have been flooded in all aspects of our lives.
The ceramic substrate means that a copper foil is directly bonded to alumina (Al) at a high temperature2O3) Or a special process board on the surface (single or double side) of an aluminum nitride (AlN) ceramic substrate, the copper layer of which is thickThe degree can be more than 2 mm. The prepared composite substrate has excellent electrical insulation performance, high heat conduction characteristic, excellent soft solderability and high adhesion strength, can be etched into various patterns like a PCB (printed circuit board), and has great current carrying capacity. Therefore, the ceramic substrate has become a basic material for high-power electronic circuit structure technology and interconnection technology.
In the prior art, the heat dissipation of the chip is an important issue to be solved in the package of the chip and the ceramic substrate.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a basic circuit board manufacturing process with high heat dissipation efficiency is provided, which comprises
A. Arranging a via hole which is communicated up and down at a chip bonding pad of a packaging substrate, filling the via hole into a solid conductive hole through a copper plating and hole filling process, wherein the via hole is more than 9 holes distributed in an array manner, a silicon chip is welded at the upper part of the chip bonding pad, and a heat conduction copper pad is arranged at the bottom of the chip bonding pad part of the packaging substrate;
B. the method comprises the following steps that copper pad clamping grooves and clamping copper columns are manufactured on a ceramic substrate through an etching process, more than 3 clamping holes are formed in the thickness direction of a packaging substrate, more than 3 clamping copper columns are arranged on the ceramic substrate 2, the diameter of each clamping copper column is 95% -99% of the aperture of each clamping hole, each clamping copper column is assembled with each clamping hole, a heat dissipation copper pad is located in each copper pad clamping groove, and gaps of 3-20 microns are formed between the periphery and the bottom of the heat dissipation copper pad and the copper pad clamping grooves;
C. and gaps between the circumferential sides and the bottoms of the heat dissipation copper pads and the copper pad clamping grooves are filled through a copper plating process, and gaps between the clamping copper columns and the clamping holes are filled at the same time.
In this embodiment, the copper plating process includes electroless copper plating and electrolytic copper plating.
In this embodiment, the thickness of the copper layer of the electroless copper plating is 1 to 3 μm;
when electroplating copper, a double-loop electroplating process is adopted, and electroplating clip clamping points are arranged on the ceramic substrate and the packaging substrate at the same time;
when the gap between the heat dissipation copper pad and the copper pad clamping groove is 3-20 microns, electroplating is carried out by adopting a double-loop electroplating process, and electroplating is carried out through electroplating clip clamping points on the ceramic substrate and the packaging substrate; when the gap between the heat dissipation copper pad and the copper pad clamping groove is smaller than 3 mu m, a single-loop electroplating process is adopted, and electroplating is carried out only through the clamping points of the electroplating clips on the ceramic substrate or the packaging substrate.
A basic circuit board comprises a silicon chip, a ceramic substrate and an encapsulation substrate; the silicon chip is a chip with double-sided bonding pads, a via hole which is communicated up and down is arranged at the chip bonding pad of the packaging substrate, the via hole is filled into a solid conductive hole through a copper plating and hole filling process, the via hole is more than 9 holes distributed in an array, the silicon chip is welded at the upper part of the chip bonding pad, and a heat-conducting copper pad is arranged at the bottom of the chip bonding pad part of the packaging substrate;
the packaging substrate is provided with a heat dissipation copper pad, the heat dissipation copper pad is positioned at one side or the bottom of the silicon chip, and the ceramic substrate is provided with a copper pad clamping groove;
more than 3 clamping holes are formed in the thickness direction of the packaging substrate, more than 3 clamping copper columns are arranged on the ceramic substrate, the diameter of each clamping copper column is 95% -99% of the aperture of each clamping hole, after the clamping copper columns and the clamping holes are assembled, the heat dissipation copper pad is located in the copper pad clamping groove, and gaps of 3-20 microns are formed between the periphery and the bottom of the heat dissipation copper pad 31 and the copper pad clamping groove;
and through a copper plating process, filling a gap between the clamping copper column and the clamping hole, and simultaneously filling a gap between the heat dissipation copper pad and the copper pad clamping groove to realize the assembly of the packaging substrate and the ceramic substrate.
Preferably, the circumferential side of the snap-in hole is a resin or a combination of a resin and a fiber.
Preferably, the clamping hole is provided with a copper plating hole of a copper layer; the clamping copper column is a copper clamping copper column.
Preferably, the ceramic substrate is a circuit board with copper layers on two sides, the ceramic substrate is provided with a first circuit pattern, and the copper clamping copper column is a part of the first circuit pattern;
the packaging substrate at least comprises more than two layers of second circuit patterns, and the copper-plated holes are part of the second circuit patterns;
and after the copper-plated hole and the copper clamping copper column are assembled through a copper plating process, the first circuit graph and the second circuit graph are assembled.
Preferably, the copper clamping copper pillar is higher than other parts of the first circuit pattern; the copper clamping copper column and the other part of the first circuit pattern are made of the same copper layer of the ceramic substrate through different etching processes.
Preferably, the insulating layer of the package substrate is made of one or two of polyimide, BT resin, and epoxy resin.
BT resin is a thermosetting resin formed by using Bismaleimide (BMI) and triazine as main resin components and adding an epoxy resin, a polyphenylene ether resin (PPE), an allyl compound, or the like as a modifying component, and is called BT resin.
Preferably, the insulating layer of the ceramic substrate is aluminum oxide or aluminum nitride.
Preferably, the bottom wall of the copper pad clamping groove is provided with a thermoelectric conversion layer, and the thermoelectric conversion layer is fixedly connected with the bottom wall of the heat dissipation copper pad through a copper plating layer.
Preferably, the copper plating process includes electroless copper plating and electrolytic copper plating.
Preferably, the thickness of the copper layer of the electroless copper plating is 1-3 μm;
when electroplating copper, a double-loop electroplating process is adopted, and electroplating clip clamping points are arranged on the ceramic substrate and the packaging substrate at the same time;
when the gap between the heat dissipation copper pad and the copper pad clamping groove is 3-20 microns, electroplating is carried out by adopting a double-loop electroplating process, and electroplating is carried out through electroplating clip clamping points on the ceramic substrate and the packaging substrate; when the gap between the heat dissipation copper pad and the copper pad clamping groove is smaller than 3 mu m, a single-loop electroplating process is adopted, and electroplating is carried out only through the clamping points of the electroplating clips on the ceramic substrate or the packaging substrate.
The invention has the beneficial effects that: the invention relates to a basic circuit board manufacturing process and a basic circuit board, comprising the following steps: a through hole which is communicated up and down is arranged at a chip bonding pad of the packaging substrate, a silicon chip is welded on the upper part of the chip bonding pad, and a heat conduction copper pad is arranged at the bottom of the chip bonding pad part of the packaging substrate; manufacturing a copper pad clamping groove and a clamping copper column on a ceramic substrate, wherein more than 3 clamping holes are formed in the thickness direction of the packaging substrate, the diameter of the clamping copper column is 95% -99% of the aperture of the clamping hole, the clamping copper column is assembled with the clamping hole, a heat dissipation copper pad is positioned in the copper pad clamping groove, and gaps of 3-20 microns are formed between the periphery and the bottom of the heat dissipation copper pad and the copper pad clamping groove; through the copper facing technology, fill the week side of heat dissipation copper pad and the clearance between bottom and the copper pad draw-in groove, fill the clearance between joint copper post and the joint hole simultaneously, realize packaging substrate and ceramic substrate's assembly, packaging substrate acts as the intermediary, utilizes the copper facing technology to realize that chip and ceramic substrate's heat dissipation copper pad draw-in groove integration are connected, can improve the radiating efficiency greatly.
The invention also relates to a basic circuit board, which comprises a silicon chip, a ceramic substrate and a packaging substrate; the silicon chip is a chip with double-sided bonding pads, a via hole which is communicated up and down is arranged at the chip bonding pad of the packaging substrate, the via hole is filled into a solid conductive hole through a copper plating and hole filling process, the via hole is more than 9 holes distributed in an array, the silicon chip is welded at the upper part of the chip bonding pad, and a heat-conducting copper pad is arranged at the bottom of the chip bonding pad part of the packaging substrate; the packaging substrate is provided with a heat dissipation copper pad, the heat dissipation copper pad is positioned at one side or the bottom of the silicon chip, and the ceramic substrate is provided with a copper pad clamping groove; more than 3 clamping holes are formed in the thickness direction of the packaging substrate, more than 3 clamping copper columns are arranged on the ceramic substrate, the diameter of each clamping copper column is 95% -99% of the aperture of each clamping hole, after the clamping copper columns and the clamping holes are assembled, the heat dissipation copper pad is located in the copper pad clamping groove, and gaps of 3-20 microns are formed between the periphery and the bottom of the heat dissipation copper pad 31 and the copper pad clamping groove; and through a copper plating process, filling a gap between the clamping copper column and the clamping hole, and simultaneously filling a gap between the heat dissipation copper pad and the copper pad clamping groove to realize the assembly of the packaging substrate and the ceramic substrate. The packaging substrate serves as an intermediary, the packaging substrate can be made thin, the BT and other high-heat-dissipation materials are used for manufacturing, the heat-dissipation copper pad at the bottom of the chip and the heat-dissipation copper pad clamping groove of the ceramic substrate are integrally connected by utilizing a copper plating process, the heat-dissipation copper pad clamping groove and the large-area copper block on the periphery of the heat-dissipation copper pad clamping groove are integrally and tightly combined through the copper plating process, and the heat-dissipation efficiency can be greatly improved.
Drawings
The basic circuit board of the present invention will be further described with reference to the accompanying drawings.
FIG. 1 is a flow chart of a basic circuit board manufacturing process of the present invention.
Fig. 2 is an exploded view of a base circuit board from a first perspective of the present invention.
Fig. 3 is an exploded view of a base circuit board of the present invention from a second perspective.
Fig. 4 is an exploded view of a third perspective of a base circuit board of the present invention.
Fig. 5 is a schematic structural diagram of a package substrate of a basic circuit board according to the present invention.
In the figure:
1-a silicon chip; 2-a ceramic substrate; 21-copper pad slot; 22-clamping a copper column; 3-a package substrate; 31-a heat-dissipating copper pad; 32-a clamping hole; 33-via holes; 34-a chip pad; 4-a thermoelectric conversion layer; 5-large area heat dissipation copper layer.
Detailed Description
The manufacturing process of the basic circuit board and the corresponding basic circuit board of the present invention will be further described with reference to fig. 1 to 5.
First, a manufacturing process of the basic circuit board is described.
A. Arranging a via hole 33 which is vertically communicated at a chip bonding pad 34 of the packaging substrate 3, filling the via hole 33 into a solid conductive hole through a copper plating and hole filling process, wherein the via hole 33 is more than 9 holes distributed in an array manner, the upper part of the chip bonding pad 34 is welded with the silicon chip 1, and the bottom of the chip bonding pad 34 of the packaging substrate 3 is provided with a heat conducting copper pad 31;
B. the method comprises the following steps that a copper pad clamping groove 21 and a clamping copper column 22 are manufactured on a ceramic substrate 2 through an etching process, more than 3 clamping holes 32 are formed in the thickness direction of a packaging substrate 3, more than 3 clamping copper columns 22 are arranged on the ceramic substrate 2, the diameter of each clamping copper column 22 is 95% -99% of the diameter of each clamping hole 32, the clamping copper columns 22 are assembled with the clamping holes 32, a heat dissipation copper pad 31 is located in the copper pad clamping groove 21, and gaps of 3-20 mu m are formed between the periphery and the bottom of the heat dissipation copper pad 31 and the copper pad clamping groove 21;
C. gaps between the circumferential side and the bottom of the heat dissipation copper pad 31 and the copper pad clamping groove 21 are filled through a copper plating process, and gaps between the clamping copper columns 22 and the clamping holes 32 are filled.
In this embodiment, the copper plating process includes electroless copper plating and electrolytic copper plating.
In this embodiment, the thickness of the copper layer of the electroless copper plating is 1 to 3 μm;
when electroplating copper, a double-loop electroplating process is adopted, and electroplating clip clamping points are arranged on the ceramic substrate 2 and the packaging substrate 3 at the same time;
when the gap between the heat dissipation copper pad 31 and the copper pad clamping groove 21 is 3-20 microns, electroplating is carried out by adopting a double-loop electroplating process, and electroplating is carried out through electroplating clip clamping points on the ceramic substrate 2 and the packaging substrate 3; when the gap between the heat dissipation copper pad 31 and the copper pad clamping groove 21 is smaller than 3 μm, a single-loop electroplating process is adopted, and electroplating is carried out only through the clamping points of the electroplating clips on the ceramic substrate 2 or the packaging substrate 3.
Then, a base circuit board manufactured based on the above manufacturing process will be described.
A basic circuit board comprises a silicon chip 1, a ceramic substrate 2 and a packaging substrate 3;
the silicon chip 1 is a chip with double-sided bonding pads, a via hole 33 which is vertically communicated is arranged at a chip bonding pad 34 of the packaging substrate 3, the via hole 33 is filled into a solid conductive hole through copper plating and hole filling processes, the via hole 33 is more than 9 holes distributed in an array manner, the silicon chip 1 is welded at the upper part of the chip bonding pad 34, and a heat-conducting copper pad 31 is arranged at the bottom of the chip bonding pad 34 of the packaging substrate 3;
the packaging substrate 3 is provided with a heat dissipation copper pad 31, the heat dissipation copper pad 31 is positioned at one side or the bottom of the silicon chip 1, and the ceramic substrate 2 is provided with a copper pad clamping groove 21;
more than 3 clamping holes 32 are formed in the thickness direction of the packaging substrate 3, more than 3 clamping copper columns 22 are arranged on the ceramic substrate 2, the diameter of each clamping copper column 22 is 95% -99% of the aperture of each clamping hole 32, after the clamping copper columns 22 and the clamping holes 32 are assembled, the heat dissipation copper pad 31 is located in the copper pad clamping groove 21, and gaps of 3-20 microns are formed between the periphery and the bottom of the heat dissipation copper pad 31 and the copper pad clamping groove 21;
and through a copper plating process, a gap between the clamping copper column 22 and the clamping hole 32 is filled, and meanwhile, a gap between the heat dissipation copper pad 31 and the copper pad clamping groove 21 is filled, so that the assembly of the packaging substrate 3 and the ceramic substrate 2 is realized.
The packaging substrate serves as an intermediary, the packaging substrate can be made thin, the BT and other high-heat-dissipation materials are used for manufacturing, the heat-dissipation copper pad at the bottom of the chip and the heat-dissipation copper pad clamping groove of the ceramic substrate are integrally connected by utilizing a copper plating process, the heat-dissipation copper pad clamping groove and the large-area copper block on the periphery of the heat-dissipation copper pad clamping groove are integrally and tightly combined through the copper plating process, and the heat-dissipation efficiency can be greatly improved.
In this embodiment, the circumferential side of the engaging hole 32 is resin or a combination of resin and fiber.
In this embodiment, the clamping hole 32 is provided with a copper plating hole of a copper layer; the clamping copper column 22 is a copper clamping copper column.
In this embodiment, the ceramic substrate 2 is a circuit board with copper layers on both sides, the ceramic substrate 2 is provided with a first circuit pattern, and the copper clamping copper pillar is a part of the first circuit pattern;
the packaging substrate 3 at least comprises more than two layers of second circuit patterns, and the copper-plated holes are part of the second circuit patterns;
and after the copper-plated hole and the copper clamping copper column are assembled through a copper plating process, the first circuit graph and the second circuit graph are assembled.
In this embodiment, the copper clamping copper column is higher than other parts of the first circuit pattern; the copper clamping copper column and the other part of the first circuit pattern are made of the same copper layer of the ceramic substrate through different etching processes.
In this embodiment, the insulating layer of the package substrate 3 is made of one or two of polyimide, BT resin, and epoxy resin.
BT resin is a thermosetting resin formed by using Bismaleimide (BMI) and triazine as main resin components and adding an epoxy resin, a polyphenylene ether resin (PPE), an allyl compound, or the like as a modifying component, and is called BT resin.
In this embodiment, the insulating layer of the ceramic substrate 2 is aluminum oxide or aluminum nitride.
The ceramic substrate means that a copper foil is directly bonded to alumina (Al) at a high temperature2O3) Or a special process plate on the surface (single or double side) of an aluminum nitride (AlN) ceramic substrate. The manufactured ultrathin composite substrate has excellent electrical insulation performance, high heat conduction characteristic, excellent soft solderability and high adhesion strength, can be etched into various patterns like a PCB (printed circuit board), and has great current carrying capacity. Therefore, the ceramic substrate has become a basic material for high-power electronic circuit structure technology and interconnection technology.
In this embodiment, the bottom wall of the copper pad slot 21 is provided with the thermoelectric conversion layer 4, and the thermoelectric conversion layer 4 is connected with the bottom wall of the heat dissipation copper pad 31 through the copper plating layer.
In this embodiment, the copper plating process includes electroless copper plating and electrolytic copper plating.
In this embodiment, the thickness of the copper layer of the electroless copper plating is 1 to 3 μm;
when electroplating copper, a double-loop electroplating process is adopted, and electroplating clip clamping points are arranged on the ceramic substrate 2 and the packaging substrate 3 at the same time;
when the gap between the heat dissipation copper pad 31 and the copper pad clamping groove 21 is 3-20 microns, electroplating is carried out by adopting a double-loop electroplating process, and electroplating is carried out through electroplating clip clamping points on the ceramic substrate 2 and the packaging substrate 3; when the gap between the heat dissipation copper pad 31 and the copper pad clamping groove 21 is smaller than 3 μm, a single-loop electroplating process is adopted, and electroplating is carried out only through the clamping points of the electroplating clips on the ceramic substrate 2 or the packaging substrate 3.
The present invention is not limited to the above embodiments, and the technical solutions of the above embodiments of the present invention may be combined with each other in a crossing manner to form a new technical solution, and all technical solutions formed by adopting equivalent substitutions fall within the protection scope of the present invention.
Claims (10)
1. A basic circuit board manufacturing process is characterized by comprising the following steps:
A. arranging a via hole (33) which is vertically communicated at a chip bonding pad (34) of a packaging substrate (3), filling the via hole (33) into a solid conductive hole by a copper plating and hole filling process, wherein the via hole (33) is more than 9 holes distributed in an array, a silicon chip (1) is welded at the upper part of the chip bonding pad (34), and a heat-conducting copper pad (31) is arranged at the bottom of the chip bonding pad (34) of the packaging substrate (3);
B. the packaging structure comprises a ceramic substrate (2), wherein copper pad clamping grooves (21) and clamping copper columns (22) are manufactured on the ceramic substrate (2) through an etching process, more than 3 clamping holes (32) are formed in the thickness direction of the packaging substrate (3), more than 3 clamping copper columns (22) are arranged on the ceramic substrate (2), the diameter of each clamping copper column (22) is 95% -99% of the aperture of each clamping hole (32), each clamping copper column (22) is assembled with each clamping hole (32), a heat dissipation copper pad (31) is located in each copper pad clamping groove (21), and gaps of 3-20 mu m are formed between the periphery and the bottom of the heat dissipation copper pad (31) and the copper pad clamping grooves (21);
C. through the copper plating process, fill the week side and the bottom of heat dissipation copper pad (31) with the clearance between copper pad draw-in groove (21), fill joint copper post (22) simultaneously with the clearance between joint hole (32).
2. The base circuit board-based manufacturing process of claim 1, wherein the copper plating process comprises electroless copper plating and electrolytic copper plating.
3. The manufacturing process based on the basic circuit board of claim 2, wherein the thickness of the copper layer of the electroless copper plating is 1 to 3 μm;
during the copper electroplating, a double-loop electroplating process is adopted, and electroplating clip clamping points are arranged on the ceramic substrate (2) and the packaging substrate (3) at the same time;
when the gap between the heat dissipation copper pad (31) and the copper pad clamping groove (21) is 3-20 microns, electroplating is carried out by adopting a double-loop electroplating process, and electroplating is carried out through electroplating clip clamping points on the ceramic substrate (2) and the packaging substrate (3); when the gap between the heat dissipation copper pad (31) and the copper pad clamping groove (21) is smaller than 3 mu m, a single-loop electroplating process is adopted, and electroplating is carried out only through the clamping points of the electroplating clips on the ceramic substrate (2) or the packaging substrate (3).
4. A basic circuit board comprises a silicon chip (1), and is characterized by further comprising a ceramic substrate (2) and a packaging substrate (3);
the silicon chip (1) is a chip with double-sided bonding pads, a through hole (33) which is communicated up and down is arranged at a chip bonding pad (34) of a packaging substrate (3), the through hole (33) is filled into a solid conductive hole through a copper plating and hole filling process, the through hole (33) is more than 9 holes distributed in an array manner, the silicon chip (1) is welded on the upper part of the chip bonding pad (34), and a heat conduction copper pad (31) is arranged at the bottom of the chip bonding pad (34) of the packaging substrate (3);
the packaging substrate (3) is provided with a heat dissipation copper pad (31), the heat dissipation copper pad (31) is positioned on one side or the bottom of the silicon chip (1), and the ceramic substrate (2) is provided with a copper pad clamping groove (21);
the packaging structure is characterized in that more than 3 clamping holes (32) are formed in the packaging substrate (3) in the thickness direction, more than 3 clamping copper columns (22) are arranged on the ceramic substrate (2), the diameter of each clamping copper column (22) is 95% -99% of the aperture of each clamping hole (32), the clamping copper columns (22) are assembled with the clamping holes (32), the heat dissipation copper pad (31) is located in the copper pad clamping groove (21), and gaps of 3-20 mu m are formed between the circumferential sides and the bottom of the heat dissipation copper pad (31) and the copper pad clamping groove (21);
through the copper facing technology, fill joint copper post (22) with clearance between joint hole (32), simultaneously, fill heat dissipation copper pad (31) with clearance between copper pad draw-in groove (21), realize packaging substrate (3) with the assembly of ceramic substrate (2).
5. The base circuit board according to claim 4, wherein the peripheral side of the click hole (32) is a resin or a combination of a resin and a fiber.
6. The base circuit board of claim 4, wherein the snap-in hole (32) is provided with a copper plated hole of a copper layer; the clamping copper column (22) is a copper clamping copper column.
7. The base circuit board of claim 6, wherein the ceramic substrate (2) is a circuit board with copper layers on both sides, the ceramic substrate (2) is provided with a first circuit pattern, and the copper snap copper pillars are part of the first circuit pattern;
the packaging substrate (3) at least comprises more than two layers of second circuit patterns, and the copper-plated holes are part of the second circuit patterns;
and after the copper-plated hole and the copper clamping copper column are assembled through a copper plating process, the first circuit pattern and the second circuit pattern are assembled.
8. The base circuit board of claim 7, wherein the copper snap copper posts are higher than other portions of the first circuit pattern; the copper clamping copper column and the other parts of the first circuit pattern are made of the same copper layer of the ceramic substrate through different etching processes.
9. The base circuit board of claim 8, wherein the insulating layer of the package substrate (3) is made of one or two of polyimide, BT resin or epoxy resin; the insulating layer of the ceramic substrate (2) is aluminum oxide or aluminum nitride.
10. The base circuit board of claim 8, wherein the bottom wall of the copper pad slot (21) is provided with a thermoelectric conversion layer (4), and the thermoelectric conversion layer (4) is firmly connected with the bottom wall of the heat dissipation copper pad (31) through a copper plating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911145198.1A CN110752161A (en) | 2019-11-21 | 2019-11-21 | Manufacturing process of basic circuit board and basic circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911145198.1A CN110752161A (en) | 2019-11-21 | 2019-11-21 | Manufacturing process of basic circuit board and basic circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110752161A true CN110752161A (en) | 2020-02-04 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911145198.1A Pending CN110752161A (en) | 2019-11-21 | 2019-11-21 | Manufacturing process of basic circuit board and basic circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110752161A (en) |
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2019
- 2019-11-21 CN CN201911145198.1A patent/CN110752161A/en active Pending
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