CN110750950A - Method for automatically shielding layout key signal line - Google Patents
Method for automatically shielding layout key signal line Download PDFInfo
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- CN110750950A CN110750950A CN201910973158.XA CN201910973158A CN110750950A CN 110750950 A CN110750950 A CN 110750950A CN 201910973158 A CN201910973158 A CN 201910973158A CN 110750950 A CN110750950 A CN 110750950A
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Abstract
The invention discloses a method for automatically shielding a key signal line of a layout, which comprises the following steps: step 1, opening a layout, and selecting a key signal line without shielding; step 2, distinguishing the types of the key signal lines; step 3, determining the shielding range of the key signal line; step 4, providing coordinates of the shielding range position of the key signal wire; and 5, selecting a shielding mode for the key signal line, and automatically generating shielding after confirmation. The layout automatically shielded by adopting the method meets the shielding requirement of the key signal line, greatly shortens the shielding adding time of the integrated circuit layout design, reduces the influence on the original layout as much as possible, so that the whole circuit design flow is more efficient, ensures the consistency of parasitic parameters of a plurality of key signal lines after automatic shielding, ensures the matching precision of the shielded related key signal lines and the like.
Description
Technical Field
The invention belongs to the field of automatic design of integrated circuit layouts, and particularly relates to a method for automatically shielding a layout key signal line.
Background
In a high-precision analog integrated circuit, there are many key signal lines, which are generally divided into a sensitive signal line and a noise signal line, the sensitive signal line is a signal line susceptible to noise signal interference, such as an input of an analog-to-digital converter, an input of a high-precision comparator, a signal with very low amplitude, and the noise signal line is a signal line generated by a noise source, such as a high-frequency digital circuit, a PLL, and the like, if the key signal line is not shielded or improperly processed, the sensitive signal is susceptible to interference, which reduces the reliability of the circuit, even causes the circuit to work abnormally, and therefore, the key signal line needs to be shielded in layout design, but the current processing method adopts manual processing, such as fig. 1, all key signal lines need to be manually processed, the work is cumbersome, and particularly in a large-scale digital-to-analog hybrid integrated circuit layout, the design efficiency of the integrated circuit layout is greatly affected, meanwhile, the consistency of parasitic parameters of a plurality of key signal lines after shielding cannot be ensured.
Disclosure of Invention
Aiming at the problems, the invention provides a method for automatically shielding the key signal lines of the layout, which overcomes the problem of low efficiency of manual shielding and ensures the consistency of parasitic parameters of a plurality of key signal lines after shielding; the universality is stronger.
In order to solve the technical problems, the invention adopts the following technical scheme:
a method for automatically shielding a layout key signal line comprises the following steps:
step 1, opening a layout, and selecting a key signal line without shielding;
step 2, distinguishing the types of the key signal lines;
step 3, determining the shielding range of the key signal line;
step 4, providing coordinates of the shielding range position of the key signal wire;
and 5, selecting a shielding mode for the key signal line, and automatically generating shielding after confirmation.
Further, in step 1, the layout is opened in the environment of Virtuoso software.
Further, in step 2, the key signal line types include a sensitive signal line and a noise signal line.
Further, in step 3, the mask range includes an overall mask and a segmented mask.
Further, in step 4, the coordinates of the shielding range of the key signal line are the coordinates of two diagonal positions of the rectangle of the key signal line.
Further, when the shielding range is the whole shielding, the coordinates of the shielding position of a pair of key signal wires are given.
Further, when the shielding range is segmented shielding, coordinates of shielding positions of a plurality of pairs of key signal wires are given.
Further, in step 5, after the shielding mode is selected for the key signal line, the shielding effect is displayed, and after the key signal line is visually checked to be qualified, the automatic generation of shielding is confirmed.
Further, in step 5, the shielding manner of the critical signal line includes three types that can be used alone or in combination: 1) placing metal ground wires on two sides of the key signal wire on the same layer of the key signal wire; 2) placing metal ground wire isolation on the upper surface or the lower surface of the layer where the key signal wire is located; 3) the critical signal lines are crossed by tunnels formed by the upper and lower metal ground lines.
Furthermore, the shielding mode of the sensitive signal line adopts three modes to be combined;
the shielding mode of the noise signal wire adopts the combination of 1) and 2).
The invention achieves the following beneficial effects:
compared with the prior art, the layout automatically shielded by adopting the method meets the shielding requirement of the key signal line, the shielding adding time of the integrated circuit layout design is greatly shortened, the influence on the original layout is reduced as much as possible, so that the whole circuit design process is more efficient, in addition, the consistency of parasitic parameters of a plurality of key signal lines after automatic shielding is ensured, the inconsistency brought by manually adding the shielding lines is further reduced, the matching precision of the shielded related key signal lines is ensured, and the like.
In addition, the method can be conveniently applied to the layouts of different IC processes to shield key signal lines only by modifying the process-related physical level definition and related signal definition selected by the layout design, and the technical scheme has strong universality.
Drawings
FIG. 1 is a flow chart of manually adding signal wire shielding wires;
FIG. 2 is a flow chart of the present invention for automatically shielding layout key signal lines;
fig. 3A-3E are schematic diagrams of the key signal line shielding manner of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
According to the method for automatically shielding the key signal line of the layout, as shown in fig. 2, the key signal line, the shielding mode and the like are defined according to the relevant physical level rule of the process and the relevant signals in the layout. After a layout is opened, firstly, selecting a key signal line, checking whether a grounded metal layer shields the key signal line or not, if the key signal line is shielded, directly finishing the shielding, and if the key signal line is not shielded, classifying the types of the signal lines, such as sensitive signal lines, noise signal lines and the like; distinguishing the shielding range of the signal wire, whether the signal wire is integrally shielded or sectionally shielded, and confirming the position of a shielding coordinate; and finally, selecting a shielding mode for the signal wire, flexibly selecting a corresponding shielding mode according to the requirements of the type of the signal wire, the layout environment and the like, displaying a shielding effect by using a dotted line, visually checking to be qualified, and automatically generating shielding after confirmation.
The method comprises the following specific steps:
in the environment of Virtuoso software, after a layout is opened, a key signal line without shielding is selected, such as a metal 2 layer 100, as shown in fig. 3A, the types of the signal lines are distinguished, whether the signal lines are sensitive signal lines or noise signal lines, then the shielding range of the signal lines is distinguished, whether the signal lines are integrally shielded (as shown in fig. 3B) or sectionally shielded (as shown in fig. 3C), the shielding line 101 and the signal lines are of the same layer of metal, and a signal line range needing shielding is given, and a rectangular region surrounded by a lower left corner coordinate and an upper right corner coordinate of the signal lines (in other implementation modes, a rectangular region surrounded by an upper left corner coordinate and a lower right corner coordinate can also be adopted), if the signal lines are integrally shielded, only one pair of coordinates needs to be given, and if the signal lines are sectionally shielded, a plurality of pairs of coordinates need to. And selecting a shielding mode for the signal wire, flexibly selecting a corresponding shielding mode according to the shielding grade of the signal wire, the layout environment and other requirements, displaying a shielding effect by using a dotted line, visually checking to be qualified, and automatically generating shielding after confirmation.
The signal line is generally shielded in the following manner: 1) the method comprises the following steps that grounded shielding wires 101 are arranged on two sides of a signal wire on the same layer of the signal wire; 2) placing grounded shielding wire isolation on or under the layer where the signal wire is positioned; 3) the signal lines are tunneled by the upper and lower grounded shield lines. The three shielding modes can be used independently or in combination, the shielding modes 1), 2) and 3) are higher and higher in grade, the general sensitive signal line can be selected from three modes, and the noise signal line can be selected from 1) and 2) modes. Mode 1) and mode 2) are combined, and a metal 1 layer 102 is placed below the metal 2 layer 100 of the signal line for shielding. Fig. 3E shows a combination of three ways, where the signal line, i.e., metal 2 layer 100, is penetrated by the metal 1 layer 102 and the metal 3 layer 103 to form a ground tunnel.
The method for automatically shielding the key signal lines is adopted, the shielding adding time of the integrated circuit layout design is greatly shortened, the influence on the original layout is reduced as much as possible, the whole layout design process is more efficient, in addition, the consistency of parasitic parameters of a plurality of key signal lines after shielding is ensured, the inconsistency brought by manually adding the shielding lines is further reduced, and the problems of matching precision of the shielded related key signal lines and the like are solved.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for automatically shielding a key signal line of a layout is characterized by comprising the following steps:
step 1, opening a layout, and selecting a key signal line without shielding;
step 2, distinguishing the types of the key signal lines;
step 3, determining the shielding range of the key signal line;
step 4, providing coordinates of the shielding range position of the key signal wire;
and 5, selecting a shielding mode for the key signal line, and automatically generating shielding after confirmation.
2. The method for automatically shielding the key signal wires of the layout as claimed in claim 1, wherein in step 1, the layout is opened under the environment of Virtuoso software.
3. The method for automatically shielding layout key signal lines as claimed in claim 1, wherein in the step 2, the key signal line types comprise sensitive signal lines and noise signal lines.
4. The method for automatically shielding layout key signal lines as claimed in claim 1, wherein in the step 3, the shielding range comprises an integral shielding and a segmented shielding.
5. The method for automatically shielding the key signal lines of the layout as claimed in claim 1, wherein in the step 4, the coordinates of the shielding range position of the key signal line are the coordinates of two diagonal positions of a key signal line rectangle.
6. The method for automatically shielding layout key signal lines as claimed in claim 5, wherein when the shielding range is the whole shielding range, a pair of coordinates of the shielding position of the key signal line is given.
7. The method for automatically shielding the key signal lines of the layout as claimed in claim 5, wherein when the shielding range is segmented shielding, a plurality of pairs of coordinates of the shielding positions of the key signal lines are given.
8. The method for automatically shielding the key signal wires of the layout as claimed in claim 1, wherein in the step 5, after the shielding mode is selected for the key signal wires, the shielding effect is displayed, and after the key signal wires are visually checked to be qualified, the automatic generation of shielding is confirmed.
9. The method for automatically shielding layout key signal lines as claimed in claim 1, wherein in the step 5, the shielding modes of the key signal lines include three modes which can be used independently or in combination: 1) placing metal ground wires on two sides of the key signal wire on the same layer of the key signal wire; 2) placing metal ground wire isolation on the upper surface or the lower surface of the layer where the key signal wire is located; 3) the critical signal lines are crossed by tunnels formed by the upper and lower metal ground lines.
10. The method for automatically shielding the key signal lines of the layout according to claim 1, wherein the shielding mode of the sensitive signal lines is combined by three modes;
the shielding mode of the noise signal wire adopts the combination of 1) and 2).
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Cited By (1)
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CN117236247A (en) * | 2023-11-16 | 2023-12-15 | 零壹半导体技术(常州)有限公司 | Signal shielding wire generation method for chip test |
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CN102314524A (en) * | 2010-06-30 | 2012-01-11 | 中国科学院微电子研究所 | Method for optimizing electromagnetic distribution of integrated circuit layout |
CN103678771A (en) * | 2013-11-13 | 2014-03-26 | 北京工业大学 | Automatic layout method for power/ground TSV positions in 3D integrated circuit |
CN109543309A (en) * | 2018-11-23 | 2019-03-29 | 珠海市微半导体有限公司 | A kind of interference investigation method based on domain key signal |
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Patent Citations (6)
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US6510545B1 (en) * | 2000-01-19 | 2003-01-21 | Sun Microsystems, Inc. | Automated shielding algorithm for dynamic circuits |
JP2004336015A (en) * | 2003-04-14 | 2004-11-25 | Kawasaki Microelectronics Kk | Wiring method and cad equipment |
CN1707773A (en) * | 2004-06-04 | 2005-12-14 | 松下电器产业株式会社 | Standard cell, semiconductor integrated circuit device of standard cell scheme and layout design method for semiconductor integrated circuit device |
CN102314524A (en) * | 2010-06-30 | 2012-01-11 | 中国科学院微电子研究所 | Method for optimizing electromagnetic distribution of integrated circuit layout |
CN103678771A (en) * | 2013-11-13 | 2014-03-26 | 北京工业大学 | Automatic layout method for power/ground TSV positions in 3D integrated circuit |
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CN117236247A (en) * | 2023-11-16 | 2023-12-15 | 零壹半导体技术(常州)有限公司 | Signal shielding wire generation method for chip test |
CN117236247B (en) * | 2023-11-16 | 2024-01-23 | 零壹半导体技术(常州)有限公司 | Signal shielding wire generation method for chip test |
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