CN106815384A - A kind of LEF storehouses and the method for GDS storehouses obstacle figure layer comparison check - Google Patents

A kind of LEF storehouses and the method for GDS storehouses obstacle figure layer comparison check Download PDF

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Publication number
CN106815384A
CN106815384A CN201510868355.7A CN201510868355A CN106815384A CN 106815384 A CN106815384 A CN 106815384A CN 201510868355 A CN201510868355 A CN 201510868355A CN 106815384 A CN106815384 A CN 106815384A
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China
Prior art keywords
storehouses
gds
lef
layer
obstacle
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CN201510868355.7A
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Chinese (zh)
Inventor
傅静静
陈彬
董森华
刘毅
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Huada Empyrean Software Co Ltd
Beijing CEC Huada Electronic Design Co Ltd
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Beijing CEC Huada Electronic Design Co Ltd
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Priority to CN201510868355.7A priority Critical patent/CN106815384A/en
Publication of CN106815384A publication Critical patent/CN106815384A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

With continuing to develop for super large-scale integration, in standard cell lib design and the design of IP modules, the LEF storehouses and increasingly huger GDS storehouses for becoming increasingly complex can be all faced.How to ensure the uniformity between LEF library units and GDS library units, improve designing quality and have become industry focus of attention.This paper presents a kind of method, for each corresponding wiring layer, the pin figure and OBS obstacle figure layer figures in LEF storehouses are extracted, the covering relation of shape in comparison check and GDS storehouses.If it find that there is the inconsistent situation of design, using graphically result is highlighted, and provide detailed text audit report, user is helped easily to carry out the inspection and amendment of library unit, to ensure designing quality.

Description

A kind of LEF storehouses and the method for GDS storehouses obstacle figure layer comparison check
Technical field
LEF storehouses in IC design define the information such as wiring layer, through hole, the modular unit of physical Design.GDS texts Part form is generally used for the data transfer of Semiconductor Physics making sheet.Set forth herein a kind of effective comparison check method, Ke Yijian The comformity relation of the obstacle figure layer looked between LEF storehouses and GDS storehouses, improves designing quality, it is ensured that the correctness of design.The present invention Belong to EDA design fields.
Background technology
With the development and the expansion of IC design scale of manufacturing process, LEF storehouses(Library Exchange Format)Also become increasingly complex.The library unit information such as wiring layer, through hole, modular unit of physical Design is included in LEF storehouses. GDS is then the general file format of semi-conductor industry, for carrying out semiconductor between design tool, computer and mask manufacturer The data transfer of physics making sheet.As a rule, after the physical layout design in GDS storehouses is completed, LEF storehouses are from corresponding GDS Extracted by extraction tool in storehouse.Need to set a series of related parameters in extraction process to control the thin of extraction Section.If the GDS storehouses of wrong version had been used when extracting, or arrange parameter would be wrong, may result in the LEF of IC design The definition in storehouse is mismatched with the content of the physical layout of GDS, can directly affect the correctness of design, and the problem brought also is difficult to adjust Examination and Wrong localization.
Obstacle figure layer(OBS Layer)It is the definition content in LEF storehouses, it is defined on some physical routings layer Geometric figure, limits the connection of physical routing.For standard cell circuit, the geometrical body in obstacle figure layer is necessarily right One block of metal in respective layer in GDS storehouses is answered, due to line lead need not be entered in these layers or these positions, so carrying Wiring obstacle has been processed into when taking LEF.And for the circuit modules such as IP and I/O, the appearance of obstacle figure layer then because IC designer thinks that user need not be concerned about implementing inside circuit, it is only necessary to pay close attention to the position of circuit pin i.e. Can, therefore the part for removing pin is all covered with OBS.
When the eda tool that existing storehouse checks, comparing between LEF and GDS library units are carried out, often using institute There is the test mode that shape is matched one by one, and can not check whether the obstacle figure layer in LEF storehouses protects it to the figure in GDS storehouses Under.If there is some GDS figures situation not under the covering of obstacle figure layer, it is more likely that can occur with follow-up physical routing Short circuit fault.We propose the obstacle figure layer covering relation of a kind of method, comparison check LEF storehouses and GDS storehouses herein.Pass through Detailed audit report and graphical result shows that help user easily carries out the inspection and amendment of library unit, to ensure Designing quality.
The content of the invention
A kind of method that the present invention proposes LEF storehouses and the obstacle figure layer comparison check of GDS storehouses, this method can be applied in mark Quasi- cell library design review (check) (DR), it is also possible to apply in IP module design review (check) (DR)s.By extracting the line pin figure in LEF library units (pin shape)With OBS obstacle figure layer figures, the figure with corresponding figure layer in GDS storehouses carries out comparison check(cross- check), check whether that all of GDS figures are comprised in the middle of the union of pin figure and obstacle figure layer figure.By text Form carries out result report, and is highlighted in graphical interfaces.
Fig. 1 shows the OBS obstacle figure layer figures in standard block LEF storehouses.In general, in standard block LEF storehouses Wiring obstacle must correspond to the metallic pattern in GDS storehouses, when designer generates the LEF of standard cell lib, can refer to Determining some need not draw the wiring layer of line as OBS obstacle figure layers from pin, so every to appear in these figure layers Figure will turn into obstacle figure layer figure.
Fig. 2 gives the OBS obstacle figure layers in the metal levels of Metal 1 in IP module LEF storehouses.For the guarantor of intellectual property Shield, OBS obstacle figure layers are likely to cover most of area of IP modules, only reserve pin positions, it is ensured that IP modules and outside Interconnection.In order to may insure the figure in 100% covering GDS storehouses, can be with defined parameters pin_obs_spacing.Work as inspection When looking into figure covering relation, pin figure stretch out pin_obs_spacing distance after, then with obstacle figure layer figure Carry out union operation.
Fig. 3 is shown each figure layer figure in GDS storehouses.It can be seen that the geometric figure that GDS library units are included is distributed in Each figure layer.When figure layer title defined in the GDS figure layers title and LEF storehouses is different, it is necessary to specify a mapping Rule(mapping rule), it is stipulated that the figure layer corresponding relation between LEF storehouses and GDS storehouses.For example, M1 layers of correspondence in LEF storehouses Metal1 layers in GDS storehouses.
After figure layer corresponding relation of the LEF storehouses with GDS storehouses is determined, it is possible to carry out the spreadability inspection of obstacle figure layer .In a certain figure layer, first find the pin figure in LEF storehouses, stretch out pin_obs_spacing distances, then with LEF storehouses Defined in obstacle figure layer figure merge operation.If union is no can very to cover correspondence figure layer in GDS storehouses On all figures, then show that design has potential danger, the physical routing in future is likely to contact the figure outside obstacle figure layer Shape and form short circuit fault.At this time, designer needs the version in the GDS storehouses used when extracting LEF storehouses according to inspection result inspection Whether this is correct, and whether parameter setting when extracting LEF storehouses is wrong.Fig. 4 gives the obstacle figure layer between LEF storehouses and GDS storehouses Comparison check result.It can be seen that the metal on one piece of M1 layer in GDS does not have corresponding metal or OBS in LEF, this Block metal is actually pin A1, does not have the definition of this pin in LEF storehouses.If user does cloth using this LEF storehouse Line, may result in the cabling and A1 short circuits for connecting other pins.
In sum, by specifying the figure layer corresponding relation in LEF storehouses and GDS storehouses, figure can be carried out in correspondence figure layer Obstacle figure layer comparison check, find in GDS storehouses those not by the geometric figure of LEF storehouses OBS obstacles figure layer covering, and provide Report and graphic software platform result.Convenient use person checks correctness, uniformity and the integrality of library unit design.
Brief description of the drawings
OBS obstacle figure layers in Fig. 1 standard block LEF storehouses
OBS obstacle figure layers in Fig. 2 IP module LEF storehouses
Each figure layer figure in Fig. 3 GDS storehouses
The OBS figure layers in Fig. 4 LEF storehouses and the comparison check of GDS storehouses figure
Specific implementation step:
With reference to the contrast inspection of LEF storehouses and GDS storehouses obstacle figure layer in a specific example description standard unit or the design of IP modules Checking method, operating process step is as follows:
1)Prepare the LEF storehouses of description standard unit or IP module physical information, and the GDS storehouses for describing layout information;
2)Eda tool is opened, work at present catalogue is set up, corresponding LEF storehouses and GDS storehouses is imported;
3)Provide the figure layer corresponding relation in LEF storehouses and GDS storehouses
4)Configuration coherence check parameter;
5)Operation LEF storehouses and the comparison check in GDS storehouses(cross-check), in the middle of corresponding figure layer, check the obstacle of figure Figure layer covering relation.
6)Generation text audit report, and open graphical window and carry out result and be highlighted.

Claims (3)

1. a kind of LEF storehouses and the method for GDS storehouses obstacle figure layer comparison check, are related to being mainly characterized by for EDA design tools:
1)The uniformity of figure layer between the automatic LEF storehouses and GDS storehouses checked in IC design standard block and IP modules, and Audit report is provided;
2)The pin shape in each figure layer is extracted in LEF library units(pin shape)With OBS obstacle figure layer shapes;
3)The geometry in each figure layer is extracted in GDS library units;
4)For each figure layer, whether the union of pin shape and OBS obstacle shapes defined in comparison check LEF storehouses can be covered All shapes in lid GDS storehouses;
5)If some shapes for finding GDS storehouses can not be capped, the mode being highlighted using figure, shape is reported with reference to word Formula is reported to user.
2. there is feature(2)、(3)、(4)Combination.
3. there is feature(1)、(4)、(5)Combination.
CN201510868355.7A 2015-12-02 2015-12-02 A kind of LEF storehouses and the method for GDS storehouses obstacle figure layer comparison check Pending CN106815384A (en)

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CN201510868355.7A CN106815384A (en) 2015-12-02 2015-12-02 A kind of LEF storehouses and the method for GDS storehouses obstacle figure layer comparison check

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109299503A (en) * 2018-08-14 2019-02-01 珠海市微半导体有限公司 A kind of generation method of the LEF file based on wiring obstruction
CN112347734A (en) * 2020-11-06 2021-02-09 海光信息技术股份有限公司 Electronic automation design method, device, medium and equipment for integrated circuit

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CN102955123A (en) * 2011-08-19 2013-03-06 上海华虹Nec电子有限公司 Examination method for different-party IP (internet protocol) containing client party chip antenna effect
CN102955865A (en) * 2011-08-19 2013-03-06 上海华虹Nec电子有限公司 Black box logic verification method for physical chip layout
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CN1897002A (en) * 2005-07-12 2007-01-17 台湾积体电路制造股份有限公司 Method for identifying a physical failure location and system for combining pure logic and physical layout information
CN102955123A (en) * 2011-08-19 2013-03-06 上海华虹Nec电子有限公司 Examination method for different-party IP (internet protocol) containing client party chip antenna effect
CN102955865A (en) * 2011-08-19 2013-03-06 上海华虹Nec电子有限公司 Black box logic verification method for physical chip layout
CN104750886A (en) * 2013-12-29 2015-07-01 北京华大九天软件有限公司 Method for confirming pin access area in integrated circuit layout wiring

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109299503A (en) * 2018-08-14 2019-02-01 珠海市微半导体有限公司 A kind of generation method of the LEF file based on wiring obstruction
CN109299503B (en) * 2018-08-14 2023-02-17 珠海一微半导体股份有限公司 LEF file generation method based on wiring blockage
CN112347734A (en) * 2020-11-06 2021-02-09 海光信息技术股份有限公司 Electronic automation design method, device, medium and equipment for integrated circuit

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