CN109543309A - A kind of interference investigation method based on domain key signal - Google Patents
A kind of interference investigation method based on domain key signal Download PDFInfo
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- CN109543309A CN109543309A CN201811410376.4A CN201811410376A CN109543309A CN 109543309 A CN109543309 A CN 109543309A CN 201811410376 A CN201811410376 A CN 201811410376A CN 109543309 A CN109543309 A CN 109543309A
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The present invention proposes a kind of interference investigation method based on domain key signal.The interference investigation method is that the RULE script for automaticly inspecting the protection of domain signal based on DRC verifying language can be obtained the inspection result of signal protection, can quickly locate the place in domain there are signal interference by executing DRC design rule check.Entire interference signal troubleshooting procedure is automatized script operation, so that easy to operate, quick, efficient, visual result, and the time expended needed for artificial investigation is greatly saved with energy, and this method can be by simply modifying predefined form, it is quickly applied in the interference signal investigation of different process domain, it is versatile.
Description
Technical field
The present invention relates to integrated circuit diagram the Automation Design field more particularly to a kind of doing based on domain key signal
Disturb investigation method.
Background technique
IC Layout is the key link for connecting circuit design and technique manufacture.Although chip is in circuit design
Stage completes all simulation works, and ensures the function and performance of circuit under adverse circumstances within the acceptable range, but
Often over falling into a long wait, but there is a series of problems in the chip produced back, lead to the deviation of chip appearance functionally, core
The performance of piece falls flat.Most of reason is all as caused by signal interference among these.Signal interference not only can
The deviation in chip functions and performance is caused, but also will cause situations such as chip debugging is difficult, chip testing is hampered.Although
Preset signal interference point is had found during follow-up test, it is also desirable to confirmation is verified by experimental methods such as FIB, then again
Correcting production, this has not only aggravated the research and development cost of chip, also extends the time that chip enters the market, therefore chip may miss city
Field good opportunity.
In order to guarantee the reliability of chip operation, after domain completes basic physical verification and functional verification, it is also necessary to right
Sensitive signal, high resistant signal, small signal and high-frequency signal in domain carry out protection investigation, prevent signal interference, thus
Improve the reliability of circuit performance.There are three types of common signal interference investigation methods, one is widen between same layer signal away from
From another kind is the shielding line for adding same physical level between same layer signal, and there are also one is use different metal layers
Carry out adjacent layer cabling.Traditional interference investigation method and step for signal interference problem is as follows:
1) the key signal table for obtaining circuit to be processed, then targetedly to each of these on circuit diagram
Key signal scans for, so that it is determined that the module to be processed where the key signal, increases the fussy degree of search routine.
2) in domain interface, the key signal line in the module to be processed is found, and check the tool of key signal line
Body trend then needs to confirm the key signal line and other same layer signal wires with the presence or absence of parallel.If parallel same layer signal
Line and the key signal line belong to a kind of signal, alternatively, parallel same layer signal is shielded signal line, then there is no signals
The case where interference；If parallel same layer signal wire and the key signal are not belonging to same class signal, there are signal interferences
Danger, the distance for needing to keep between setting signal line by calculating is to prevent stop signal interference.Due in same domain
In, same signal wire is erected by different metal layer Lai, it is meant that the number of the same layer signal wire parallel with signal wire
It is in the majority with type sum, the phenomenon that it is complicated, cumbersome to be easy to cause mode of checking, and generates under-enumeration.
As it can be seen that traditional interference investigation method flow for signal interference problem is sufficiently complex, cumbersome, and result can not
It leans on, this will seriously affect the time of chip delivery.
Summary of the invention
In order to allow in domain the investigation that there is the signal wire of interference simpler comprehensively accurate, the present invention proposes following skill
Art scheme:
A kind of interference investigation method based on domain key signal, includes the following steps: the pass in predefined domain circuit structure
Key signals line, shielded signal line, the safe spacing value for causing the key signal line interference and the relevant metal of corresponding technique
Hierarchical information；Capture the metal level link information of the shielded signal line and the metal hierarchical linkage letter of the key signal line
Breath, and the metal level link information of the same level of aforementioned uniformity signal line is merged into storage；It is deposited according to aforementioned merging
The metal hierarchical linkage of the metal level link information of the same level of the uniformity signal line of storage and shielded signal line letter
The spacing of the preset signals line and the key signal line is not met the report result of the safe spacing value as row by breath
The fruit that comes to an end output；Wherein, the preset signals line and the key signal line are the same layers of non-uniformity signal and unmasked signal
The signal lead of metal layer, the signal lead of the unmasked signal are the signal leads other than the shielded signal line；
The safe spacing value is that the signal interference between the preset signals line and the key signal line is decayed in engineering and can be neglected
The slightly distance value of degree.
Further, in the metal level link information of the capture shielded signal line and the key signal line
Before metal level link information, further includes: the signal wire for treating the domain of investigation is classified, and wherein class condition includes letter
Metal layer belonging to number type, signal characteristic and signal wire；Wherein, it is divided into the uniformity signal line and non-same according to signal type
Class signal wire is divided into shielded signal line and unmasked signal wire according to signal characteristic, is divided into according to metal layer belonging to signal wire
The signal wire of the metal layer of the signal wire of the same layer metal layer and non-same level.
Further, the script of abovementioned steps method is all language to be verified using DRC, and check come defeated by executing DRC
The investigation result of the key signal out.
Compared with prior art, the interference investigation method based on domain key signal provided through the invention, can be rapidly
Metal layer signal wires all on integrated circuit diagram to be checked are classified according to specified classifying rules in ground, pass through utilization
The artificial investigation of automatized script investigation and comprehensively replacement, can quickly navigate to the position of signal interference, and investigation result is accurate, can
It leans on, it is easy to operate, quick, intuitive.
In addition, the definition of IC technique related physical level and coherent signal definition in classifying rules need to be only modified, it can be quick
Applied to signal protection investigation is carried out in the domain of different IC techniques, the versatility of the technical program is stronger.
Detailed description of the invention
Fig. 1 is a kind of flow chart of the interference investigation method based on domain key signal provided in an embodiment of the present invention；
Fig. 2 is the metal connecting line area in domain to be detected provided in an embodiment of the present invention before executing the interference investigation method
The schematic diagram in domain；
Fig. 3 is the metal connecting line area in domain to be detected provided in an embodiment of the present invention after executing the interference investigation method
The schematic diagram in domain.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention is retouched in detail
It states.It should be appreciated that disclosed below, the specific embodiments are only for explaining the present invention, is not intended to limit the present invention.
The present invention proposes a kind of interference investigation method based on domain key signal, is the design based on DRC verifying language
The controlled execution of rule script, wherein the inspection result of signal protection can be obtained by executing DRC design rule check,
The place in domain there are signal interference can be quickly located, so that easy to operate, quick, efficient, visual result, thus greatly
The time expended needed for artificial investigation is saved greatly with energy, and the interference investigation method can be predefined by simply modifying
Form is quickly applied in the interference signal investigation of different process domain, versatile.The specific reality of the interference investigation method
The mode of applying can refer to flow chart 1.
Predefined information: key signal line specially defines the crucial letter according to specified circuit key signal table
The signal type of number line；Meanwhile predefined shielded signal line；The predefined safe spacing for causing the key signal line interference
Value；The relevant metal hierarchical information of predefined technique.
Capturing information: the metal level link information of the shielded signal line is captured, while capturing the key signal line
Metal level link information, and the metal layer information of the same level of uniformity signal is merged and is stored.Meanwhile it can also
Obtain the metal level link information of unmasked signal wire.It should be noted that in layout design, the key signal line
Uniformity signal will not generate interference to the key signal line, so the metal layer information of the same level of uniformity signal is carried out
Merge and stores.In addition, interference problem will not be generated between the metal layer signal wire of non-same level.
Before aforementioned capturing information, need first to classify to signal wire, wherein the assorting process of class condition is specific
Are as follows: it is divided into uniformity signal and non-uniformity signal according to the type of signal；It is divided into shielded signal line and unmasked according to signal characteristic
Signal wire；It is divided into the signal wire of same layer metal layer and the signal wire of non-same layer metal layer according to metal layer belonging to signal wire.It needs
To illustrate that above process elaboration is the process individually classified according to each class condition, when class condition is final election
When, for example, there are two class condition or it is multiple when, then without specific sequencing between two or more class conditions.
Export violation information: according to the same layer metal layer information of the aforementioned uniformity signal line for merging storage and the screen
The spacing of the preset signals line and the key signal line is not met the peace by the metal level link information for covering signal wire
The result report of full distance values is exported as investigation result output as the violation information of DRC, i.e., the described key signal line
The distance values of a line circle of the preset signals line of a line circle and its spacing recently are unsatisfactory for the safe spacing value,
Indicate that the key signal has disturbed risk.Wherein, the preset signals line and the key signal line are non-similar
The signal lead of the same layer metal layer of signal, while the preset signals line and the key signal line belong to same layer metal layer
The signal lead of unmasked signal, the signal lead of the unmasked signal are that the signal other than the shielded signal line is walked
Line.
The script of abovementioned steps method is all language to be verified using DRC, and check the realization crucial letter by executing DRC
Number troubleshooting procedure, then according to DRC inspection result, when necessary and feasible, by the signal of the same layer metal layer interfered
Cabling movement is so that spacing each other is adjusted to the safe spacing value.Wherein, the safe spacing value are as follows: if described
At the adjacent same layer metal layer routing region of key signal line, so that the key signal line and its belonging to non-uniformity signal
Signal interference between the signal lead of the same layer metal layer of unmasked signal decays in engineering the distance value for the degree that can be ignored.
It is to need to hold repeatedly in general, executing DRC design rule check and adjusting domain according to DRC inspection result
Capable process executes the result that DRC is checked come the continuous structure feature for adjusting domain, until completing institute by obtaining repeatedly
It states preset signals line investigation and there is no the signal wires interfered the key signal.
As a kind of embodiment of the invention, Fig. 2 is gold of the domain to be detected before executing the interference investigation method
Belong to tie region, in which: the label 101 in attached drawing 2 and attached drawing 3 represents the key signal line, by the first default metal layer structure
At；Label 103 and label 101 in attached drawing 2 and attached drawing 3 belong to the non-uniformity signal line, and label 103 is the unmasked
Signal wire is made of the second default metal layer；Label 102 in attached drawing 2 and attached drawing 3 represents the unmasked signal wire, and marks
Note 102 belongs to the non-uniformity signal line with label 101, is made of the described first default metal layer.
In the present embodiment, signal wire 101 and signal wire 102 belong to the signal lead of same layer metal layer, i.e., and described first
Default metal layer and the third preset the metal layer that metal layer belongs to same level, signal wire 101 and signal wire 102 in Fig. 2
Spacing be less than the safe spacing value, thus there are the danger of signal interference with signal wire 102 for signal wire 101.In this implementation
Under example, the safe spacing value may be configured as the signal lead line width of the same layer metal layer more than or equal to three times.Meanwhile and by
Belong to the signal lead of non-same layer metal layer in signal wire 101 and signal wire 103, therefore signal wire 101 is not present with signal wire 103
The danger of signal interference.Using the interference investigation method, the position on domain there are signal interference can be quickly oriented, such as
Shown in Fig. 3, the thick line box 104 between the metal layer boundary of signal wire 101 and the metal layer boundary of signal wire 102 can highlight aobvious
Show, the width of layout design person's thick line box 104 is prompted to be unsatisfactory for the safe spacing value, indicates the region of thick line box 104
Interior to there is the factor for causing key signal line 101 that signal interference occurs, i.e. signal wire 102 can the letter of the key described in signal wire 101(
Number line) generate interference.Then the violation information checked according to DRC will in the case where meeting the necessary situation of design rule
The signal wire 102 of the same layer metal layer interfered with signal wire 101 is mobile, so that spacing each other meets the safety
Distance values, i.e. the signal lead line width greater than the same layer metal layer of three times, meet the safe spacing value, to guarantee chip in work
The key signal is not influenced by signal interference during work.
The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；Although referring to aforementioned each reality
Applying example, invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each
Technical solution documented by embodiment is modified, or equivalent substitution of some or all of the technical features；And
These are modified or replaceed, the range for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (3)
1. method is checked in a kind of interference based on domain key signal, which comprises the steps of:
Key signal line, shielded signal line in predefined domain circuit structure, the safety for causing the key signal line interference
Distance values and the relevant metal hierarchical information of corresponding technique；
The metal level link information of the shielded signal line and the metal level link information of the key signal line are captured, and
The metal level link information of the same level of aforementioned uniformity signal line is merged into storage；
According to the metal level link information of the same level of the aforementioned uniformity signal line for merging storage and the shielded signal
The spacing of the preset signals line and the key signal line is not met the safe spacing by the metal level link information of line
The report result of value is as investigation result output；
Wherein, the preset signals line and the key signal line are the same layer metal layers of non-uniformity signal and unmasked signal
Signal lead, the signal lead of the unmasked signal are the signal leads other than the shielded signal line；The safety
Distance values are that the signal interference between the preset signals line and the key signal line decays to negligible degree in engineering
Distance value.
2. interfering investigation method according to claim 1, which is characterized in that in the metal of the capture shielded signal line
Before hierarchical linkage information and the metal level link information of the key signal line, further includes: treat the letter of the domain of investigation
Number line is classified, and wherein class condition includes signal type, metal layer belonging to signal characteristic and signal wire；Wherein, according to
Signal type is divided into the uniformity signal line and non-uniformity signal line, is divided into shielded signal line according to signal characteristic and unmasked is believed
Number line, the letter of the signal wire of the same layer metal layer and the metal layer of non-same level is divided into according to metal layer belonging to signal wire
Number line.
3. according to claim 1 to any one of 2 interference investigation methods, which is characterized in that the script of abovementioned steps method is all
It is language to be verified using DRC, and the troubleshooting procedure of the realization key signal is checked by executing DRC.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811410376.4A CN109543309B (en) | 2018-11-23 | 2018-11-23 | Interference checking method based on layout key signals |
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| CN201811410376.4A CN109543309B (en) | 2018-11-23 | 2018-11-23 | Interference checking method based on layout key signals |
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| CN109543309B CN109543309B (en) | 2023-01-06 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110750950A (en) * | 2019-10-14 | 2020-02-04 | 中国兵器工业集团第二一四研究所苏州研发中心 | Method for automatically shielding layout key signal line |
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| US20060095872A1 (en) * | 2002-07-29 | 2006-05-04 | Mcelvain Kenneth S | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices |
| CN101782931A (en) * | 2009-01-20 | 2010-07-21 | 英业达股份有限公司 | Processing method and system of constraint areas of circuit board wiring |
| CN102855337A (en) * | 2011-06-27 | 2013-01-02 | 鸿富锦精密工业（深圳）有限公司 | Automated wiring inspection system and automated wiring inspection method |
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|---|---|---|---|---|
| WO2001088956A2 (en) * | 2000-05-15 | 2001-11-22 | Atheros Communications, Inc. | Rf integrated circuit layout |
| US20040145033A1 (en) * | 2002-07-29 | 2004-07-29 | Mcelvain Kenneth S. | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices |
| US20060095872A1 (en) * | 2002-07-29 | 2006-05-04 | Mcelvain Kenneth S | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices |
| CN101782931A (en) * | 2009-01-20 | 2010-07-21 | 英业达股份有限公司 | Processing method and system of constraint areas of circuit board wiring |
| CN102855337A (en) * | 2011-06-27 | 2013-01-02 | 鸿富锦精密工业（深圳）有限公司 | Automated wiring inspection system and automated wiring inspection method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110750950A (en) * | 2019-10-14 | 2020-02-04 | 中国兵器工业集团第二一四研究所苏州研发中心 | Method for automatically shielding layout key signal line |
| CN110750950B (en) * | 2019-10-14 | 2023-04-18 | 中国兵器工业集团第二一四研究所苏州研发中心 | Method for automatically shielding layout key signal line |
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Address after: 519000 2706, No. 3000, Huandao East Road, Hengqin new area, Zhuhai, Guangdong Applicant after: Zhuhai Yiwei Semiconductor Co.,Ltd. Address before: Room 105-514, No.6 Baohua Road, Hengqin New District, Zhuhai City, Guangdong Province Applicant before: AMICRO SEMICONDUCTOR Co.,Ltd. |
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