CN104103545A - Wafer defect detection method - Google Patents
Wafer defect detection method Download PDFInfo
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- CN104103545A CN104103545A CN201410377444.7A CN201410377444A CN104103545A CN 104103545 A CN104103545 A CN 104103545A CN 201410377444 A CN201410377444 A CN 201410377444A CN 104103545 A CN104103545 A CN 104103545A
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- wafer
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- wafer defect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a wafer defect detection method. A mask defect detection result is transferred into wafer defect detection equipment, and the detection sensitivity around corresponding positions of defects on a mask is increased to detect defects on a practical wafer. The influences of defects found in mask detection on a practical circuit can be verified during production, thereby realizing linkage of wafer defect detection in production for mask defect detection, increasing the sensitivity specific to defects which are difficult to capture in wafer defect detection, and further increasing the recall ratio of wafer defect detection.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of detection method of semiconductor crystal wafer defect.
Background technology
Advanced integrated circuit fabrication process generally all comprises the operation of hundreds of step, the small mistake of any link all will cause the inefficacy of whole chip, constantly dwindling along with circuit critical size particularly, it is just stricter to the requirement of technology controlling and process, so all need to dispose high sensitivity optical defect checkout equipment for finding in time and deal with problems in actual production process, product is detected online.
Wherein, the transfer of circuitous pattern is by by the figure designing on circuit mask, the method by photoetching projects on wafer, and a defect on circuit mask all can be transferred on a lot of chips on wafer as shown in Figure 1.So in the process of producing, have special-purpose circuit mask checkout equipment it is carried out to the detection of defect, a defects detection result as Fig. 2 just represents a circuit mask, has a lot of defects above it.
Certainly, only have when defect is positioned on the circuit of design and just can impact the figure projecting on wafer.For the defects detection of wafer no matter be the defects detection of optics and electronics, the basic principle of its work is all by equipment, to obtain the signal of several chips, and then carry out the comparison of data, as Fig. 3 is expressed as 3 adjacent chips, by the graph data of 3 chips is gathered simultaneously, then the position that relatively draws signal difference by B chip and A chip as shown in Figure 4, the position that relatively draws signal difference by B chip and C chip as shown in Figure 5 again, in these two comparing results, the same position of difference signal is exactly the position of the defect that detects on B chip so.
Yet owing to there is more background noise, in circle as shown in Figure 6, the defect of figure is not easy to be detected on actual wafer, very high could discovery is transferred in the program sensitivity that conventionally wafer defect need to be detected; Meanwhile, if having a lot of noises on wafer as shown in Figure 7, can cause the difficulty of judgement greatly to increase, cannot identify even at all.
Therefore, how providing a kind of detection method of wafer defect, improve the sensitivity of capture graph defect, more full defect to be detected, is one of those skilled in the art's technical problem urgently to be resolved hurrily.
Summary of the invention
In order to realize goal of the invention of the present invention, the invention provides a kind of wafer defect detection method, with solve prior art cannot complete detection to the problem of defect on wafer.
Wafer defect detection method provided by the invention comprises the following steps:
Step S01, provides a wafer and this wafer photolithography mask used;
Step S02, carries out defects detection to this mask, obtains the first testing result that contains defective locations information;
Step S03, is input to this first testing result in wafer defect checkout equipment;
Step S04, in wafer defect checkout equipment, improve on this wafer with the detection sensitivity of the opposite position of this mask defective locations information, this wafer is carried out to defects detection.
Further, this first testing result comprises mask defect coordinate axle figure and the coordinate of defect on this reference axis figure.
Further, step S03 comprises the position on this reference axis figure according to mask defect, obtain mask defect with respect to the more specific location information of a fixing point on mask graph, the fixing point of setting chip figure same position in wafer defect checkout equipment, and the more specific location information of this mask defect is transferred on graphics chip.
Further, the lower-left end points that this fixing point is mask graph.
Further, step S03 comprises this first testing result automatic synchronization in the wafer defect trace routine of wafer defect checkout equipment, and is read by this wafer defect trace routine.
Further, in step S04, be to improve this defective locations detection sensitivity of 1-100 μ m around.
Further, in step S04, be the detection sensitivity that improves 40-60%.
Wafer defect detection method of the present invention, by mask defects detection result is transferred in wafer defect checkout equipment, and improve the detection sensitivity around of defect correspondence position on mask, to detect the defect on actual wafer, can be to the defect of finding in mask detects, verify aborning its impact on side circuit, thereby realize the interlock that wafer defect detects aborning of mask defects detection, the defect that is difficult to catch during wafer defect is detected improves sensitivity, and then improves the recall ratio that wafer defect detects.
Accompanying drawing explanation
For can clearer understanding objects, features and advantages of the present invention, below with reference to accompanying drawing, preferred embodiment of the present invention is described in detail, wherein:
Fig. 1 is that a defect on available circuit mask is transferred to the schematic diagram on a plurality of chips on wafer;
Fig. 2 is a defects detection result schematic diagram of available circuit mask;
Fig. 3 is the schematic diagram of adjacent three chips in existing wafer defect detection method;
Fig. 4 is the data comparison diagram of B chip and A chip in Fig. 3;
Fig. 5 is the data comparison diagram of B chip and C chip in Fig. 3;
Fig. 6 is the schematic diagram that available circuit graphic defects is normal and defect is abnormal;
Fig. 7 is the simultaneous defect distribution schematic diagram of available circuit figure repeated defects and noise;
Fig. 8 is the schematic flow sheet of wafer defect detection method of the present invention;
Fig. 9 is the coordinate schematic diagram of mask defect in the inventive method one embodiment;
Figure 10 is the coordinate schematic diagram of wafer defect in the inventive method one embodiment.
Embodiment
Refer to Fig. 8, the wafer defect detection method of the present embodiment comprises the following steps:
Step S01, one wafer and this wafer photolithography mask used are provided, because mask exists one or more defects, cause the wafer after its photoetching also to certainly exist the one or more defects that shifted by mask, wherein, " defect " of the present invention generally comprises two classes: on mask, should carve sky and not carve empty part; On mask, should not carve sky and carve empty part, the former is main, common deficiency;
Step S02, carries out defects detection to this mask, obtains the first testing result that contains defective locations information;
Step S03, is input to this first testing result in wafer defect checkout equipment;
Step S04, in wafer defect checkout equipment, improve on this wafer with the detection sensitivity of the opposite position of this mask defective locations information, this wafer is carried out to defects detection.
By wafer defect detection method of the present invention, mask defects detection result is transferred in wafer defect checkout equipment, and improve the detection sensitivity around of defect correspondence position on mask, to detect the defect on actual wafer, can be to the defect of finding in mask detects, verify aborning its impact on side circuit, thereby realize the interlock that wafer defect detects aborning of mask defects detection, the defect that is difficult to catch during wafer defect is detected improves sensitivity, and then improves the recall ratio that wafer defect detects.
In the present embodiment, for the ease of wafer defect checkout equipment, read defect relevant information, the first testing result comprises mask defect coordinate axle figure and the coordinate of defect on this reference axis figure.Because the figure that mask defect detection equipment generates may be based on the different origins of coordinates from the figure of wafer defect checkout equipment analysis, preferably, step S03 comprises the reference axis figure of this mask is corresponded on chip wafer, so that mask graph is corresponding with graphics chip.More, step S03 comprises the position on this reference axis figure according to mask defect, obtain mask defect with respect to the more specific location information of a fixing point on mask graph, the fixing point of setting chip figure same position in wafer defect checkout equipment, and the more specific location information of this mask defect is transferred on graphics chip.
As shown in Figure 9 and Figure 10, Fig. 9 is the figure that mask defect detection equipment generates, and its origin of coordinates is positioned at the lower left of mask graph, and Figure 10 is the figure that wafer defect checkout equipment can read, analyzes, and its origin of coordinates is the lower-left end points of graphics chip.Pass through above-mentioned steps, first the coordinate of a plurality of mask defects in mask defective patterns is done respectively to finishing adjustment, using the x of this origin of coordinates and mask graph lower-left end points (described " fixing point ") to, y to difference as radix, obtain the concrete coordinate of each defect based on mask graph lower-left end points, as the first testing result, and transfer on graphics chip, just can obtain defective locations information corresponding with mask defective locations on graphics chip.
In practical application, step S03 comprises this first testing result automatic synchronization in the wafer defect trace routine of wafer defect checkout equipment, and read by this wafer defect trace routine, to improve the automation efficiency of detection.
In the present embodiment, improve the detection sensitivity of wafer defect checkout equipment 1-10000 μ m around these defective locations, preferably, the distance range that improves detection sensitivity can, between 1-100 μ m, with further accurate detection range, improve detection efficiency.In the present embodiment, raising detection sensitivity is 0-100%, and preferably, the scope that improves sensitivity degree can both guarantee the recall ratio of detection between 40-60%, can improve again the efficiency of detection.
The present embodiment mask defect detection equipment used includes but are not limited to Lasertec; Wafer defect checkout equipment includes but are not limited to KLA2835.
Claims (7)
1. a wafer defect detection method, is characterized in that, it comprises the following steps:
Step S01, provides a wafer and this wafer photolithography mask used;
Step S02, carries out defects detection to this mask, obtains the first testing result that contains defective locations information;
Step S03, is input to this first testing result in wafer defect checkout equipment;
Step S04, in wafer defect checkout equipment, improve on this wafer with the detection sensitivity of the opposite position of this mask defective locations information, this wafer is carried out to defects detection.
2. wafer defect detection method according to claim 1, is characterized in that: this first testing result comprises mask defect coordinate axle figure and the coordinate of defect on this reference axis figure.
3. wafer defect detection method according to claim 2, it is characterized in that: step S03 comprises the position on this reference axis figure according to mask defect, obtain mask defect with respect to the more specific location information of a fixing point on mask graph, the fixing point of setting chip figure same position in wafer defect checkout equipment, and the more specific location information of this mask defect is transferred on graphics chip.
4. wafer defect detection method according to claim 3, is characterized in that: the lower-left end points that this fixing point is mask graph.
5. according to the wafer defect detection method described in claim 1 to 4 any one, it is characterized in that: step S03 comprises this first testing result automatic synchronization in the wafer defect trace routine of wafer defect checkout equipment, and read by this wafer defect trace routine.
6. according to the wafer defect detection method described in claim 1 to 4 any one, it is characterized in that: in step S04, be to improve the opposite position detection sensitivity of 1-100 μ m around.
7. according to the wafer defect detection method described in claim 1 to 4 any one, it is characterized in that: in step S04, be the detection sensitivity that improves 40-60%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410377444.7A CN104103545A (en) | 2014-08-01 | 2014-08-01 | Wafer defect detection method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410377444.7A CN104103545A (en) | 2014-08-01 | 2014-08-01 | Wafer defect detection method |
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| CN104103545A true CN104103545A (en) | 2014-10-15 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108461371A (en) * | 2018-05-08 | 2018-08-28 | 德淮半导体有限公司 | Electron beam scanning device, defect detecting system and method |
| CN110945636A (en) * | 2017-07-25 | 2020-03-31 | 科磊股份有限公司 | Hybrid inspection system for efficient process window exploration |
| CN111722092A (en) * | 2020-06-22 | 2020-09-29 | 上海华力微电子有限公司 | Wafer defect detection method and system |
| CN112053967A (en) * | 2020-08-21 | 2020-12-08 | 华虹半导体(无锡)有限公司 | Method for evaluating influence degree of mask defect on device manufacturing |
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| US20040121496A1 (en) * | 2002-12-19 | 2004-06-24 | Keith Brankner | Method and apparatus for translating detected wafer defect coordinates to reticle coordinates using CAD data |
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| CN1892419A (en) * | 2005-07-06 | 2007-01-10 | 株式会社东芝 | Mask pattern inspection method, exposure condition verification method, and manufacturing method of semiconductor device |
| CN105489517A (en) * | 2014-09-15 | 2016-04-13 | 上海和辉光电有限公司 | Method for detecting defects of mask |
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2014
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Patent Citations (7)
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| JP3431567B2 (en) * | 2000-03-30 | 2003-07-28 | 株式会社東芝 | Defect inspection device and inspection method |
| CN1489195A (en) * | 2002-09-05 | 2004-04-14 | 株式会社东芝 | Mask defect inspection method and use thereof |
| US20040121496A1 (en) * | 2002-12-19 | 2004-06-24 | Keith Brankner | Method and apparatus for translating detected wafer defect coordinates to reticle coordinates using CAD data |
| CN1846170A (en) * | 2003-07-03 | 2006-10-11 | 恪纳腾技术公司 | Methods and systems for inspection of wafers and reticles using designer intent data |
| CN1879005A (en) * | 2003-11-20 | 2006-12-13 | Hoya株式会社 | Method of inspecting unevenness defect of pattern and device therefor |
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| CN105489517A (en) * | 2014-09-15 | 2016-04-13 | 上海和辉光电有限公司 | Method for detecting defects of mask |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110945636A (en) * | 2017-07-25 | 2020-03-31 | 科磊股份有限公司 | Hybrid inspection system for efficient process window exploration |
| CN110945636B (en) * | 2017-07-25 | 2021-05-25 | 科磊股份有限公司 | Hybrid inspection system for efficient process window exploration |
| CN108461371A (en) * | 2018-05-08 | 2018-08-28 | 德淮半导体有限公司 | Electron beam scanning device, defect detecting system and method |
| CN111722092A (en) * | 2020-06-22 | 2020-09-29 | 上海华力微电子有限公司 | Wafer defect detection method and system |
| CN111722092B (en) * | 2020-06-22 | 2023-02-10 | 上海华力微电子有限公司 | Wafer defect detection method and system |
| CN112053967A (en) * | 2020-08-21 | 2020-12-08 | 华虹半导体(无锡)有限公司 | Method for evaluating influence degree of mask defect on device manufacturing |
| CN112053967B (en) * | 2020-08-21 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Method for evaluating influence degree of mask defect on device manufacturing |
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Application publication date: 20141015 |