CN110750214A - Method for giving consideration to sequential reading and random reading performances of eMMC (enhanced multimedia card) memory - Google Patents
Method for giving consideration to sequential reading and random reading performances of eMMC (enhanced multimedia card) memory Download PDFInfo
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Abstract
The invention discloses a method for giving consideration to both sequential reading and random reading performances of an eMMC memory so as to improve the reading efficiency of the eMMC memory, which comprises the following steps of: a1, acquiring the data length of the data to be read; and B1, selecting one of at least two predefined reading operations according to the acquired data length and applying the selected one to read the data. By adopting the method provided by the invention, both the random reading performance and the sequential reading performance of the eMMC memory can be considered.
Description
Technical Field
The invention relates to the field of data reading and writing, in particular to a method for giving consideration to sequential reading and random reading performances of an eMMC memory.
Background
The eMMC memory is used as a storage device with excellent performance, and is widely applied to occasions such as a tablet personal computer, a television box, a mobile phone and the like. But as systems such as android become more complex, users put higher demands on the performance of products. The read performance requirements of the eMMC memory by product designers are also increased. If the eMMC memory does not handle random read performance, this would occur, for example: the product plays games, plays video blocks, has slow response to application program loading, and even has a false halt.
The following solutions are common at present: 1. the front-end command processing starts, an FTL (flash translation layer) algorithm is optimized, and different mapping methods are adopted; 2. optimizing command data paths, reducing latency, etc. on a targeted basis; 3. the performance of the eMMC memory can be improved by improving the interface frequency of the NAND Flash (NAND Flash), and using multiPlane (concurrent reading) of the NAND Flash or different reading operation methods of the NAND, such as cache read (cache read) or normal read (normal read); 4. the eMMC layer and the NAND layer realize a concurrency mechanism and improve the overall efficiency.
The existing common NAND Flash can support multiPlane operation, basically adopts multiPlane of the NAND Flash, and improves the read bandwidth of the NAND Flash or a system to 2 times of single-line read operation. However, not all scenarios are suitable for multiPlane operation, and the eMMC memory also has many scenarios for storing small files, such as the EXT4 file system format used by Linux and above systems, the default file of the system is 4KB minimum, and for some scenarios for reading 4KB, for example, when the IO size is smaller than the page size of the flash memory (for example, the size of one page is 16KB), the requirement can be satisfied by using single read. Because in the multiPlane read operation, the multiPlane read operation is slightly longer than the ordinary single page read operation, the multiPlane read operation sequentially sends page selection commands, and the gap time is reserved between each page selection, thereby reducing the read performance of the eMMC. But if a single plane is used for all, multiPlane is more advantageous in other scenarios such as continuous reading, e.g., continuous reading of 512KB of data on the linux side.
Disclosure of Invention
In order to solve the technical problems, the invention provides a method for giving consideration to both sequential reading and random reading performances of an eMMC memory.
Firstly, the invention provides a method for giving consideration to both sequential reading and random reading performances of an eMMC memory so as to improve the reading efficiency of the eMMC memory, and the method comprises the following steps of:
a1, acquiring the data length of the data to be read;
and B1, selecting one of at least two predefined reading operations according to the acquired data length and applying the selected one to read the data.
Secondly, the invention provides a method for giving consideration to both sequential reading and random reading performances of an eMMC memory so as to improve the reading efficiency of the eMMC memory, and the method comprises the following steps:
a2, acquiring the data length of the data to be read;
b2, if the length of the acquired data is less than the first length, selecting and applying a first reading operation; if the length of the acquired data is larger than the first length and smaller than the second length, selecting and applying a second reading operation; otherwise, a third read operation is applied to read the data.
Further, in the method provided by the present invention, before obtaining the data length of the data to be read, the method further includes the following steps:
requesting the Host end for the length of data to be read; and sends the data length acquired in response to the request to the flash translation layer FTL.
Further, in the method provided by the present invention, when the data length cannot be obtained, a third read operation is applied to read the data.
Further, in the above method provided by the present invention, the first length is 16 KB; the second length is 64 KB.
Further, in the above method proposed by the present invention, the second read operation is a concurrent read operation; and the third read operation is a read-ahead and concurrent read operation.
Further, in the above method provided by the present invention, the reading time of the second reading operation is 1.5 times the reading time of the first reading operation.
The invention provides a device giving consideration to both sequential reading and random reading performances of an eMMC memory so as to improve the reading efficiency of the eMMC memory, and the device comprises the following modules:
the first acquisition module is used for acquiring the data length of the data to be read;
and the first reading module is used for selecting one of at least two predefined reading operations according to the acquired data length and applying the selected one to read the data.
The invention provides a device giving consideration to both sequential reading and random reading performances of an eMMC memory so as to improve the reading efficiency of the eMMC memory, and the device comprises the following modules:
the second acquisition module is used for acquiring the data length of the data to be read;
the second reading module is used for selecting and applying the first reading operation if the length of the acquired data is smaller than the first length; if the length of the acquired data is larger than the first length and smaller than the second length, selecting and applying a second reading operation; otherwise, apply
And a third read operation to read the data.
Finally, the invention proposes a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above-mentioned method.
The beneficial results of the invention are: by: 1. acquiring read length information through an eMMC protocol layer; 2. transmitting the length information to the FTL; 3. the FTL selects the optimal NAND operation method according to the length information, so that both the random reading performance and the sequential reading performance of the eMMC memory can be considered.
Drawings
The invention is further illustrated with reference to the following figures and examples. In the accompanying drawings, like reference numerals refer to like parts throughout.
Fig. 1 is a block diagram illustrating an eMMC memory;
fig. 2 is a schematic diagram illustrating a comparison between a concurrent read mode and a single line read mode of an eMMC memory;
fig. 3 is a flow diagram illustrating a first embodiment of a method for providing both sequential read and random read performance for an eMMC memory in accordance with the present invention;
fig. 4 is a flow diagram illustrating a second embodiment of a method for providing both sequential read and random read performance for an eMMC memory in accordance with the present invention;
fig. 5 is a flow diagram illustrating a third embodiment of a method for providing both sequential read and random read performance for an eMMC memory in accordance with the present invention;
fig. 6 is a block diagram of an apparatus for performing both sequential read and random read of an eMMC memory in accordance with the present invention;
fig. 7 is another block diagram of an apparatus for performing both sequential and random read of an eMMC memory according to the present invention.
Detailed Description
The conception, the specific structure and the technical effects of the present invention will be clearly and completely described below in conjunction with the embodiment and the accompanying drawings to fully understand the objects, the schemes and the effects of the present invention. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The same reference numbers will be used throughout the drawings to refer to the same or like parts.
It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature or indirectly fixed or connected to the other feature. Furthermore, the descriptions of upper, lower, left, right, etc. used in this application are only relative to the positional relationship of the various elements of the application with respect to one another in the drawings. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The exemplary embodiments described herein and depicted in the drawings should not be considered limiting. Various mechanical, compositional, structural, electrical, and operational changes, including equivalents, may be made without departing from the scope of this disclosure and the claims. In some instances, well-known structures and techniques have not been shown or described in detail to avoid obscuring the disclosure. The same reference numbers in two or more drawings identify the same or similar elements. Moreover, elements and their associated features, which are described in detail with reference to one embodiment, may be included in other embodiments, where they are not specifically shown or described, where practicable. For example, if an element is described in detail with reference to one embodiment and not described with reference to the second embodiment, it may also be claimed to be included in the second embodiment.
Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any combination of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element of the same type from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "at … …" depending on the context.
In an embodiment of the invention, the method steps may be performed in another order. The invention is not limited to the order in which the method steps are performed.
emmc (embedded multimedia card) is an abbreviation of embedded multimedia card, and the embedded memory standard specification established by MMC Association (multimedia card Association) is mainly directed to mobile device products, such as mobile phones, smart phones, tablet computers, notebook computers, and the like; the products all need a light and thin machine body, so that the requirement of reducing the area of used components is met, the eMMC memory simplifies the design of a memory, and a multi-chip packaging technology is used for packaging a NAND Flash chip and a control chip together to form a single chip, so that the components can be saved, and the area of a circuit board can be increased. The structure of the eMMC in the prior art is shown in fig. 1
Referring to fig. 2, a schematic diagram of a comparison between a concurrent read mode and a single line read mode of an eMMC memory is shown; at present, the commonly used NAND Flash can support multiPlane (concurrent read) operation, basically, the multiPlane of the NAND Flash is used, and the read bandwidth of the NAND Flash or a system is improved to 2 times of that of singlePlane (single-wire) read operation. However, not all scenarios are suitable for multiPlane operation, and the eMMC memory also has many scenarios for storing small files, such as the EXT4 file system format used by Linux and above systems, the default file of the system is 4KB minimum, and for some scenarios for reading 4KB, for example, when the IO size is smaller than the page size of the flash memory (for example, the size of one page is 16KB), the requirement can be satisfied by using single read. Because in the multiPlane read operation, the multiPlane read operation is slightly longer than the ordinary single page read operation, the multiPlane read operation sequentially sends page selection commands, and the gap time is reserved between each page selection, thereby reducing the read performance of the eMMC. The time with singleRead is T1 and the time with multiPlane is 1.5 times that of T1, so forcing multiPlane to be used instead reduces the random read performance of eMMC. But if a single plane is used for all, multiPlane is more advantageous in other scenarios such as continuous reading, e.g., continuous reading of 512KB of data on the linux side.
Referring to fig. 3, which is a flowchart illustrating a first embodiment of a method for considering both sequential read and random read performance of an eMMC memory according to the present invention, the method for considering both sequential read and random read performance of the eMMC memory according to an embodiment of the present invention is shown to improve the reading efficiency of the eMMC memory, and includes the following steps: a1, acquiring the data length of the data to be read; and B1, selecting one of at least two predefined reading operations according to the acquired data length and applying the selected one to read the data. In an embodiment of the present invention, the at least two predefined read operations may be the concurrent read operation and the single-line read operation, but it should be understood that the at least two predefined read operations may also be other read operation manners, as long as the two predefined read operation manners are different and the technical effect of considering both the random read performance and the continuous read performance can be achieved, and the present invention also falls into the protection scope of the present invention.
Further, referring to fig. 4, a flow diagram of a second embodiment of a method for accounting for eMMC memory sequential read and random read performance in accordance with the present invention is shown; the figure shows a method for improving the reading efficiency of an eMMC memory by considering both the sequential reading performance and the random reading performance of the eMMC memory according to an embodiment of the invention, and the method comprises the following steps: a2, acquiring the data length of the data to be read; b2, if the length of the acquired data is less than the first length, selecting and applying a first reading operation; if the length of the acquired data is larger than the first length and smaller than the second length, selecting and applying a second reading operation; otherwise, a third read operation is applied to read the data. In an embodiment of the present invention, the first read operation and the second read operation may be the concurrent read operation and the single-line read operation, respectively, but it should be understood that the at least two predefined read operations may also be other read operation manners, as long as the two predefined read operation manners are different and the technical effect of considering both the random read performance and the continuous read performance can be achieved, and the present invention also falls into the protection scope of the present invention.
In one embodiment of the present invention, the first read operation, the second read operation, and the third read operation described above are applied according to the data length division shown in the following table. It should be understood that the first, second and third expressions are not meant to express an order, but merely to distinguish different read operations.
| Data length | Read operation |
| 4KB、8KB、16K | First read operation |
| Greater than 16KB and less than 64KB | Second read operation |
| Greater than 64KB | Third read operation |
Further, in an embodiment of the present invention, before acquiring the data length of the data to be read, the method further includes the following steps: requesting the Host end for the length of data to be read; and sends the data length acquired in response to the request to the flash translation layer FTL. Specifically, returning to fig. 1, in order to implement the method proposed by the present invention, an interface needs to be added in the eMMC protocol layer, the read length of the Host is determined, information such as the length is returned to the FTL layer, and then the FTL layer selects the operation mode with the highest efficiency.
In an embodiment of the present invention, the method for determining the Host reading length may be obtained by a standard protocol of the eMMC. As shown in the following table:
| command | Length of | Nand command |
| Cmd17 | 512 bytes | SingleRead |
| Cmd23+cmd18 | Parameter of 512 bytes cmd23 | SingleRead/MultiPlaneRead |
| Cmd18 | Without length, normally for sequential reading | MultiPlanecachehead (concurrent cache type) |
Initiating a read request to an FTL layer according to the length of read data corresponding to the read command and the logic page; the FTL layer distinguishes according to the length of the received read request and selects which NAND read operation is used; and the NAND physical layer reads the NAND Flash data according to the read command in the FTL request. The time of random reading of the eMMC at small IO (input/output) is saved, and the reading performance of the eMMC is improved. For sequential reading of large IO, the FTL layer adopts a pre-reading mode, and sequential reading performance of the eMMC is improved.
Further, referring to the flowchart of fig. 5 of a third embodiment of a method for considering both sequential read and random read performance of an eMMC memory according to the present invention, in an embodiment of the present invention, when the data length cannot be obtained, a third read operation is applied to read data.
Further, in one embodiment of the present invention, the first length is 16 KB; the second length is 64 KB.
Specifically, in one embodiment of the present invention, the first read operation is a single-wire read operation, and the second read operation is a concurrent read operation; and the third read operation is a read-ahead and concurrent read operation.
Specifically, in one embodiment of the present invention, the read time of the second read operation is 1.5 times the read time of the first read operation. It should be understood that the reading time of the second reading operation is not necessarily 1.5 times the reading time of the first reading operation, and may be other times, integers, or decimal numbers.
Further, referring to a block diagram of an apparatus for performing both sequential read and random read of an eMMC memory according to the present invention as shown in fig. 6, in an embodiment of the present invention, the proposed apparatus includes the following modules: the first acquisition module is used for acquiring the data length of the data to be read; and the first reading module is used for selecting one of at least two predefined reading operations according to the acquired data length and applying the selected one to read the data. In an embodiment of the present invention, the at least two predefined read operations may be the concurrent read operation and the single-line read operation, but it should be understood that the at least two predefined read operations may also be other read operation manners, as long as the two predefined read operation manners are different and the technical effect of considering both the random read performance and the continuous read performance can be achieved, and the present invention also falls into the protection scope of the present invention.
In one embodiment of the present invention, the first reading module is further followed by a data length module, configured to request a Host end for a data length to be read; and sends the data length acquired in response to the request to the flash translation layer FTL.
Further, referring to another block diagram of an apparatus for performing both sequential read and random read of an eMMC memory according to the present invention as shown in fig. 7, in an embodiment of the present invention, the proposed apparatus includes the following modules: the second acquisition module is used for acquiring the data length of the data to be read; the second reading module is used for selecting and applying the first reading operation if the length of the acquired data is smaller than the first length; if the length of the acquired data is larger than the first length and smaller than the second length, selecting and applying a second reading operation; otherwise, a third read operation is applied to read the data. In an embodiment of the present invention, the first read operation and the second read operation may be the concurrent read operation and the single-line read operation, respectively, but it should be understood that the at least two predefined read operations may also be other read operation manners, as long as the two predefined read operation manners are different and the technical effect of considering both the random read performance and the continuous read performance can be achieved, and the present invention also falls into the protection scope of the present invention.
In an embodiment of the present invention, the second reading module is further followed by a data length module, configured to request a Host end for a data length to be read; and sends the data length acquired in response to the request to the flash translation layer FTL.
It should be understood that the first, second and third expressions are not meant to express an order, but merely to distinguish different read operations.
Finally, in an embodiment of the invention, a computer-readable storage medium is proposed, on which a computer program is stored, characterized in that the computer program realizes the above-mentioned method steps when executed by a processor.
It should be recognized that embodiments of the present invention can be realized and implemented by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer readable memory. The methods may be implemented in a computer program using standard programming techniques, including a non-transitory computer-readable storage medium configured with the computer program, where the storage medium so configured causes a computer to operate in a specific and predefined manner, according to the methods and figures described in the detailed description. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.
Further, the method may be implemented in any type of computing platform operatively connected to a suitable interface, including but not limited to a personal computer, mini computer, mainframe, workstation, networked or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and the like. Aspects of the invention may be embodied in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optically read and/or write storage medium, RAM, ROM, or the like, such that it may be read by a programmable computer, which when read by the storage medium or device, is operative to configure and operate the computer to perform the procedures described herein. Further, the machine-readable code, or portions thereof, may be transmitted over a wired or wireless network. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. The invention also includes the computer itself when programmed according to the methods and techniques described herein.
Embodiments of this disclosure are described herein, including the best mode known to the inventors for carrying out the invention. Variations of those described embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate, and the inventors intend for the embodiments of the disclosure to be practiced otherwise than as specifically described herein. Accordingly, the scope of the present disclosure includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, the scope of the present disclosure encompasses any combination of the above-described elements in all possible variations thereof unless otherwise indicated herein or otherwise clearly contradicted by context.
While the present invention has been described in considerable detail and with particular reference to a few illustrative embodiments thereof, it is not intended to be limited to any such details or embodiments or any particular embodiments, but it is to be construed as effectively covering the intended scope of the invention by providing a broad, potential interpretation of such claims in view of the prior art with reference to the appended claims. Furthermore, the foregoing describes the invention in terms of embodiments foreseen by the inventor for which an enabling description was available, notwithstanding that insubstantial modifications of the invention, not presently foreseen, may nonetheless represent equivalent modifications thereto.
The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. However, it will be apparent that: various modifications and changes may be made thereto without departing from the broader spirit and scope of the application as set forth in the claims.
Other variations are within the spirit of the present application. Accordingly, while the disclosed technology is susceptible to various modifications and alternative constructions, certain embodiments thereof have been shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the application to the specific form or forms disclosed; on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the application, as defined in the appended claims.
Claims (10)
1. A method for giving consideration to both sequential reading and random reading performances of an eMMC memory so as to improve the reading efficiency of the eMMC memory is characterized by comprising the following steps of:
a1, acquiring the data length of the data to be read;
and B1, selecting one of at least two predefined reading operations according to the acquired data length and applying the selected one to read the data.
2. A method for giving consideration to both sequential reading and random reading performances of an eMMC memory so as to improve the reading efficiency of the eMMC memory is characterized by comprising the following steps of:
a2, acquiring the data length of the data to be read;
b2, if the length of the acquired data is less than the first length, selecting and applying a first reading operation; if the length of the acquired data is larger than the first length and smaller than the second length, selecting and applying a second reading operation; otherwise, a third read operation is applied to read the data.
3. The method for achieving both sequential reading and random reading of the eMMC memory according to claim 1 or 2, wherein before the data length of the data to be read is obtained, the method further comprises the steps of:
requesting the Host end for the length of data to be read; and sends the data length acquired in response to the request to the flash translation layer FTL.
4. The method of claim 2, wherein a third read operation is applied to read data when the data length cannot be obtained.
5. The method of claim 2, wherein the eMMC memory is configured to perform both sequential and random read operations: the first length is 16 KB; the second length is 64 KB.
6. The method of claim 2, wherein the eMMC memory is configured to perform both sequential and random read operations: the second read operation is a concurrent read operation; and the third read operation is a read-ahead and concurrent read operation.
7. The method of claim 2, wherein the eMMC memory is configured to perform both sequential and random read operations: the read time of the second read operation is 1.5 times the read time of the first read operation.
8. An apparatus for improving reading efficiency of an eMMC memory by considering sequential reading and random reading performances of the eMMC memory, comprising the following modules:
the first acquisition module is used for acquiring the data length of the data to be read;
and the first reading module is used for selecting one of at least two predefined reading operations according to the acquired data length and applying the selected one to read the data.
9. An apparatus for improving reading efficiency of an eMMC memory by considering sequential reading and random reading performances of the eMMC memory, comprising the following modules:
the second acquisition module is used for acquiring the data length of the data to be read;
the second reading module is used for selecting and applying the first reading operation if the length of the acquired data is smaller than the first length; if the length of the acquired data is larger than the first length and smaller than the second length, selecting and applying a second reading operation; otherwise, a third read operation is applied to read the data.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program realizes the steps of the method according to one of claims 1 to 7 when executed by a processor.
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| JP2014182626A (en) * | 2013-03-19 | 2014-09-29 | Axell Corp | Method for reading out memory storage information, and memory interface |
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| CN113703664A (en) * | 2021-06-24 | 2021-11-26 | 杭州电子科技大学 | Random write rate optimization implementation method for eMMC chip |
| CN113703664B (en) * | 2021-06-24 | 2024-05-03 | 杭州电子科技大学 | Random writing rate optimization implementation method for eMMC chip |
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