CN110737196B - Design method of digital power supply loop compensator based on PID alpha - Google Patents
Design method of digital power supply loop compensator based on PID alpha Download PDFInfo
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Abstract
A design method of a digital power supply loop compensator based on PID alpha can realize stable, accurate and rapid control on the output voltage of a digital power supply, and comprises the following steps: (1) drawing a Bode diagram of a main power transfer function of the digital power supply based on simulation software; (2) designing an analog two-zero two-pole compensator with the same zero-pole type as the PID alpha digital loop compensator, and drawing a compensator bode diagram; (3) converting the analog two-zero two-pole compensator of the s-domain into a z-domain PID alpha digital loop compensator; (4) based on the structural characteristics of the PID alpha digital loop compensator algorithm, the function of the PID alpha digital loop compensator is realized by program programming; (5) and a prototype experiment debugs the function of the PID alpha digital power supply loop compensator. By adopting the design method of the loop compensator based on the PID alpha, the loop compensator with excellent performance can be designed aiming at the digital power supply, and the stable, accurate and quick control of the output voltage of the digital power supply is realized.
Description
Technical Field
The invention relates to the technical field of digital power supply control, in particular to a design method of a digital power supply loop compensator based on PID alpha.
Background
The accuracy and stability of the output voltage of the digital power supply and the rapidity of response to the input voltage and the load current disturbance are all determined by an open-loop gain phase curve diagram (namely a bird diagram) of the digital power supply system. The feedback system stability criteria are: at frequencies where the open loop gain is 1 (i.e., the crossover frequency fc), the open loop phase delay must be less than 360 °. Since the negative feedback is self-carrying a-180 phase delay, the difference between the phase angle at the crossover frequency fc and-180 is defined as the phase margin. If the phase margin is too small, self-oscillation of the DC/DC converter occurs. Engineering experience often designs the phase margin above 60 °. The accuracy of the feedback system is related to the gain of the system at 0Hz (i.e. the dc gain): the larger the dc gain, the more accurate the output voltage. Engineering experience often sets the dc gain above 50dB to meet higher output voltage accuracy. The rapidity of the feedback system is related to the open loop system crossing frequency: the larger the crossover frequency fc, the faster the feedback system.
The design of the loop compensator of the digital power supply is a key technology in the design of the digital power supply, and the realization method and algorithm optimization of the digital loop compensator directly determine an open-loop gain phase curve graph of a digital power supply system and determine the accuracy and rapidness of the regulation stability of the output voltage of the digital power supply.
The existing digital power supply based on the UCD3138 is implemented by a digital power supply control loop DPP to implement power supply feedback control. Each DPP control loop consists of a special error analog-to-digital converter EADC, a 2 pole and 2 zero digital PID alpha loop compensator and a DPWM output with 250ps pulse width resolution. The block diagram of a digital power supply control system based on UCD3138 is shown in fig. 1, an output voltage Vo passes through a sampling and conditioning circuit and then is input to an error analog-to-digital converter (EADC) conversion channel of a digital power supply control loop DPP of the UCD3138 for error comparison and analog-to-digital conversion, then a digitized error signal is input to a digital PID alpha loop compensator CLA to obtain a control signal, the control signal enters a DPWM module to generate a PWM driving signal to complete conversion from a digital quantity to an analog quantity, and a PWM wave is amplified by a driving circuit to control a digital power supply main power switch tube to work so as to complete control of the output voltage Vo of the digital power supply.
However, the problem of the existing UCD 3138-based digital power control technology is that the PID alpha loop compensator control coefficient KP、KI、KDAnd strong coupling relation exists among alpha and key coefficients in the digital power supply open-loop transfer function, namely static gain Ao, crossing frequency fc, zero point omega z and pole omega p, the adjustment of one compensator control coefficient can cause the transformation of a plurality of open-loop transfer function key coefficients, and the independent adjustment of the open-loop transfer function key coefficients is difficult to realize directly by correcting the compensator control coefficient, so that the stability, the accuracy and the rapidity of a control loop are accurately adjusted.
Disclosure of Invention
The design method of the digital power supply loop compensator based on the PID alpha can solve the technical problem that the stability, the accuracy and the rapidity of the control loop cannot be independently adjusted due to the strong coupling relation between the control coefficient of the PID alpha loop compensator and the key coefficient in the digital power supply open-loop transfer function.
In order to achieve the purpose, the invention adopts the following technical scheme:
a design method of a digital power supply loop compensator based on PID alpha comprises the following steps:
s100, drawing a Bode diagram of a main power transfer function of the digital power supply based on simulation software;
s200, designing an analog two-zero two-pole compensator which has the same zero-pole type as the PID alpha digital loop compensator;
s300, converting the analog two-zero two-pole compensator in the S domain into a z-domain PID alpha digital loop compensator;
s400, designing a corresponding hardware register of the controller to realize the function of the digital compensator by combining the structural characteristics of the PID alpha loop compensator algorithm of the digital controller;
s500, building a full-bridge digital power model machine, and setting the function of the PID alpha digital power loop compensator for experimental debugging.
Further, S100, drawing a bode diagram of a main power transfer function of the digital power supply based on simulation software; the method specifically comprises the following steps:
s101, setting main power topological parameters of the full-bridge digital power supply based on simulation software;
s102, simulating to obtain a bode diagram of a main power transfer function of the full-bridge digital power supply;
s103, determining the frequency f of the dual pole according to the bode diagram of the main power transfer function of the full-bridge digital power supplyLCAnd according to the dynamic performance requirement of the digital power supply system, setting the open-loop transfer function crossing frequency fc of the system, and determining the gain of the system at fc.
Further, the step S200 of designing an analog two-zero two-pole compensator having the same type of zero pole as the PID α digital loop compensator;
the method specifically comprises the following steps:
s201, the analog loop compensator and the PID alpha digital loop compensator have the same pole-zero mode, and the transfer function of the analog loop compensator and the PID alpha digital loop compensator in an S domain is shown as a formula (1);
expressing the formula (1) in a zero-pole form as shown in the following formula (2);
s202, obtaining a simulated Berde diagram of the analog two-zero two-pole compensator;
s203, configuring and simulating two zero point omega z1 and omega z2 frequencies in the two-zero-point two-pole compensator to inhibit the influence of the main power dual pole on the attenuation of the phase margin;
s204, configuring and simulating the frequency of a pole omega p1 in the two-zero two-pole compensator to suppress high-frequency interference signals;
s205, adjusting a gain coefficient Ko of the analog two-zero two-pole compensator to enable the gain of a frequency response curve of the analog loop compensator at the crossing frequency fc to be opposite to the gain of the main power part at the crossing frequency fc;
and S206, simulating to obtain a power system open-loop transfer function simulation Berde diagram.
Further, the S300 step of converting the analog two-zero two-pole compensator of the S-domain into a z-domain PID α digital loop compensator;
the method specifically comprises the following steps:
setting a bilinear transformation formula shown in the following formula (3) for mapping zero poles between an s domain and a z domain, converting the s domain formula into the z domain formula, wherein Ts is a sampling period of the digital power supply controller;
z＝es·Ts (3)
based on bilinear transformation of formula (3), converting a transfer function of the two-zero two-pole analog loop compensator shown in formula (1) in an s domain into a transfer function of the digital loop compensator in a z domain as shown in formula (4);
the corresponding relation between the PID alpha coefficient in the z domain and the pole zero in the s domain is shown in the following formula;
further, in the step S400, in combination with the structural feature of the PID α loop compensator algorithm of the digital controller, a corresponding hardware register of the controller is designed to implement the function of the digital compensator;
the method specifically comprises the following steps: adopting a PID alpha algorithm structure diagram of UCD3138 to obtain a difference equation of the PID alpha algorithm in a z domain as shown in the following formula;
y(z)＝yP(z)+yI(z)+yD(z) (9)
yP(z)＝KP·e(z) (10)
yI(z)＝z-1·yI(z)+KI(e(z)+z-1·e(z)) (11)
yD(z)＝α·z-1·yD(z)+KD(e(z)-z-1·e(z)) (12)
corresponding PID alpha coefficient K calculated based on step S300P、KI、KDAnd alpha, assigning values to corresponding register variables of the UCD3138 in the code to implement the digital loop controller function thereof.
Further, in the step S100, the digital power supply main power adopts any one of Buck, forward, half bridge and full bridge topology.
Further, in S100, the simulation software may be any one of Fusion Digital Power Designer, Matlab, MathCAD, Simplis, and Saber.
Further, the design method of the analog compensator in S200 adopts any one of a zero-pole configuration method, a simulation method, and an empirical trial and error method.
Further, in S300, the analog compensator is converted into a digital PID α compensator, and any one of bilinear transformation, forward differential transformation, and backward differential transformation is adopted.
Further, the digital controller in S400 employs UCD 3138.
Further, the programming language in S400 is any one of a C language and an assembler language.
Further, the experimental prototype described in S500 is a full-bridge digital power supply based on a PCB manufacturing process.
According to the technical scheme, the design method of the digital power supply loop compensator based on the PID alpha has the following beneficial effects:
therefore, the design method based on the PID alpha digital power supply loop compensator provided by the invention can design the loop compensator with excellent performance aiming at the digital power supply, and realizes the stable, accurate and rapid control of the output voltage of the digital power supply. The invention can effectively improve the phase margin and static gain of the switching power supply of the forward system main power topology, and can select proper system open loop transfer function crossing frequency according to the dynamic index of the power supply system, thereby effectively, stably, accurately and quickly controlling the output voltage of the digital power supply.
Drawings
FIG. 1 is a block diagram of a UCD3138 based digital power control system;
FIG. 2 is a block diagram of an implementation flow of the present invention;
FIG. 3 is a simulation bode diagram of the main power topology of the full-bridge digital power supply;
FIG. 4 is a diagram of a circuit diagram of a two-zero two-pole compensator;
FIG. 5 is a simulated Burdet plot of a two-zero two-pole compensator;
FIG. 6 is a graph of a power system open loop transfer function simulation bode;
fig. 7 is a diagram of a PID α algorithm structure of UCD 3138;
FIG. 8 is a measured Bode diagram of the main power portion of the full-bridge digital power supply;
FIG. 9 is a measured bode diagram of a PID α loop compensator of a full-bridge digital power supply;
FIG. 10 is a measured bode plot of the open loop transfer function of the full bridge digital power system;
FIG. 11 is a graph of PID α coefficients in the z-domain versus pole-zero variation in the s-domain.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
As shown in fig. 2, the design method of the digital power loop compensator based on PID α according to the present embodiment includes the following steps:
s100, drawing a Bode diagram of a main power transfer function of the digital power supply based on simulation software;
s200, designing an analog two-zero two-pole compensator which has the same zero-pole type as the PID alpha digital loop compensator;
s300, converting the analog two-zero two-pole compensator of the S domain into a z domain PID alpha digital loop compensator;
s400, designing a corresponding hardware register of the controller to realize the function of the digital compensator by combining the structural characteristics of the PID alpha loop compensator algorithm of the digital controller;
s500, a full-bridge digital power model machine is built, and the function of the PID alpha digital power loop compensator is set up for experimental debugging.
The following is a detailed description of each of the above steps:
As shown in fig. 3, a bode diagram of the main power transfer function of the full-bridge digital power supply is obtained through simulation.
Determining the frequency f of the dual pole according to the bode diagram of the main power transfer function of the full-bridge digital power supplyLCAbout 11kHz, and according to the dynamic performance requirement of the digital power supply system, setting the open-loop transfer function crossing frequency fc of the system to be 4kHz, and determining that the gain of the system at fc is about 9 dB.
And 2, designing the analog two-zero two-pole compensator which has the same zero-pole type as the PID alpha digital loop compensator and is shown in the figure 4 based on a zero-pole allocation method.
The analog loop compensator and the PID α digital loop compensator have the same pole-zero pattern, and their transfer functions in the s-domain are shown in equation (1).
Equation (1) is expressed in the form of a zero-pole, as shown in equation (2) below.
A simulated bode plot of the analog two-zero two-pole compensator shown in fig. 5.
In order to inhibit the influence of the double poles of the main power on the attenuation of the phase margin, the frequencies of two zeros omega z1 and omega z2 in the two-zero two-pole compensator are arranged at the frequency f of the double poleLCNear 8 kHz.
In order to effectively suppress high-frequency interference signals without influencing the lifting action of the zero points ω z1 and ω z2 on the phase margin, the frequency of the first pole ω p1 in the analog two-zero two-pole compensator is set to be 5 fc-20 kHz.
And adjusting the gain coefficient Ko of the analog two-zero two-pole compensator to ensure that the gain of the frequency response curve of the analog loop compensator part at the crossing frequency fc which is 4kHz is-9 dB, which is just opposite to the gain of the main power part at the crossing frequency fc, and at the moment, the open-loop frequency response curve of the system just crosses at the crossing frequency fc.
Such as the power supply system open loop transfer function simulation bode plot of fig. 6.
The simulation results show that the power supply system after loop compensation has a phase margin of about 114 degrees, a gain of about 51dB at 10Hz and a crossing frequency fc of about 3.9 kHz. The stability requirement that the phase margin is larger than 60 degrees, the accuracy requirement that the static gain is larger than 50dB and the dynamic performance requirement that the crossing frequency is about 4kHz in engineering application are met.
And 3, converting the analog two-zero two-pole compensator in the s domain into a z-domain PID alpha digital loop compensator based on a bilinear transformation method.
The bilinear transformation formula shown in the following formula (3) is used for mapping zero between an s domain and a z domain, and the s domain formula can be converted into the z domain formula, and Ts is a sampling period of the digital power supply controller.
z＝es·Ts (3)
Based on the bilinear transformation of equation (3), the transfer function of the two-zero two-pole analog loop compensator shown in equation (1) in the s-domain can be converted into the transfer function of the digital loop compensator in the z-domain as shown in equation (4) below.
The corresponding relation between the PID alpha coefficient in the z domain and the pole-zero in the s domain is shown as the following formula.
And 4, based on the structural characteristics of the PID alpha loop compensator of the UCD3138 digital controller, adopting C language programming to configure a corresponding function register to realize the function of the PID alpha digital loop compensator.
A structure diagram of the PID alpha algorithm of UCD3138 is shown in fig. 7.
From fig. 7, the difference equation of the PID α algorithm in the z-domain can be obtained as shown in the following formula.
y(z)＝yP(z)+yI(z)+yD(z) (9)
yP(z)＝KP·e(z) (10)
yI(z)＝z-1·yI(z)+KI(e(z)+z-1·e(z)) (11)
yD(z)＝α·z-1·yD(z)+KD(e(z)-z-1·e(z)) (12)
Corresponding PID alpha coefficient K calculated based on step 3P、KI、KDα, the corresponding register variable of UCD3138 may be assigned in the code to implement its digital loop controller function, and the relevant program segments are as follows:
#defineINIT_FILTER_0_KP_COEF_0(1500) (13)
#defineINIT_FILTER_0_KI_COEF_0(160) (14)
#defineINIT_FILTER_0_KD_COEF_0(2000) (15)
#defineINIT_FILTER_0_KD_ALPHA_0(150) (16)
and 5, taking the UCD3138 digital power supply controller as a main control chip, building a full-bridge digital power supply prototype, and debugging the functions of the PID alpha digital power supply loop compensator.
The measured main power bode diagram of the full-bridge digital power supply based on the frequency response analyzer is shown in fig. 8.
The bode diagram of the PID alpha loop compensator of the full-bridge digital power supply measured based on the frequency response analyzer is shown in FIG. 9.
The open-loop transfer function bode diagram of the digital power supply system after compensation of the full-bridge digital power supply PID α based on the actual measurement of the frequency response analyzer is shown in fig. 10.
From fig. 10, it can be seen that the compensated actual digital power supply system 10Hz has a gain of about 50dB, a crossover frequency fc of about 3.6kHz, and a phase margin of about 104 °, which is substantially the same as the simulation parameters based on fusion digital power designer in step 2, and the deviation between the two is less than 10%, and the main reason for generating the deviation is that the simulation model ignores the parasitic parameters of the actual device and the sampling quantization delay link of the digital controller UCD 3138.
In order to correct the deviation between the simulation and the actual parameters, the relation between the PID alpha coefficient in the z-domain and the pole-zero change in the s-domain can be deduced according to the expressions (5), (6), (7) and (8) for correction.
The relationship of the PID α coefficients in the z-domain to the pole-zero variation in the s-domain is shown in fig. 11.
As shown in FIG. 11, increase KPThe gain between the zero points can be improved and the two zero point frequencies can be separated; increase of KIThe low-frequency gain can be improved and the low-frequency zero frequency can be improved; increase of KDThe high-frequency zero frequency can be reduced; increasing a can lower the high frequency zero frequency and lower the high frequency pole frequency, and vice versa.
In summary, the design method of the digital power supply loop compensator based on the PID α provided by the embodiment of the present invention can effectively improve the phase margin and the static gain of the switching power supply of the forward main power topology, and can select a suitable system open loop transfer function crossing frequency according to the dynamic index of the power supply system, thereby effectively, accurately and rapidly controlling the output voltage of the digital power supply.
The above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (7)
1. A design method of a digital power supply loop compensator based on PID alpha is characterized in that: the method comprises the following steps:
s100, drawing a Bode diagram of a main power transfer function of the digital power supply based on simulation software;
s200, designing an analog two-zero two-pole compensator with the same zero-pole type as the PID alpha digital loop compensator;
s300, converting the analog two-zero two-pole compensator of the S domain into a z domain PID alpha digital loop compensator;
s400, designing a corresponding hardware register of the controller to realize the function of the digital compensator by combining the structural characteristics of the PID alpha loop compensator algorithm of the digital controller;
s500, building a full-bridge digital power supply prototype, and setting the function of an experimental debugging PID alpha digital power supply loop compensator;
wherein, the S200 designs an analog two-zero two-pole compensator with the same zero-pole type as the PID alpha digital loop compensator;
the method specifically comprises the following steps:
s201, setting the analog loop compensator and the PID alpha digital loop compensator to have the same pole-zero mode, wherein the transfer function of the analog loop compensator and the PID alpha digital loop compensator in an S domain is shown as a formula (1);
expressing the equation (1) in a zero-pole form as shown in the following equation (2);
s202, obtaining a simulated Berde diagram of the analog two-zero two-pole compensator;
s203, configuring and simulating two zero point omega z1 and omega z2 frequencies in the two-zero-point two-pole compensator to inhibit the influence of the main power dual pole on the attenuation of the phase margin;
s204, configuring and simulating the frequency of a pole omega p1 in the two-zero two-pole compensator to suppress high-frequency interference signals;
s205, adjusting a gain coefficient Ko of the analog two-zero two-pole compensator to enable the gain of a frequency response curve of the analog loop compensator at the crossing frequency fc to be opposite to the gain of the main power part at the crossing frequency fc;
s206, simulating to obtain a Bode diagram of the open-loop transfer function of the power supply system;
the S300, converting the analog two-zero two-pole compensator of the S domain into a z domain PID alpha digital loop compensator;
the method specifically comprises the following steps:
setting a bilinear transformation formula shown in the following formula (3) to be used for mapping zero-pole between an s domain and a z domain, converting the s domain formula into the z domain formula, wherein Ts is a sampling period of the digital power supply controller;
z＝es·Ts (3)
based on bilinear transformation of the formula (3), the transfer function of the two-zero two-pole analog loop compensator shown in the formula (1) in the s domain is converted into the transfer function of the digital loop compensator in the z domain as shown in the following formula (4);
the corresponding relation between the PID alpha coefficient in the z domain and the pole zero in the s domain is shown in the following formula;
s400, designing a corresponding hardware register of the controller to realize the function of the digital compensator by combining the structural characteristics of the PID alpha loop compensator algorithm;
the method specifically comprises the following steps: adopting a PID alpha algorithm structure diagram of UCD3138 to obtain a difference equation of the PID alpha algorithm in a z domain as shown in the following formula;
y(z)＝yP(z)+yI(z)+yD(z) (9)
yP(z)＝KP·e(z) (10)
yI(z)＝z-1·yI(z)+KI(e(z)+z-1·e(z)) (11)
yD(z)＝α·z-1·yD(z)+KD(e(z)-z-1·e(z)) (12)
corresponding PID alpha coefficient K calculated based on step S300P、KI、KDAnd alpha, assigning values to corresponding register variables of the UCD3138 in the code to implement the digital loop controller function thereof.
2. The design method of the PID α -based digital power loop compensator according to claim 1, wherein: s100, drawing a Bode diagram of a main power transfer function of the digital power supply based on simulation software; the method specifically comprises the following steps:
s101, setting main power topological parameters of the full-bridge digital power supply based on simulation software;
s102, simulating to obtain a bode diagram of a main power transfer function of the full-bridge digital power supply;
s103, determining a dual-pole frequency f according to a full-bridge digital power supply main power transfer function bode diagramLCSetting the open-loop transfer function of the system according to the dynamic performance requirement of the digital power supply systemThe number crossing frequency fc, determines the gain of the system at fc.
3. The design method of the PID α -based digital power loop compensator according to claim 1, wherein: in the step S100, the main power of the digital power supply adopts any one of Buck, forward, half-bridge and full-bridge topologies.
4. The design method of the PID α -based digital power loop compensator according to claim 1, wherein: in S100, the simulation software adopts any one of Fusion Digital Power Designer, Matlab, MathCAD, Simplis and Saber.
5. The design method of the PID α -based digital power loop compensator according to claim 1, wherein: in the S200, the design method of the analog two-zero two-pole compensator having the same type of zero and pole as the PID α digital loop compensator adopts any one of a zero and pole allocation method, a simulation method, and an empirical trial and error method.
6. The design method of the PID α -based digital power loop compensator according to claim 1, characterized in that: in S300, the analog two-zero two-pole compensator in the S domain is converted into a z-domain PID α digital loop compensator, and any one of bilinear transformation, forward differential transformation, and reverse differential transformation is adopted.
7. The design method of the PID α -based digital power loop compensator according to claim 1, wherein: the digital controller in S400 employs UCD 3138.
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