CN111400987B - Double-closed-loop BUCK converter based on frequency domain analysis and loop design method thereof - Google Patents

Double-closed-loop BUCK converter based on frequency domain analysis and loop design method thereof Download PDF

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CN111400987B
CN111400987B CN202010134907.2A CN202010134907A CN111400987B CN 111400987 B CN111400987 B CN 111400987B CN 202010134907 A CN202010134907 A CN 202010134907A CN 111400987 B CN111400987 B CN 111400987B
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loop
current
compensation
frequency
voltage
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CN111400987A (en
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宋久旭
高鹏飞
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Xian Shiyou University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention provides a loop design method of a double closed loop BUCK converter based on frequency domain analysis, which takes an average current mode BUCK converter as a model to carry out system analysis on the model; deducing a transfer function of the system through a model analysis result, and carrying out frequency domain analysis on the basis of the obtained transfer function; according to the frequency domain analysis result, carrying out current loop compensation design; on the basis of current loop compensation, carrying out voltage loop compensation design; and according to the current loop compensation and the voltage loop compensation, obtaining the double closed loop BUCK converter with the double loop compensation. Meanwhile, the double closed loop BUCK converter based on frequency domain analysis is designed by the loop design method. The invention designs the average current type double-closed-loop BUCK converter by selecting proper current loop compensation and voltage loop compensation, and verifies the correctness and feasibility of the double-closed-loop BUCK converter through simulation, thereby greatly reducing the research and development difficulty and the research and development period of the switching power supply.

Description

Double-closed-loop BUCK converter based on frequency domain analysis and loop design method thereof
Technical Field
The invention relates to the technical field of loop design of a current type control system (double-loop control system), in particular to a double-closed-loop BUCK converter based on frequency domain analysis and a loop design method thereof.
Background
The DC-DC switching power supply has the advantages of high efficiency, high power density, high reliability and the like, and is widely applied to the fields of communication, computers, industrial equipment, household appliances and the like. The design of the control loop of the switching power supply is always a difficult point of the switching power supply, and the time domain design or the simple debugging is adopted for probing in the traditional research and development process, so that the research and development difficulty and the research and development period are certainly increased.
The search finds that: the adoption of the time domain design is to directly realize steady-state error and dynamic response of the system in the time domain by adopting a PI or PID controller. And the simple debugging is performed by observing specific experimental waveforms through simple compensation according to experience, so that loop stability of the circuit is realized.
No description or report of similar technology is found at present, and similar data at home and abroad are not collected.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a double-closed-loop BUCK converter based on frequency domain analysis and a loop design method thereof. The method takes an average current mode BUCK converter as a model, derives a transfer function of the system by carrying out system analysis on the BUCK converter, further carries out frequency domain analysis, and respectively selects proper current loop compensation and voltage loop compensation to design an average current mode double-closed loop BUCK converter.
The invention is realized by the following technical scheme.
According to one aspect of the invention, there is provided a loop design method of a double closed loop BUCK converter based on frequency domain analysis, comprising:
s1, taking an average current mode BUCK converter as a model, and performing system analysis on the model;
s2, deducing a transfer function of the system according to the model analysis result obtained in the S1, and carrying out frequency domain analysis on the basis of the obtained transfer function;
s3, carrying out current loop compensation design according to the frequency domain analysis result obtained in the S2;
s4, carrying out voltage loop compensation design on the basis of the current loop compensation obtained in the S3;
and S5, obtaining the double-closed-loop BUCK converter with double-loop compensation according to the current loop compensation obtained in the step S3 and the voltage loop compensation obtained in the step S4.
Preferably, in S1, using the average current mode BUCK converter as a model, the system analysis of the model includes:
will output a voltage signal V o And the sampled voltage signal V ref After comparison, the voltage is sent to a voltage controller VA, and after compensation, a voltage signal V is generated VA Obtaining a voltage outer ring;
the inductance current is passed through a sampling resistor to obtain a voltage feedback signal V RS Compensated by a current controller CA and then connected with a voltage signal V VA After comparison, a voltage signal V is generated CA Obtaining a current outer ring;
voltage signal V CA And saw-tooth wave signal V M Generating a PWM signal for controlling the power tube after comparison;
when the switching tube is turned on, the inductor current rises and the current controller outputs a voltage signal V CA Descending when V CA ＝V M When the switch tube is turned off; when the switching tube is turned off, the inductance current drops, and the current controller outputs a voltage signal V CA Rise to when V CA ＝V M When the switch tube is turned on; wherein the voltage signal V CA The rising slope of (a) must be smaller than the sawtooth wave V M I.e. slope matching.
Preferably, in the step S2, a transfer function of the system is:
duty cycle d to output voltage V o Is a small signal transfer function G of (2) vd (s) is:
wherein: q is the quality factor of the product,s is an imaginary variable, w z0 To control the zero angular frequency of the loop, w z0 ＝1/R c C；w p0 To control the pole angular frequency of the loop, < >>
The transfer function H(s) of the sampling element is:
wherein R is 1 And R is 2 Forming a voltage sampling network;
transfer function G of PWM link M (s) is:
wherein V is M Is a sawtooth peak value;
let the transfer function G of the compensation link c (s) =1, resulting in an uncompensated system open loop transfer function T(s) of:
wherein: t (T) u0 In order to achieve a direct current gain,
setting electric parameters of a power loop of the BUCK converter in an average current mode, substituting the electric parameters of the power loop into an open loop transfer function T(s) of the system when compensation is not added to obtain an open loop amplitude-frequency characteristic curve of the BUCK converter, and carrying out frequency domain analysis on the obtained open loop amplitude-frequency characteristic curve to obtain the crossing frequency and the phase margin of the system when the loop is opened.
Preferably, in the step S3, the method for performing current loop compensation design includes:
the ramp up slope of the sawtooth wave is:
wherein: t (T) s Is a sawtooth wave period;
the slope matching standard of two PWM input ends is as follows:
wherein G is max Maximum gain for the current compensation network;
thus, the following steps are obtained:
the transfer function A of the control object of the current controller is obtained by carrying out small signal analysis on the voltages from the current compensation network to the two ends of the current sampling P (s) is:
the open loop transfer function T(s) of the current control loop is:
let |t(s) |=1 to obtain the crossing frequency f c The method comprises the following steps:
a single pole-single zero compensation network is used as compensation of the current controller, wherein the single pole-single zero compensation network has a transfer function G C (s) is:
wherein K is c To compensate the network DC gain for the current, K c ≈R i2 /R i1 ；w z Compensating the zero angular frequency of the network for current, w z ＝1/(R i2 C i2 )；w p Compensating the angular frequency of the poles of the network for current, w p ＝1/(R i2 C i1 )；R i1 To compensate the resistance; r is R i2 To compensate the resistance; c (C) i1 To compensate the capacitance; c (C) i2 To compensate for the capacitance.
Setting a high-frequency pole at a switching frequency, and compensating the gain G of a single pole-single zero compensation network c ＝R i2 /R i1 ＝G max Obtained by the formula (7):
to ensure a sufficient phase margin, the zero frequency is set at half the crossover frequency as much as possible, resulting in:
setting a high-frequency pole at a switching frequency to obtain:
to have a sufficient width for the mid-band to increase the phase margin, let:
C i2 ＝(10-25)C i1 (15)
combined type (12), (13), (14), (15) to obtain: resistor R i1 Resistance R i2 Capacitance C i1 Capacitance C i2 Is a value of (2).
Preferably, in the step S4, the method for performing voltage loop compensation design includes:
simplifying the closed loop transfer function of the current control loop to obtain a simplified closed loop transfer function A if The method comprises the following steps:
wherein w is p Pole angular frequency for the current control loop; damping coefficient ζ=1;
the load Z(s) of the current control loop consists of an output capacitor and a load, and the transfer function is as follows:
wherein w is z1 For the zero angular frequency of the load loop, w z1 ＝1/R c C；w p1 For the angular frequency of the pole of the load loop, w p1 ＝1/[(R c +R)C]。
The control object of the voltage controller consists of a current closed loop transfer function and a load network, and the transfer function A thereof p (s) is:
wherein w is p2 For controlling the angular frequency of the pole of the loop, w p2 ＝w p /2。
From equation (18), the control object of the voltage controller is composed of three poles and a zero point, and adopts a bipolar point-bipolar zero point as compensation, wherein the bipolar point-bipolar zero point compensation network has a transfer function G v (s) is:
wherein w is vz1 Is the zero angular frequency of the voltage controller, w vz2 Is the zero angular frequency of the voltage controller, w vp1 Is the angular frequency of the pole of the voltage controller, w vp2 The pole angular frequency of the voltage controller; w (w) vz1 ＜w vz2 ＜w vp1 ＜w vp2 ；K v The voltage controller is DC gain, R v1 To compensate for resistance, R v2 To compensate for resistance, R v3 To compensate for resistance, C v1 To compensate for capacitance, C v2 To compensate for capacitance, C v3 To compensate the capacitance; k (K) v ＝1/(R v1 C v2 )；w vz1 ＝1/(R v2 C v2 )；w vz2 ＝1/(R v1 C v3 )；w vp1 ＝1/(R v3 C v3 )；w vp2 ＝1/(R v2 C v1 )。
Preferably, in the step S5, a double-loop Buck converter with double-loop compensation is added, and the transfer function T thereof v (s) is:
and (3) making:
G v the first zero point of(s) is located at A p At the load pole of(s): w (w) vz1 ＝w p1 ；
G v One pole of the second zero current loop of(s): w (w) vz2 ＝w p2 ；
G v The first pole of(s) cancels the zero caused by the output filter capacitance ESR: w (w) vp1 ＝w z1 ；
G v The second pole of(s) is placed at the switching frequency f s The high frequency attenuation is increased: w (w) vp2 ＝w p ；
Taking the crossing frequency f c ＝f s /4, when f=f c Time |T v (s) |=1, i.e. K v ＝R s f c /(RHf p1 ) From this, it is possible to: resistor R v1 Resistance R v2 Resistance R v3 Capacitance C v1 Capacitance C v2 Capacitance C v3 Is a value of (2).
According to another aspect of the invention, a frequency domain analysis-based double-closed-loop BUCK converter is provided, and the frequency domain analysis-based double-closed-loop BUCK converter is designed by adopting any one or any multiple loop design methods on the basis of an average current mode BUCK converter.
Preferably, in the dual closed loop BUCK converter based on frequency domain analysis:
the main power loop sets the following parameters: input voltage V i =30v, output voltage V o =15v, input current I o =5a, switching frequency f s =100 KHz, inductance l=50uh, filter capacitance c=500 uF, sampling resistance R s =0.1Ω, parasitic resistance R c =0.1Ω, load r=3Ω;
the voltage sampling network is set as follows:
the PWM link is set as follows:
the loop part sets parameters according to the result of loop calculation as follows: for the current inner loop, the compensation resistor R i1 =1kΩ; compensation resistor R i2 =13 kΩ; supplementary capacitor C i1 =120 pF; compensating capacitor C i2 =1.2 nF; for the voltage outer loop, the compensation resistor R v1 =1kΩ; compensation resistor R v2 =390 Ω; compensation resistor R v3 =16kΩ; compensating capacitor C v1 =4nf; compensating capacitor C v2 =40 uF; compensating capacitor C v3 ＝3.12nF。
Compared with the prior art, the invention has the following beneficial effects:
aiming at the complexity problem of a current type control system (a double-loop control system) in the aspect of loop design, the invention provides a double-closed-loop BUCK converter based on frequency domain analysis and a loop design method thereof, wherein an average current mode BUCK converter is taken as a model, the system analysis is carried out on the current mode BUCK converter, the transfer function of the system is deduced, the frequency domain analysis is further carried out, and proper current loop compensation and voltage loop compensation are respectively selected, so that the average current type double-closed-loop BUCK converter is designed.
According to the double-closed-loop BUCK converter and the loop design method thereof based on frequency domain analysis, the correctness and feasibility of the design method are verified through PSIM simulation, the double-closed-loop BUCK converter has a certain reference value for loop design of the switching power supply, and the research and development difficulty and the research and development period of the switching power supply are greatly reduced.
The invention provides a double closed loop BUCK converter based on frequency domain analysis and a loop design method thereof, which establish a model of a current control type BUCK converter, and design the current control type BUCK converter by adding a proper compensation network to the frequency domain analysis of a current inner loop and a voltage outer loop, thereby providing reference for the research of a complex current type converter.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a schematic circuit diagram of an average current mode BUCK converter according to a preferred embodiment of the present invention;
FIG. 2 is a Bode plot of an open loop amplitude-frequency characteristic of an average current mode BUCK converter provided in a preferred embodiment of the present invention;
FIG. 3 is a schematic diagram of a single pole-single zero compensation network provided in a preferred embodiment of the present invention;
FIG. 4 is a block diagram of an equivalent single loop control system provided in a preferred embodiment of the present invention;
FIG. 5 is a schematic diagram of a bipolar point-to-dual zero compensation network provided in a preferred embodiment of the present invention;
FIG. 6 is a Bode diagram of a dual loop control system provided in a preferred embodiment of the present invention;
FIG. 7 is a schematic diagram of a dual closed loop BUCK converter simulation circuit provided in a preferred embodiment of the present invention;
FIG. 8 is a graph of simulation results of an open loop BUCK converter provided in a preferred embodiment of the present invention;
FIG. 9 is a diagram showing simulation results of the BUCK converter after closed loop compensation according to the preferred embodiment of the present invention.
Detailed Description
The following describes embodiments of the present invention in detail: the embodiment is implemented on the premise of the technical scheme of the invention, and detailed implementation modes and specific operation processes are given. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the invention, which falls within the scope of the invention.
The embodiment of the invention provides a loop design method of a double-closed-loop BUCK converter based on frequency domain analysis, which takes an average current mode BUCK converter as a model, deduces a transfer function of a system by carrying out system analysis on the BUCK converter, further carries out frequency domain analysis, and respectively selects proper current loop compensation and voltage loop compensation to design the double-closed-loop BUCK converter with an average current mode; and finally, PSIM software simulation is adopted to verify the correctness and feasibility of the design method.
The loop design method of the double closed loop BUCK converter based on frequency domain analysis provided by the embodiment of the invention is described in detail below with reference to the accompanying drawings.
1. Average current control principle
The basic structure of the average current mode BUCK converter is shown in fig. 1. Wherein V is i Is input voltage, V o Is output voltage, L is inductance, D is freewheeling diode, R s For sampling resistance, R c Parasitic resistance, filter capacitance as C, and load as R.
BUCK converter in average current control mode, and voltage outer loop is formed by outputting voltage signal V o And the sampled voltage signal V ref After comparison, the voltage is sent to a voltage controller VA, and after compensation, V is generated VA Obtaining a signal; the current inner loop obtains a voltage feedback signal V from the inductance current through a sampling resistor RS After being compensated by the current controller CA, the current is matched with V VA After the signal comparison, a voltage signal V is generated CA Obtaining; final voltage signal V CA And saw-tooth wave signal V M And generating a PWM signal for controlling the power tube after comparison. It can be seen that when the switching tube is turned on, the inductor current rises and the current controller outputs V CA Descending when V CA＝ V M When the switch tube is turned off; when the switching tube is turned off, the inductance current drops, and the current controller outputs V CA Rise to when V CA＝ V M And when the switch tube is turned on. Wherein the voltage signal V CA The rising slope of (a) must be smaller than the sawtooth wave V M I.e. the slope matches (the rising slope of the sawtooth cannot be exceeded by the rising slope of the amplified inductor current).
2. Power circuit
As shown in table 1, the average current mode BUCK converter power loop electrical parameters are shown. Wherein I is o For outputting current, f s Is the switching frequency.
TABLE 1 principal electrical parameters
Duty cycle d to output voltage V o Is a small signal transfer function G of (2) vd (s) is:
wherein: q is the quality factor of the product,s is an imaginary variable, w z0 To control the zero angular frequency of the loop, w z0 ＝1/R c C；w p0 To control the pole angular frequency of the loop, < >>
The transfer function H(s) of the sampling element is:
wherein R is 1 And R is 2 Forming a voltage sampling network;
transfer function G of PWM link M (s) is:
wherein V is M The value of the sawtooth peak value is preferably 4V.
First, let the transfer function G of the compensation link c (s) =1, the system open loop transfer function T(s) can be obtained without compensation as:
wherein: t (T) u0 In order to achieve a direct current gain,
the parameters of Table 1 are taken to equation (4) and the open loop amplitude-frequency characteristic of the BUCK variator is developed using MATLAB, as shown in FIG. 2.
As can be seen from FIG. 2, the system cross-over frequency at the time of open loop is 1.95KHz, and the phase margin is 36 degrees. The crossing frequency of the system is less than 1/10 of the switching frequency, the phase margin is less than 45 degrees, the steady state error is 30.3%, and the system is unstable. Therefore, a reasonably designed compensation network is required to enable the BUCK converter to stably operate.
3. Current inner loop design
The ramp up slope of the sawtooth wave is:
wherein: t (T) s Is a sawtooth period.
The slope matching standard of two PWM input ends is as follows:
wherein G is max The maximum gain of the network is compensated for current.
Thus, the following steps are obtained:
the transfer function A of the current controller control object is obtained by carrying out small signal analysis on the voltages from the current compensation network to the two ends of the current sampling P (s) is:
the open loop transfer function T(s) of the current control loop is:
let |t(s) |=1 to obtain the crossing frequency f c The method comprises the following steps:
as can be seen from equation (9), the control object of the current control loop is an approximate integration link, and a design often requires a sufficient phase margin at the crossover frequency and the frequency band flatness. A single pole-single zero compensation network is used as compensation for the current controller.
As in fig. 3, a single pole-single zero compensation network with a transfer function G C (s) is:
wherein K is c To compensate the network DC gain for the current, K c ≈R i2 /R i1 ；w z Compensating the zero frequency of the network for current, w z ＝1/(R i2 C i2 )；w p Compensating the network pole frequency, w for current p ＝1/(R i2 C i1 )；R i1 To compensate the resistance; r is R i2 To compensate the resistance; c (C) i1 To compensate the capacitance; c (C) i2 To compensate for the capacitance.
Setting a high-frequency pole at a switching frequency, and compensating the gain G of a single pole-single zero compensation network c ＝R i2 /R i1 ＝G max Obtained by the formula (7):
to ensure a sufficient phase margin, the zero frequency is set at half the crossover frequency as much as possible, resulting in:
setting a high-frequency pole at a switching frequency to obtain:
to have a sufficient width for the mid-band to increase the phase margin, let:
C i2 ＝(10-25)C i1 (15)
combined type (12), (13), (14), (15) can be obtained: r is R i1 ＝1kΩ；R i2 ＝13kΩ；C i1 ＝120pF；C i2 ＝1.2nF。
4. Voltage outer ring design
A single pole-single zero compensation network is adopted as compensation of a current controller, a closed loop transfer function of a current control loop obtained after calculation is a high-order system, and A for simplifying processing is needed if And (3) representing.
Wherein w is p Pole angular frequency for the current control loop; damping coefficient ζ=1. The load Z(s) of the current control loop consists of an output capacitor and a load, and the transfer function is as follows:
wherein w is z1 For the zero angular frequency of the load loop, w z1 ＝1/R c C；w p1 For the angular frequency of the pole of the load loop, w p1 ＝1/[(R c +R)C]。
As can be seen from fig. 4, the control object of the voltage controller consists of a current closed loop transfer function and a load network, the transfer function a thereof p (s) is:
wherein w is p2 Compensating the angular frequency of the poles of the network for current, w p2 ＝w p /2。
As can be seen from equation (18), the control object of the voltage controller is composed of three poles and one zero point, and the two poles-two zero points are adopted as compensation:
as shown in fig. 5, a bipolar point-double zero compensation network with a transfer function G v (s) is:
wherein: w (w) vz1 Compensating the zero angular frequency of the network for voltage, w vz2 Compensating the zero angular frequency of the network for voltage, w vp1 Compensating the angular frequency of the poles of the network for voltage, w vp2 Compensating the angular frequency of the pole of the network for the voltage; w (w) vz1 ＜w vz2 ＜w vp1 ＜w vp2 ；K v For compensating network DC gain for voltage, R v1 To compensate for resistance, R v2 To compensate for resistance, R v3 To compensate for resistance, C v1 To compensate for capacitance, C v2 To compensate for capacitance, C v3 To compensate the capacitance; k (K) v ＝1/(R v1 C v2 )；w vz1 ＝1/(R v2 C v2 )；w vz2 ＝1/(R v1 C v3 )；w vp1 ＝1/(R v3 C v3 )；w vp2 ＝1/(R v2 C v1 )。
5. Dual closed loop BUCK converter system analysis
The transfer function of the Buck converter with double-loop compensation is as follows:
let G v The first zero point of(s) is located at A p At the load pole of(s): w (w) vz1 ＝w p1 ；G v One pole of the second zero current loop of(s): w (w) vz2 ＝w p2 ；G v The first pole of(s) cancels the zero caused by the output filter capacitance ESR: w (w) vp1 ＝w z1 ；G v The second pole of(s) is placed at the switching frequency f s The high frequency attenuation is increased: w (w) vp2 ＝w p 。
Taking the crossing frequency f c ＝f s /4, when f=f c Time |T v (s) |=1, i.e. K v ＝R s f c /(RHf p1 ) =25, thereby obtaining R v1 ＝1kΩ；R v2 ＝38.8kΩ；R v3 ＝16kΩ；C v1 ＝40pF；C v2 ＝40nF；C v3 ＝3.12nF。
As can be seen from fig. 6, the system has a crossover frequency of 33KHz and a phase margin of 56 degrees. Compared with the prior art, the system crossing frequency is increased (more than 1/10 of the switching frequency), the phase margin is more than 45 degrees, the steady state error is 1%, and the BUCK converter has good stability and transient response.
6. Simulation verification
To verify the correctness of the voltage and current loop designs, a BUCK converter was built with PSIM, as shown in fig. 7.
The simulation results are shown in fig. 8 and 9. It can be seen from fig. 8 and 9 that the output voltage ripple of the BUCK converter after compensation is 0.5% of the output voltage, the adjustment time is less than 2ms, the overshoot is 3.78%, the dynamic performance of the system is good, and the design requirement is met.
The embodiment of the invention simultaneously provides a frequency domain analysis-based double-closed-loop BUCK converter, which is designed by adopting any one or any multiple loop design methods on the basis of an average current mode BUCK converter.
Further, as shown in fig. 7, in the dual closed loop BUCK converter based on frequency domain analysis:
the main power loop sets the following parameters according to table 1: input voltage V i Output voltage V o Input current I o Switching frequency f s An inductor L, a filter capacitor C and a sampling resistor R s Parasitic resistance R c A load R;
the voltage sampling network is set as follows:
the PWM link is set as follows:
the loop part sets parameters according to the result of loop calculation as follows: for the inner loop of the current, R i1 ＝1kΩ；R i2 ＝13kΩ；C i1 ＝120pF；C i2 =1.2 nF; for the voltage outer loop, R v1 ＝1kΩ；R v2 ＝390Ω；R v3 ＝16kΩ；C v1 ＝4nF；C v2 ＝40uF；C v3 ＝3.12nF。
According to the double closed-loop BUCK converter based on the frequency domain analysis and the loop design method thereof, provided by the embodiment of the invention, the average current mode BUCK converter is taken as a model, the system analysis is carried out on the model, the transfer function of the system is deduced, the frequency domain analysis is further carried out, and proper current loop compensation and voltage loop compensation are respectively selected, so that the average current mode double closed-loop BUCK converter is designed; finally, PSIM software simulation is adopted to verify the correctness and feasibility of the design method; the method provided by the embodiment of the invention has a certain reference value for the loop design of the switching power supply converter, and greatly reduces the research and development difficulty and the research and development period of the switching power supply.
The foregoing describes specific embodiments of the present invention. It is to be understood that the invention is not limited to the particular embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the claims without affecting the spirit of the invention.

Claims (4)

1. The loop design method of the double closed loop BUCK converter based on frequency domain analysis is characterized by comprising the following steps of:
s1, taking an average current mode BUCK converter as a model, and performing system analysis on the model;
s2, deducing a transfer function of the system according to the model analysis result obtained in the S1, and carrying out frequency domain analysis on the basis of the obtained transfer function;
s3, carrying out current loop compensation design according to the frequency domain analysis result obtained in the S2;
s4, carrying out voltage loop compensation design on the basis of the current loop compensation obtained in the S3;
s5, obtaining a double-closed-loop BUCK converter added with double-loop compensation according to the current loop compensation obtained in the S3 and the voltage loop compensation obtained in the S4;
in the step S1, using the average current mode BUCK converter as a model, performing system analysis on the model, including:
will output a voltage signal V o And the sampled voltage signal V ref After comparison, the voltage is sent to a voltage controller VA, and after compensation, a voltage signal V is generated VA Obtaining a voltage outer ring;
the inductance current is passed through a sampling resistor to obtain a voltage feedback signal V RS Compensated by a current controller CA and then connected with a voltage signal V VA After comparison, a voltage signal V is generated CA Obtaining a current outer ring;
voltage signal V CA And saw-tooth wave signal V M Generating a PWM signal for controlling the power tube after comparison;
when the switching tube is turned on, the inductor current rises and the current controller outputs a voltage signal V CA Descending when V CA ＝V M When the switch tube is turned off; when the switching tube is turned off, the inductance current drops, and the current controller outputs a voltage signal V CA Rise to when V CA ＝V M When the switch tube is turned on; wherein the voltage signal V CA The rising slope of (a) must be smaller than the sawtooth wave V M I.e. slope match;
in the step S2, the transfer function of the system is:
duty cycle d to output voltage V o Is a small signal transfer function G of (2) vd (s) is:
wherein: q is the quality factor of the product,s is an imaginary variable, w z0 To control the zero angular frequency of the loop, w z0 ＝1/R c C；w p0 To control the pole angular frequency of the loop, < >>V i Is an input voltage signal;
the transfer function H(s) of the sampling element is:
wherein R is 1 And R is 2 Forming a voltage sampling network;
transfer function G of PWM link M (s) is:
wherein V is M Is a sawtooth peak value;
let the transfer function G of the compensation link c (s) =1, resulting in an uncompensated system open loop transfer function T(s) of:
wherein: t (T) u0 In order to achieve a direct current gain,
setting electric parameters of a power loop of the BUCK converter in an average current mode, substituting the electric parameters of the power loop into an open loop transfer function T(s) of the system when compensation is not added to obtain an open loop amplitude-frequency characteristic curve of the BUCK converter, and carrying out frequency domain analysis on the obtained open loop amplitude-frequency characteristic curve to obtain the crossing frequency and phase margin of the system when the loop is opened;
in the step S3, the method for performing current loop compensation design includes:
the ramp up slope of the sawtooth wave is:
wherein: t (T) s Is a sawtooth wave period, f s Is the switching frequency;
the slope matching standard of two PWM input ends is as follows:
wherein G is max Maximum gain for the current compensation network;
thus, the following steps are obtained:
the transfer function A of the control object of the current controller is obtained by carrying out small signal analysis on the voltages from the current compensation network to the two ends of the current sampling P (s) is:
the open loop transfer function T(s) of the current control loop is:
let |t(s) |=1 to obtain the crossing frequency f c The method comprises the following steps:
a single pole-single zero compensation network is used as compensation of the current controller, wherein the single pole-single zero compensation network has a transfer function G C (s) is:
wherein K is c For DC gain, K c ≈R i2 /R i1 ；w z Compensating the zero angular frequency of the network for current, w z ＝1/(R i2 C i2 )；w p Compensating the angular frequency of the poles of the network for current, w p ＝1/(R i2 C i1 )；R i1 To compensate the resistance; r is R i2 To compensate the resistance; c (C) i1 To compensate the capacitance; c (C) i2 To compensate the capacitance;
setting a high-frequency pole at a switching frequency, and compensating the gain G of a single pole-single zero compensation network c ＝R i2 /R i1 ＝G max Obtained by the formula (7):
to ensure a sufficient phase margin, the zero frequency is set at half the crossover frequency as much as possible, resulting in:
setting a high-frequency pole at a switching frequency to obtain:
to have a sufficient width for the mid-band to increase the phase margin, let:
C i2 ＝(10-25)C i1 (15)
combined type (12), (13), (14), (15) to obtain: resistor R i1 Resistance R i2 Capacitance C i1 Capacitance C i2 Is a value of (2);
in the step S4, the method for performing voltage loop compensation design includes:
simplifying the closed loop transfer function of the current control loop to obtain a simplified closed loop transfer function A if The method comprises the following steps:
wherein w is p Pole angular frequency for the current control loop; damping coefficient ζ=1;
the load Z(s) of the current control loop consists of an output capacitor and a load, and the transfer function is as follows:
wherein w is z1 Is zero angular frequency, w z1 ＝1/R c C；w p1 For pole angular frequency, w p1 ＝1/[(R c +R)C]；
The control object of the voltage controller consists of a current closed loop transfer function and a load network, and the transfer function A thereof p (s) is:
wherein w is p2 Is the pole angular frequency, w, of the voltage control loop p2 ＝w p /2；
From formula (18), electricityThe control object of the pressure controller consists of three poles and a zero point, and adopts a bipolar point-bipolar zero point as compensation, wherein the bipolar point-bipolar zero point compensation network has a transfer function G v (s) is:
wherein w is vz1 Is the zero angular frequency of the voltage control loop, w vz2 Is the zero angular frequency of the voltage control loop, w vp1 For controlling the angular frequency of the pole of the loop, w vp2 The pole angular frequency of the voltage control loop is set; w (w) vz1 ＜w vz2 ＜w vp1 ＜w vp2 ；K v For voltage control loop DC gain, R v1 To compensate for resistance, R v2 To compensate for resistance, R v3 To compensate for resistance, C v1 To compensate for capacitance, C v2 To compensate for capacitance, C v3 To compensate the capacitance; k (K) v ＝1/(R v1 C v2 )；w vz1 ＝1/(R v2 C v2 )；w vz2 ＝1/(R v1 C v3 )；w vp1 ＝1/(R v3 C v3 )；w vp2 ＝1/(R v2 C v1 )。
2. The loop design method of a double closed loop BUCK converter based on frequency domain analysis according to claim 1, wherein in the step S5, a double closed loop BUCK converter with double loop compensation is added, and the transfer function T thereof v (s) is:
and (3) making:
G v the first zero point of(s) is located at A p At the load pole of(s): w (w) vz1 ＝w p1 ；
G v One pole of the second zero current loop of(s): w (w) vz2 ＝w p2 ；
G v The first pole of(s) cancels the zero caused by the output filter capacitance ESR: w (w) vp1 ＝w z1 ；
G v The second pole of(s) is placed at the switching frequency f s The high frequency attenuation is increased: w (w) vp2 ＝w p ；
Taking the crossing frequency f c ＝f s /4, when f=f c Time |T v (s) |=1, i.e. K v ＝R s f c /(RHf p1 ) From this, it is possible to: resistor R v1 Resistance R v2 Resistance R v3 Capacitance C v1 Capacitance C v2 Capacitance C v3 Is a value of (2).
3. The frequency-domain-analysis-based double-closed-loop BUCK converter is characterized in that the frequency-domain-analysis-based double-closed-loop BUCK converter is designed by adopting the frequency-domain-analysis-based double-closed-loop BUCK converter loop design method according to any one of claims 1-2 on the basis of an average current mode BUCK converter.
4. The frequency domain analysis based dual closed loop BUCK converter according to claim 3, wherein in the frequency domain analysis based dual closed loop BUCK converter:
the main power loop sets the following parameters: input voltage V i =30v, output voltage V o =15v, input current I o =5a, switching frequency f s =100 KHz, inductance l=50uh, filter capacitance c=500 uF, sampling resistance R s =0.1Ω, parasitic resistance R c =0.1Ω, load r=3Ω;
the voltage sampling network is set as follows:
the PWM link is set as follows:
the loop part sets parameters according to the result of loop calculation as follows: for the current inner loop, the compensation resistor R i1 =1kΩ; compensation resistor R i2 =13 kΩ; supplementary capacitor C i1 =120 pF; compensating capacitor C i2 =1.2 nF; for the voltage outer loop, the compensation resistor R v1 =1kΩ; compensation resistor R v2 =390 Ω; compensation resistor R v3 =16kΩ; compensating capacitor C v1 =4nf; compensating capacitor C v2 =40 uF; compensating capacitor C v3 ＝3.12nF。
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