CN110729989A - Hysteresis comparator circuit - Google Patents
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- CN110729989A CN110729989A CN201911300369.3A CN201911300369A CN110729989A CN 110729989 A CN110729989 A CN 110729989A CN 201911300369 A CN201911300369 A CN 201911300369A CN 110729989 A CN110729989 A CN 110729989A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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Abstract
The invention discloses a hysteresis comparator circuit, which comprises a comparator, an inverter, a first impedor, a second impedor, a third impedor, a fourth impedor, a first switch, a second switch, a third switch and a fourth switch, wherein the inverter is connected with the first impedor; the comparator is used for respectively controlling the on/off of the first switch and the second switch according to the difference value of the positive input end and the negative input end of the comparator; and the inverter is used for respectively controlling the on/off of the third switch and the fourth switch according to the output of the comparator. The technical scheme of the invention reduces the cost of the hysteresis comparator circuit.
Description
Technical Field
The invention relates to the field of integrated circuit counting, in particular to a hysteresis comparator circuit.
Background
A comparator is a commonly used circuit block in integrated circuits. At present, more and more application fields adopt differential input, especially for application to sensor bridges and the like, the circuit module needs to be used as a switch in an integrated circuit, and when external application such as pressure, a magnetic field and the like reaches a threshold value, the state of the switch is changed from on to off or from off to on. Due to the instability or jitter of external action, burrs or metastable states can be generated in the adjacent state, so that the reliability is reduced and even the false action is caused for the judgment of subsequent circuits. Most of the solutions for solving the problem in the related art require a plurality of comparators, so that the circuit structure is complex and the cost is increased.
Disclosure of Invention
The main objective of the present invention is to provide a hysteresis comparator circuit, which is to simplify the structure of the hysteresis comparator circuit and reduce the cost of the hysteresis comparator circuit.
In order to achieve the above object, the present invention provides a hysteresis comparator circuit, which includes a comparator, an inverter, a first resistor, a second resistor, a third resistor, a fourth resistor, a first switch, a second switch, a third switch, and a fourth switch;
the hysteresis comparator circuit has a positive differential input terminal, a negative differential input terminal, a reference voltage terminal and an output terminal, the first terminal of the first impedance device is the positive differential input terminal of the hysteresis comparator circuit, the first terminal of the second impedance device is connected to the second terminal of the first switch and the second terminal of the fourth switch, the second terminal of the first impedance device and the second terminal of the second impedance device are connected to the positive input terminal of the comparator, the common terminal of the first switch and the first terminal of the third switch is the reference voltage terminal of the hysteresis comparator circuit, the common terminal of the second terminal of the third comparator and the second terminal of the second comparator is connected to the first terminal of the third impedance device, the common terminal of the first terminal of the second switch and the first terminal of the fourth switch is grounded, the common terminal of the second terminal of the third impedance device and the second terminal of the fourth impedance device is connected to the negative input terminal of the comparator The input end of the fourth impedor is connected, the first end of the fourth impedor is the differential input negative end of the hysteresis comparator circuit, the controlled end of the first switch, the controlled end of the second switch and the input end of the inverter are respectively connected with the output end of the comparator, and the controlled end of the third switch and the controlled end of the fourth switch are respectively connected with the output end of the inverter;
the comparator is used for respectively controlling the on/off of the first switch and the second switch according to the difference value between the positive input end and the negative input end of the comparator;
the inverter is used for respectively controlling the on/off of the third switch and the fourth switch according to the output of the comparator.
Optionally, the comparator is an open-loop comparator based on an uncompensated operational amplifier.
Optionally, the inverter is a TTL not gate inverter.
Optionally, the first impedance device, the second impedance device, the third impedance device, and the fourth impedance device are resistors or switched capacitors.
Optionally, the impedance values of the first, second, third and fourth impeders are the same.
Optionally, the first switch, the second switch, the third switch and the fourth switch are switch tubes.
Optionally, the switch tube is an NMOS tube.
According to the technical scheme, the hysteresis comparator circuit comprises a comparator, an inverter, a plurality of impedors and a plurality of switches, differential signals are input to the input end of the hysteresis comparator circuit, and the output of the comparator is used for controlling the exchange of two reference voltages when the states are changed, so that the hysteresis can be freely adjusted, and the hysteresis center is at the zero point. Compared with the method for realizing the free setting of the hysteresis window value in the related technology, two comparators are needed, so that the circuit structure is complex to set, and the reliability is low; the scheme is suitable for various occasions, reduces the complexity of a circuit structure, reduces the design difficulty, and reduces the cost of the hysteresis comparator circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic diagram of a hysteresis comparator circuit in the prior art;
FIG. 2 is a schematic diagram of a hysteresis comparator circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the hysteresis comparator circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an embodiment of an inverter of a hysteresis comparator circuit according to the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| Z1 | First impedor | S2 | Second switch |
| Z2 | Second impedor | S3 | Third switch |
| Z3 | Third impedor | S4 | The fourth switch |
| Z4 | Fourth impedor | U | Comparator with a comparator circuit |
| S1 | First switch | Q | Inverter with a capacitor having a capacitor element |
| Q1 | A first transistor | Q2 | Second transistor |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, if appearing throughout the text, "and/or" is meant to include three juxtaposed aspects, taking "A and/or B" as an example, including either the A aspect, or the B aspect, or both A and B satisfied aspects. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a hysteresis comparator circuit. In the conventional comparator circuit using differential input, when a sensor bridge or the like is required to function as a switch, when an external force such as pressure, a magnetic field, or the like reaches a threshold value, the state of the switch changes. Specifically, the switch state changes from on to off or from off to on. Due to instability or jitter of external action, a burr or a metastable state can be generated in an adjacent state, great unreliability is generated on judgment of a subsequent circuit, and even false action is caused. To solve this problem, a hysteresis window needs to be added. Further, hysteresis is a function of the input or output level of an input threshold. As shown in fig. 1, the output level changes when the input passes through the threshold, and the input threshold decreases accordingly, so the input must return to the previous threshold before the output of the comparator U changes state again. When the input changes from a negative value to a positive value, the output does not change into a low level, and when the positive turning threshold value VTRP + is reached, the output of the comparator U changes into a high level; once the output is high, the threshold turning point is changed, when the input is reduced towards a negative value, the output is kept not to be high level, and when the negative turning threshold value VTRP-is reached, the output is changed to be low level, so that the noise and the jitter of the input signal can be well inhibited.
However, as the application has more and more degrees of freedom, the value of the hysteresis window also needs to be freely settable, and all external effects are mostly in two directions, so the central value of the hysteresis window should be at zero. At present, most of circuits which need to realize adjustable values of hysteresis windows need two comparators, and the circuit structure is complex, so that the cost is increased.
In order to solve the above problem, in an embodiment of the present invention, as shown in fig. 2, the hysteresis comparator circuit includes a comparator U, an inverter Q, a first impedance Z1, a second impedance Z2, a third impedance Z3, a fourth impedance Z4, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4;
the hysteretic comparator circuit has a positive differential input terminal, a negative differential input terminal, a reference voltage terminal and an output terminal, the first terminal of the first impedance device Z1 is the positive differential input terminal of the hysteretic comparator circuit, the first terminal of the second impedance device Z2 is connected to the second terminal of the first switch S1 and the second terminal of the fourth switch S4, the second terminal of the first impedance device Z1 and the second terminal of the second impedance device Z2 are connected to the positive input terminal of the comparator U, the common terminal of the first switch S1 and the first terminal of the third switch S3 is the reference voltage terminal of the hysteretic comparator circuit, the common terminal of the second terminal of the third comparator U and the second terminal of the second comparator U is connected to the first terminal of the third impedance device Z3, the common terminal of the first terminal of the second switch S2 and the first terminal of the fourth switch S4 is grounded, a common terminal of the second terminal of the third impedance device Z3 and the second terminal of the fourth impedance device Z4 is connected to a negative input terminal of the comparator U, a first terminal of the fourth impedance device Z4 is a negative differential input terminal of a hysteresis comparator circuit, a controlled terminal of the first switch S1, a controlled terminal of the second switch S2 and an input terminal of the inverter Q are respectively connected to an output terminal of the comparator U, and a controlled terminal of the third switch S3 and a controlled terminal of the fourth switch S4 are respectively connected to an output terminal of the inverter Q;
the comparator U is configured to control on/off of the first switch S1 and the second switch S2 according to a difference between a positive input end and a negative input end of the comparator U;
the inverter Q is used for controlling the on/off of the third switch S3 and the fourth switch S4 according to the output of the comparator U.
In this embodiment, the positive terminal of the differential input of the hysteresis comparator circuit is a VIP terminal, the negative terminal of the differential input is a VIN terminal, the reference voltage terminal is a VREF terminal, and the output terminal is an OUT terminal. In this embodiment, as shown in fig. 2, the input terminal of the inverter Q is connected to the output terminal of the comparator U, and the output of the inverter Q controls the third switch S3 and the fourth switch S4. It can be understood that the output terminal of the comparator U is the output of the final result of the hysteresis comparator circuit, and directly controls the on/off of the first switch S1 and the second switch S2; the output of the comparator U controls on/off of the third switch S3 and the fourth switch S4 through the inverter Q. Further, the output initial state of the comparator U is a low level, and when the positive input end of the comparator U is greater than the negative input end, the output of the comparator U is a high level.
In this embodiment, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are turned on when the control level is high; and when the control level is low level, the power is turned off.
Based on the above embodiments, the control signals of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all at a high level, turned on, and at a low level, turned off, and the initial state of the comparator U is at a low level. At this time, the first switch S1 and the second switch S2 are turned off under the control of the output of the comparator U, the third switch S3 and the fourth switch S4 are turned on, and the reference ground voltage is connected to the second resistor Z2, so that the voltage at the positive input terminal of the comparator U is the divided voltage of the first resistor Z1 and the second resistor Z2, that is: 1/2 [ (VIP) ]; the reference voltage VREF is connected to the third resistor Z3, and the voltage at the negative input terminal of the comparator U is the divided voltage of the third resistor Z3 and the fourth resistor Z4, that is: 1/2 ((VIN + VREF)). The difference between the positive input and the negative input of the comparator U is: 1/2 [ ("VIP-VIN-VREF) ], when the differential input voltage (VIP-VIN) is less than the reference voltage VREF, the output of the comparator U maintains low level, when the differential input voltage (VIP-VIN) is greater than or equal to the reference voltage VREF, the output of the comparator U changes to high level, at this time, the first switch S1 and the second switch S2 are turned on under the control of the comparator U outputting high level, and the third switch S3 and the fourth switch S4 are turned off under the control of the comparator U outputting high level, the reference voltage VREF inputted from the reference voltage terminal is connected to the first terminal of the second impedance Z2, and the voltage at the positive input terminal of the comparator U is: 1/2 (VIP + VREF); the reference ground voltage is connected to the first end of the third impedor Z3, and the voltage of the negative input end of the comparator U is: 1/2 (VIN). Then the difference between the positive input end and the negative input end of the comparator U at this time is: 1/2 (VIP-VIN + VREF), the voltage of the differential input continues to increase, and the output keeps high level; when the differential input voltage begins to decrease, the comparator U output remains high until the negative reference voltage VREF. When the differential input voltage decreases to the negative reference voltage VREF, and the voltage of the negative terminal VIN of the differential input is greater than that of the positive terminal VIP of the differential input, the output of the comparator U starts to change to the low level, the first switch S1 and the second switch S2 are turned off under the control of the low level output of the comparator U, the third switch S3 and the fourth switch S4 are turned on under the control of the low level output of the comparator U, the difference between the positive input terminal and the negative input terminal of the comparator U becomes 1/2 × (VIP-VIN-VREF), and the output of the comparator U keeps the low level all the time. Through the mutual cooperation of a comparator U, an inverter Q, a plurality of impedors and a plurality of switches, the hysteresis function of differential input is realized, and a hysteresis schematic diagram shown in figure 3 is formed; while achieving a hysteresis window with a central value at zero.
It should be noted that the impedance values of the first impedance device Z1, the second impedance device Z2, the third impedance device Z3, and the fourth impedance device Z4 are the same. It is understood that the impedance values of the plurality of resistors in the hysteresis comparator circuit are equal.
In addition, with respect to the first resistor Z1, the second resistor Z2, the third resistor Z3 and the fourth resistor Z4, it may be ensured that only the first resistor Z1 and the third resistor Z3 are equal, i.e., Z1= Z3, the first resistor Z2 and the third resistor Z4 are equal, i.e., Z2= Z4, and the first resistor Z1 is not necessarily equal to the second resistor Z2.
According to the technical scheme, the hysteresis comparator circuit comprises a comparator U, an inverter Q, a plurality of impedors and a plurality of switches, differential signals are input to the input end of the hysteresis comparator circuit, and the output of the comparator U is used for controlling the exchange of two reference voltages when the states are changed, so that the hysteresis can be freely adjusted, and the hysteresis center is at a zero point. Compared with the method for realizing the free setting of the hysteresis window value in the related technology, two comparators U are needed, so that the circuit structure is complex to set, and the reliability is low; the scheme is suitable for various occasions, reduces the complexity of a circuit structure, reduces the design difficulty, and reduces the cost of the hysteresis comparator circuit.
In one embodiment, the comparator U is an open-loop comparator U based on an uncompensated operational amplifier. It can be understood that, in the differential input single-ended output, when the positive input end of the comparator U is greater than the negative input end of the comparator U, the comparator U outputs a high level; conversely, when the positive input end of the comparator U is smaller than the negative input end of the comparator U, the comparator U outputs a low level. The characteristic gain and signal speed of the comparator U can be set according to practical applications, and are not limited herein. In this embodiment, the inverter Q, the first switch S1, and the second switch S2 are controlled by the open-loop comparator U.
In one embodiment, the inverter Q is a TTL inverter. Further, as shown in fig. 4, the inverter Q may be composed of a first transistor Q1 and a second transistor Q2; the first transistor Q1 is a P-type transistor, and the second transistor Q2 is an N-type transistor; the gate of the first transistor Q1 and the gate of the second transistor Q2 are connected to each other and are the input of the inverter Q; the drain of the first transistor Q1 and the drain of the second transistor Q2 are connected to each other and are the output terminal of the inverter Q; the source of the first transistor Q1 is connected to a power supply and the source of the second transistor Q2 is connected to ground. In the scheme, the on/off control of the third switch S3 and the fourth switch S4 by the inverter Q is realized through a TTL inverter.
In an embodiment, the first impedance Z1, the second impedance Z2, the third impedance Z3, and the fourth impedance Z4 are resistors or switched capacitors. It is understood that in this embodiment, the impeder may be a resistor; in addition, in order to alleviate the disadvantage of the reduction of the input resistance, the impedance device may also adopt the matching transformation of a capacitor and a switch. Therefore, the arrangement that the hysteresis in the hysteresis comparator circuit can be adjusted is realized, the jitter of the hysteresis comparator circuit is reduced, and the stability of the hysteresis comparator circuit is improved.
In an embodiment, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are switching tubes.
In this embodiment, the switch tube is an NMOS tube. It is understood that the NMOS transistor is an NMOS, and the circuit formed by the NMOS is an NMOS integrated circuit. According to the scheme, the on/off of the NMOS tube is controlled through the comparator U and the phase inverter Q, so that the adjustable control of the hysteresis in the hysteresis comparator circuit is realized.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (7)
1. A hysteresis comparator circuit, characterized in that the hysteresis comparator circuit comprises a comparator, an inverter, a first impedance, a second impedance, a third impedance, a fourth impedance, a first switch, a second switch, a third switch, and a fourth switch;
the hysteresis comparator circuit has a positive differential input terminal, a negative differential input terminal, a reference voltage terminal and an output terminal, the first terminal of the first impedance device is the positive differential input terminal of the hysteresis comparator circuit, the first terminal of the second impedance device is connected to the second terminal of the first switch and the second terminal of the fourth switch, the second terminal of the first impedance device and the second terminal of the second impedance device are connected to the positive input terminal of the comparator, the common terminal of the first switch and the first terminal of the third switch is the reference voltage terminal of the hysteresis comparator circuit, the common terminal of the second terminal of the third comparator and the second terminal of the second comparator is connected to the first terminal of the third impedance device, the common terminal of the first terminal of the second switch and the first terminal of the fourth switch is grounded, the common terminal of the second terminal of the third impedance device and the second terminal of the fourth impedance device is connected to the negative input terminal of the comparator The input end of the fourth impedor is connected, the first end of the fourth impedor is the differential input negative end of the hysteresis comparator circuit, the controlled end of the first switch, the controlled end of the second switch and the input end of the inverter are respectively connected with the output end of the comparator, and the controlled end of the third switch and the controlled end of the fourth switch are respectively connected with the output end of the inverter;
the comparator is used for respectively controlling the on/off of the first switch and the second switch according to the difference value between the positive input end and the negative input end of the comparator;
the inverter is used for respectively controlling the on/off of the third switch and the fourth switch according to the output of the comparator.
2. The hysteretic comparator circuit of claim 1, wherein the comparator is an open-loop comparator based on an uncompensated operational amplifier.
3. The hysteresis comparator circuit of claim 1, wherein the inverter is a TTL not gate inverter.
4. A hysteretic comparator circuit as claimed in claim 1, wherein said first, second, third and fourth impeders are resistors or switched capacitors.
5. A hysteretic comparator circuit as claimed in claim 1, wherein said first, second, third and fourth impedances have the same impedance value.
6. The hysteresis comparator circuit of claim 1, wherein the first switch, the second switch, the third switch, and the fourth switch are switching tubes.
7. The hysteresis comparator circuit of claim 6, wherein the switching transistor is an NMOS transistor.
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| CN201911300369.3A CN110729989B (en) | 2019-12-17 | 2019-12-17 | Hysteresis comparator circuit |
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| CN201911300369.3A CN110729989B (en) | 2019-12-17 | 2019-12-17 | Hysteresis comparator circuit |
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| CN112290791A (en) * | 2020-05-18 | 2021-01-29 | 珠海市杰理科技股份有限公司 | Boost type hysteresis switch converter, control method, chip and electronic equipment |
| CN113708745A (en) * | 2021-08-25 | 2021-11-26 | 南开大学 | Differential input hysteresis comparator with accurately adjustable hysteresis window and working method |
| CN116545421A (en) * | 2023-07-04 | 2023-08-04 | 芯动微电子科技(珠海)有限公司 | Dynamic latching comparator with mismatch calibration function |
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| CN116545421B (en) * | 2023-07-04 | 2023-10-31 | 芯动微电子科技(珠海)有限公司 | Dynamic latching comparator with mismatch calibration function |
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| CN110729989B (en) | 2020-05-05 |
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