CN110729361A - Schottky barrier diode with MoC alloy - Google Patents

Schottky barrier diode with MoC alloy Download PDF

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Publication number
CN110729361A
CN110729361A CN201910955104.0A CN201910955104A CN110729361A CN 110729361 A CN110729361 A CN 110729361A CN 201910955104 A CN201910955104 A CN 201910955104A CN 110729361 A CN110729361 A CN 110729361A
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China
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alloy
moc
schottky
barrier diode
schottky barrier
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王颖
杨朝阳
曹菲
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Hangzhou Dianzi University
HANGZHOU ELECTRONIC SCIENCE AND TECHNOLOGY UNIV
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HANGZHOU ELECTRONIC SCIENCE AND TECHNOLOGY UNIV
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47Schottky barrier electrodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a Schottky barrier diode with MoC alloy, which comprises an N-type 4H-SiC substrate, wherein SiO is sequentially arranged on the front surface of the N-type 4H-SiC substrate from bottom to top2The back of the N-type 4H-SiC substrate is provided with an ohmic contact layer, the Schottky metal layer is MoC alloy, and the mass percentage of C in the MoC alloy is 20-40%; the invention improves the Schottky barrier of the Schottky barrier diode, keeps stable under the condition of high-temperature annealing, and obviously improves the parameter capability.

Description

Schottky barrier diode with MoC alloy
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a Schottky barrier diode with MoC alloy.
Background
Silicon carbide schottky diodes are the most popular of silicon carbide based devices due to their mature fabrication process and large forward current. The schottky contact and electrode selection on the surface of silicon carbide is critical to the important parameters of the schottky diode, so that it is important to form good schottky and ohmic contacts.
Schottky contacts are typically subjected to a Rapid Thermal Annealing (RTA) process that can remove dangling bonds and internal stresses at the metal/SiC contact interface after metal deposition. During the annealing process, the metal reacts with the SiC material. The interface characteristics of the schottky contact have a large influence on the electrical performance of the schottky barrier diode.
Schottky contacts can be formed by contacting various metals such as Ti, Ni, Pt, Mo, etc. with silicon carbide, and recently, studies have been made on the use of molybdenum as a schottky contact metal for silicon carbide. These studies indicate that the schottky contact of Mo metal presents a barrier non-uniformity. The potential barrier is not uniform because the metal and the semiconductor do not form a good contact interface, such as irregular arrangement of atoms, grain-like boundaries, composition of various phases, defects, and the like at the contact interface. When annealing treatment is carried out, metal and semiconductor react at a contact interface, and products generated by the reaction at the interface have direct influence on the electrical characteristics of the Schottky contact. It is therefore believed that the formation of a good schottky contact interface requires assurance that excessive reaction at the metal to silicon carbide interface is avoided.
Disclosure of Invention
It is an object of the present invention to provide a schottky barrier diode that improves the schottky barrier height and remains stable under high temperature annealing by using an alloy to solve the above-mentioned problems of the prior art.
In order to achieve the purpose, the invention provides the following scheme: comprises an N-type 4H-SiC substrate, wherein the front surface of the N-type 4H-SiC substrate is sequentially provided with SiO from bottom to top2The Schottky metal layer is an MoC alloy, wherein the mass percentage of C in the MoC alloy is 20-40%.
Preferably, the thickness of the MoC alloy film in the schottky metal layer is in the range of 60-80 nm.
Preferably, a TiN layer is deposited on a surface of the schottky metal layer.
Preferably, the thickness of the TiN layer is 50 nm.
Preferably, the schottky metal layer is formed by performing radio frequency sputtering under a vacuum condition, wherein the target material is a MoC alloy with 20-40% of C by mass, and nitrogen is filled for protection in the alloy deposition process to form the schottky metal layer.
Preferably, the SiO2The thickness of the passivation layer was 250 nm.
The invention provides a Schottky barrier diode with MoC alloy,
the invention discloses the following technical effects: the Schottky barrier of the Schottky barrier diode is improved, and the Schottky barrier is slightly increased from 0.89eV at low temperature to about 1.2eV at high temperature. And can still keep stable under the high-temperature annealing condition, and the parameter capability is obviously improved. In addition, the MoC alloy target is easy to manufacture, and the material cost and the manufacturing cost are both lower.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic view of a Schottky diode structure according to the present invention;
fig. 2 is a graph of schottky barrier height versus annealing temperature for the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1-2, the present invention provides a portable electronic device havingThe Schottky barrier diode of the MoC alloy comprises an N-type 4H-SiC substrate 2, wherein SiO is sequentially arranged on the front surface of the N-type 4H-SiC substrate 2 from bottom to top2The semiconductor device comprises a passivation layer 3 and a Schottky metal layer 4, wherein an ohmic contact layer 1 is arranged on the back surface of the N-type 4H-SiC substrate 2, the Schottky metal layer 4 is a MoC alloy, and the mass percentage of C in the MoC alloy is 20-40%.
Further, the thickness of the MoC alloy film in the schottky metal layer 4 ranges from 60 nm to 80 nm.
Further, a TiN layer 5 is deposited on the surface of the schottky metal layer 4.
Further, the thickness of the TiN layer 5 was 50 nm.
Further, the forming method of the schottky metal layer 4 is performed in a radio frequency sputtering mode under a vacuum condition, the target material is a MoC alloy with 20-40% of C by mass, and nitrogen gas is filled for protection in the alloy deposition process to form the schottky metal layer 4.
Further, the SiO2The thickness of the passivation layer 3 is 250nm
The manufacturing method of the Schottky barrier diode of the MoC alloy comprises the following steps:
step 1, selecting a 4H-SiC substrate 2 to carry out standard RCA cleaning.
1a) Selecting the doping concentration to be 1 × 1018cm3An N-type 4H-SiC substrate 2;
1b) the use ratio is 1: 1: 5, cleaning the selected N-type 4H-SiC substrate 2 by using a mixed solution of hydrochloric acid, hydrogen peroxide and deionized water for 5 minutes to remove impurities such as metal oxides, hydroxides and active metals on the surface of the substrate;
1c) placing the cleaned substrate in a condition that the proportion is 1: 10, soaking the substrate in a mixed solution of hydrogen fluoride and deionized water for 30 seconds to remove natural oxides on the surface of the substrate;
1d) the cleaned substrate was blow-dried with nitrogen.
And 2, growing an oxide layer.
2a) The cleaned N-type 4H-SiC substrate 2 was immediately placed in a heating furnace, a 50nm oxide layer was grown on the epitaxial layer at a temperature of 1150 ℃ in an oxygen atmosphere, and then annealed at 1100 ℃ for 1 hour in a nitrogen atmosphere.
2b) Then growing SiO by PECVD method2And the passivation layer 3 is 250nm thick and is densified in an oxidation furnace for 1 hour after the passivation layer is grown.
The process conditions for growing the passivation layer 3 of Si02 are as follows:
the growth temperature is 300 ℃, and the growth time is 300 seconds;
the reaction gas in the growth process is SiH4And C3H8In which is SiH4And C3H8The ratio of (A) to (B) is 5: 1;
the protective gas is hydrogen;
the pressure in the reaction chamber was 500 mT.
And 3, preparing ohmic contact on the back surface of the N-type 4H-SiC substrate processed in the step 1-2.
3a) Sputtering Ni metal on the back surface of the cleaned N-type 4H-SiC substrate 2 by a direct current sputtering method, wherein the thickness of the metal Ni is 150 nm;
3b) after the metal is evaporated, the device is placed in an annealing furnace in a nitrogen atmosphere for rapid annealing for 2min, the annealing temperature is 1000 ℃, and an ohmic contact layer 1 is formed.
And 4, photoetching the middle passivation layer to form a Schottky window, realizing effective regulation of a Schottky contact potential barrier between the MoC alloy and the silicon carbide, and improving the phenomenon of nonuniform potential barrier of Mo metal in Schottky contact.
4a) Coating photoresist with the thickness of 0.2um on the surface of the passivation layer, developing, flushing in ultrapure water for 2min, and flushing in a nitrogen atmosphere;
4b) using photoresist as barrier layer, etching off SiO in the middle by reactive ion etching method2A passivation layer, thereby forming a schottky window;
the process conditions of the reactive ion etching are as follows:
the reaction gas being CF4And O2
The pressure in the reaction chamber is 5 mT;
the power of the reaction cavity is 50W;
4c) and after etching, the device is organically cleaned by using stripping liquid, and the residual photoresist is removed.
And 5, preparing Schottky contact and field plate terminals.
5a) Coating photoresist on the surface of the passivation layer and the surface of the Schottky window and developing, forming a pattern region of a field plate terminal on the surface of the passivation layer, and forming a pattern region of Schottky contact on the surface of the Schottky window;
5b) after a pattern area is formed, the device is placed in ultrapure water to be flushed for 2min and flushed and dried in a nitrogen atmosphere;
5c) depositing MoC alloy in the formed pattern area by using radio frequency sputtering, and forming more stable Mo by designing mass percent of C2And C, wherein the thickness of the MoC alloy is 60-80nm, and a Schottky metal layer 4 is formed on the Schottky window. And depositing a TiN layer 5 on the alloy layer by direct current sputtering, wherein the thickness of the TiN layer 5 is 50nm so as to prevent the electrode layer from being oxidized in the annealing process.
5d) After the field plate terminal is formed to contact with the Schottky, the device is subjected to organic cleaning by using a stripping solution to remove the residual photoresist, and the residual stripping solution is cleaned by using ethanol and acetone.
Step 6, annealing the Schottky metal
Annealing is carried out in a rapid annealing furnace, the thermal annealing temperature is 600-1000 ℃ in the nitrogen atmosphere, and the annealing time is 1-2min, so that Mo and C are fully reacted, and the potential barrier nonuniformity of a Schottky interface is further improved.
Thus, the schottky barrier diode with MoC alloy is manufactured, and the structure is shown in fig. 1.
According to the invention, the Schottky barrier diode is formed through the deposition of the MoC alloy, so that the effective regulation of the Schottky contact barrier between the MoC alloy and the silicon carbide is realized, and the phenomenon of nonuniform barrier of Mo metal in Schottky contact is improved. The schottky barrier height variation at different temperature anneals is shown in fig. 2. The small increase in barrier height from 0.89eV at low temperature to around 1.2eV at high temperature indicates stability below 1000 c.
In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, are merely for convenience of description of the present invention, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
The above-described embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements of the technical solutions of the present invention can be made by those skilled in the art without departing from the spirit of the present invention, and the technical solutions of the present invention are within the scope of the present invention defined by the claims.

Claims (6)

1. A schottky barrier diode having a MoC alloy, comprising: comprises an N-type 4H-SiC substrate (2), wherein the front surface of the N-type 4H-SiC substrate (2) is sequentially provided with SiO from bottom to top2The semiconductor device comprises a passivation layer (3) and a Schottky metal layer (4), wherein an ohmic contact layer (1) is arranged on the back surface of the N-type 4H-SiC substrate (2), the Schottky metal layer (4) is an MoC alloy, and the mass percentage of C in the MoC alloy is 20-40%.
2. The schottky barrier diode with MoC alloy of claim 1, wherein: the thickness of the MoC alloy film in the Schottky metal layer (4) ranges from 60 nm to 80 nm.
3. The schottky barrier diode with MoC alloy of claim 1, wherein: and a TiN layer (5) is deposited on the surface of the Schottky metal layer (4).
4. The schottky barrier diode with MoC alloy of claim 3, wherein: the thickness of the TiN layer (5) is 50 nm.
5. The schottky barrier diode with MoC alloy of claim 1, wherein: the forming method of the Schottky metal layer (4) comprises the steps of performing radio frequency sputtering under a vacuum condition, wherein a target material is MoC alloy with the mass percent of C being 20-40%, and nitrogen gas is filled for protection in the alloy deposition process to form the Schottky metal layer (4).
6. The schottky barrier diode with MoC alloy of claim 1, wherein: the SiO2The thickness of the passivation layer (3) is 250 nm.
CN201910955104.0A 2019-10-09 2019-10-09 Schottky barrier diode with MoC alloy Pending CN110729361A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4982243A (en) * 1988-03-28 1991-01-01 Sumitomo Electric Industries, Ltd. Schottky contact
JP2002076372A (en) * 2000-09-01 2002-03-15 Shindengen Electric Mfg Co Ltd Schottky junction semiconductor device
CN104303269A (en) * 2012-04-06 2015-01-21 富士电机株式会社 Method for manufacturing silicon carbide semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4982243A (en) * 1988-03-28 1991-01-01 Sumitomo Electric Industries, Ltd. Schottky contact
JP2002076372A (en) * 2000-09-01 2002-03-15 Shindengen Electric Mfg Co Ltd Schottky junction semiconductor device
CN104303269A (en) * 2012-04-06 2015-01-21 富士电机株式会社 Method for manufacturing silicon carbide semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TOMOYUKI SUZUKI等: ""Laminated Mo/C Electrodes for 4H–SiC Schottky Barrier Diodes With Ideal Interface Characteristics"", 《IEEE ELECTRON DEVICE LETTERS》 *

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Application publication date: 20200124