CN110729179A - Smart card chip processing method and smart card chip - Google Patents
Smart card chip processing method and smart card chip Download PDFInfo
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- CN110729179A CN110729179A CN201911042325.5A CN201911042325A CN110729179A CN 110729179 A CN110729179 A CN 110729179A CN 201911042325 A CN201911042325 A CN 201911042325A CN 110729179 A CN110729179 A CN 110729179A
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- 238000003672 processing method Methods 0.000 title claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 116
- 238000000034 method Methods 0.000 claims abstract description 59
- 238000002161 passivation Methods 0.000 claims abstract description 52
- 230000008569 process Effects 0.000 claims abstract description 43
- 239000004642 Polyimide Substances 0.000 claims abstract description 37
- 229920001721 polyimide Polymers 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 81
- 235000012239 silicon dioxide Nutrition 0.000 claims description 40
- 239000000377 silicon dioxide Substances 0.000 claims description 40
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 5
- 238000001723 curing Methods 0.000 claims description 4
- 238000003848 UV Light-Curing Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000012360 testing method Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application discloses a processing method of an intelligent card chip and the intelligent card chip, and belongs to the technical field of chip manufacturing. The method comprises the following steps: providing a smart card chip having at least one metal top layer; depositing a passivation layer on the at least one metal top layer; carrying out planarization treatment on the passivation layer; removing the passivation layer above the target metal top layer in the at least one metal top layer through an etching process to expose the target metal top layer; coating a polyimide layer on the passivation layer and the target metal top layer; and removing the polyimide layer above the target metal top layer to form a pin through hole, so that the target metal top layer is exposed outside through the pin through hole. This application is through behind the metal top layer deposit passivation layer, through carrying out planarization to the passivation layer to make the surface of smart card chip become flat, can receive the atress comparatively uniformly when pressure, simultaneously, through set up the polyimide layer on the passivation layer, can further increase cushioning effect and mechanical properties, improved the compressive property of smart card chip.
Description
Technical Field
The application relates to the technical field of chip manufacturing, in particular to a processing method of an intelligent card chip and the intelligent card chip.
Background
Smart cards, such as electronic passports, financial (e.g., debit, credit, etc.) cards, and bus cards, are provided with smart card chips that require pressure testing during their manufacture to measure their pressure resistance. For example, a point pressure test is generally used for a smart card chip applied to an electronic passport, and three rounds of pressure tests are generally used for a smart card chip applied to a financial card.
With the thickness of the smart card chip becoming thinner and thinner, the smart card chip manufactured by the related art is difficult to pass the pressure test, and the pressure resistance is poorer.
Disclosure of Invention
The application provides a processing method of an intelligent card chip and the intelligent card chip, which can solve the problem of poor compression resistance of the intelligent card chip provided in the related technology.
In one aspect, the present application provides a method for processing a smart card chip, where the method includes:
providing a smart card chip having at least one metal top layer;
depositing a passivation layer on the at least one metal top layer;
carrying out planarization treatment on the passivation layer;
removing the passivation layer above the target metal top layer in the at least one metal top layer through an etching process to expose the target metal top layer;
coating a polyimide layer on the passivation layer and the target metal top layer;
and removing the polyimide layer above the target metal top layer to form a pin through hole, so that the target metal top layer is exposed outside through the pin through hole.
Optionally, the passivation layer comprises a silicon dioxide layer, and the depositing the passivation layer on the at least one metal top layer comprises:
depositing the silicon dioxide layer on the at least one metal top layer by a High Density Plasma Chemical Vapor Deposition (HDPCVD) process, and/or a Plasma Enhanced (PECVD) process.
Optionally, the planarizing the passivation layer includes:
and carrying out the planarization treatment on the silicon dioxide layer by a Chemical Mechanical Polishing (CMP) process.
Optionally, the passivation layer further includes a silicon nitride layer or a silicon oxynitride layer on the silicon dioxide layer;
after the polishing treatment is performed on the silicon dioxide layer by the Chemical Mechanical Polishing (CMP) process, the method further comprises the following steps:
depositing the silicon nitride layer or the silicon oxynitride layer on the silicon dioxide layer by the PECVD process;
the removing the passivation layer above the target metal top layer in the at least one metal top layer through an etching process includes:
and removing the silicon dioxide layer and the silicon nitride layer or the silicon oxynitride layer above the target metal top layer in the at least one metal top layer by the etching process.
Optionally, the removing the silicon dioxide layer and the silicon nitride layer or the silicon oxynitride layer above the target metal top layer in the at least one metal top layer by the etching process includes:
coating photoresist on the silicon nitride layer or the silicon oxynitride layer;
exposing the photoresist above the target metal top layer;
removing the photoresist above the target metal top layer through a developing solution to expose the silicon nitride layer or the silicon oxynitride layer above the target metal top layer;
removing the silicon nitride layer or the silicon oxynitride layer and the silicon dioxide layer above the target metal top layer through the etching process;
and removing the photoresist on the silicon nitride layer or the silicon oxynitride layer.
Optionally, the removing the polyimide layer above the target metal top layer includes:
exposing the polyimide layer above the target metal top layer;
and removing the polyimide layer above the target metal top layer by using a developing solution.
Optionally, after the exposing the polyimide layer on the top layer of the target metal, the method further includes:
and curing the polyimide layer by an ultraviolet UV curing process.
In another aspect, the present application provides a smart card chip comprising a smart card chip block, at least one metal top layer disposed on the smart card chip block, a passivation layer disposed on the metal top layer, and a polyimide layer disposed on the passivation layer;
the polyimide layer includes a pin via for exposing a target metal top layer of the at least one metal top layer.
Optionally, the passivation layer includes a silicon dioxide layer and a silicon nitride layer or a silicon oxynitride layer.
Optionally, the silicon dioxide layer is a silicon dioxide layer polished by a CMP process after deposition.
The technical scheme at least comprises the following advantages:
through after the passivation layer is deposited on the metal top layer, the passivation layer is flattened, so that the surface of the intelligent card chip becomes flat, the surface stress of the chip is relatively uniform, the polyimide layer can be covered on the flattened passivation layer and the metal top layer in a coating mode, the flattening and buffer layers can be further increased, the stress can be uniformly applied when the stress is applied, the intelligent card chip can pass through a pressure test, and the pressure resistance of the intelligent card chip is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a pressure testing method of a smart card chip;
FIG. 2 is a flow chart of a method of processing a smart card chip provided in an exemplary embodiment of the present application;
fig. 3 to 9 are schematic diagrams illustrating a process of manufacturing a smart card chip according to an exemplary embodiment of the present application;
FIG. 10 is a cross-sectional view of a smart card chip provided in an exemplary embodiment of the present application;
fig. 11 is a schematic diagram of a pressure test of the smart card chip provided in the present application and the smart card chip provided in the related art.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 shows a schematic diagram of a pressure testing method of a smart card chip. As shown in fig. 1, the smart card chip 110 is placed on the base 120, and the pressure test probe 130 applies pressure on the smart card chip 110 to perform a pressure test on the smart card chip 110.
Because the existing smart card chip is generally small in thickness (generally can reach less than 150 micrometers, even less than 100 micrometers), and meanwhile, the surface of the smart card chip is uneven, the stress is not uniform when the chip is subjected to a pressure test, so that the smart card chip is difficult to pass the pressure test, and the pressure resistance of the smart card chip is poor.
Fig. 2 is a flowchart illustrating a method for processing a smart card chip according to an exemplary embodiment of the present application, where the method includes:
The smart card chip may be a wafer of smart card chips including a plurality of smart card chip blocks (Die), or may be one smart card chip block. At least one metal top layer is prepared on the smart card chip, and the metal top layer can be an electric connection port of the smart card chip. Illustratively, the smart card chip includes a substrate and a smart card chip pattern on the substrate, wherein the smart card chip pattern includes at least one metal top layer.
A passivation layer is deposited 202 on the at least one metal top layer.
Wherein the passivation layer comprises silicon dioxide (SiO)2) And (3) a layer. Illustratively, as shown in fig. 3, at least one metal top layer is disposed on the smart card chip 300 (the metal top layer 311 and the metal top layer 312 are illustrated in fig. 3, and one or more than two metal top layers may be disposed in actual production), and the silicon oxide layer 301 may be deposited on the side of the smart card chip 300 where the metal top layer is disposed.
Alternatively, a silicon dioxide layer may be deposited on the at least one metal top layer by a High Density Plasma Chemical Vapor Deposition (HDPCVD) process; alternatively, a silicon dioxide layer may be deposited on the at least one metal top layer by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process; alternatively, a silicon dioxide layer may be deposited on the at least one metal top layer by a HDPCVD process and a PECVD process, respectively.
Illustratively, the silicon dioxide layer may be planarized by Polishing the silicon dioxide layer using a Chemical Mechanical Polishing (CMP) process. As shown in fig. 3, the deposited silicon dioxide layer 301 is not flat, especially the silicon dioxide layer above the metal top layer is formed with a protrusion; as shown in fig. 4, after the silicon dioxide layer 301 is polished by the CMP process, the surface of the silicon dioxide layer 301 becomes flat.
Optionally, the passivation layer further comprises silicon nitride (Si)3N4) A layer or a silicon oxynitride (SiON) layer. And after the silicon dioxide is ground through the CMP process, depositing a silicon oxynitride layer on the silicon dioxide layer through a PECVD process.
Illustratively, as shown in fig. 5, a silicon nitride layer or a silicon oxynitride layer 302 may be deposited on the silicon dioxide layer 301 by a PECVD process.
And 204, removing the passivation layer above the target metal top layer in the at least one metal top layer through an etching process, so that the target metal top layer is exposed outside.
Wherein, the target metal top layer is a metal top layer which needs to be exposed to the outside and is electrically connected with other electronic components or devices. Illustratively, the passivation layer over the target one of the at least one metal top layer is removed by an etching process, including but not limited to:
coating photoresist on the passivation layer; exposing the photoresist above the target metal top layer; removing the photoresist above the target metal top layer through a developing solution to expose the passivation layer above the target metal top layer; removing the passivation layer exposed above the target metal top layer through an etching process; and removing the photoresist on the passivation layer.
For example, taking the metal top layer 311 as a target metal top layer, as shown in fig. 6, coating a photoresist 303 on the silicon nitride layer 302, shielding the photoresist except for the photoresist above the target metal top layer 311 by a first mask (not shown in fig. 6), exposing the photoresist above the target metal top layer 311 by Ultraviolet (UV), removing the photoresist above the target metal top layer 311 by a developing solution, exposing the silicon nitride layer or the silicon nitride layer 302 above the target metal top layer 311, and removing a passivation layer above the exposed target metal top layer 311 by an etching process; as shown in fig. 7, the photoresist on the silicon nitride layer or silicon nitride layer 302 is removed.
Illustratively, as shown in fig. 8, a Polyimide layer (Polyimide)304 is coated on the silicon nitride layer 302 and on the target metal top layer 311.
In step 206, the polyimide layer above the target metal top layer is removed to form a pin via, so that the target metal top layer is exposed through the pin via.
Exemplary, removing the polyimide layer above the target metal top layer to form the pin via includes, but is not limited to:
exposing the polyimide layer above the target metal top layer; and removing the polyimide layer above the target metal top layer by using a developing solution.
Illustratively, as shown in fig. 9, the polyimide layer except for the region above the target metal top layer 311 may be masked by a first mask or another mask (not shown in fig. 8), the polyimide layer above the target metal top layer 311 may be exposed by irradiating UV light, and the polyimide layer above the target metal top layer 311 may be removed by a developing solution to form a pin via hole (PAD) 305. Optionally, after exposing the polyimide layer on the top layer of the target metal, a Curing process of the polyimide layer by a UV Curing (Curing) process is further included.
When the smart card chip comprises more than two target metal top layers, the pin through holes can be formed above the more than two target metal top layers by the method. When the smart card chip is a wafer including a plurality of smart card chip blocks, after the above steps are completed, the wafer may be cut to obtain a chip including one smart card chip block.
To sum up, in this application embodiment, through behind the metal top layer deposit passivation layer, through carrying out the planarization to the passivation layer to make the surface of smart card chip become flat, can receive the atress comparatively evenly when pressure, and then cover the polyimide layer through the mode of coating on the passivation layer of planarization and the metal top layer, further increased shock-absorbing capacity and mechanical properties, thereby can make the smart card chip pass through pressure test, improved the compressive property of smart card chip.
FIG. 10 illustrates a side view of a smart card chip provided in an exemplary embodiment of the present application. As shown in fig. 10, a smart card chip 1000 provided by the embodiment of the present application includes a smart card chip block 1010, at least one metal top layer (metal top layers 1021 and 1022 are exemplarily illustrated in fig. 10) disposed on the smart card chip block 1010, a passivation layer 1030 disposed on the metal top layer, and a polyimide layer 1040 disposed on the passivation layer 1030. The polyimide layer 1040 includes a pin via 1041 for exposing the target metal top layer 1021. The smart card chip 1000 in the embodiment of the present application can be processed by the processing method in the embodiment of fig. 2.
Optionally, the passivation layer 1030 includes a silicon dioxide layer 1031, a silicon nitride layer, or a silicon oxynitride layer 1032; the silicon dioxide layer 1031 is a silicon dioxide layer that has been polished by a CMP process after deposition.
Fig. 11 is a schematic diagram illustrating a stress test of the smart card chip provided in the present application and the smart card chip provided in the related art. As shown in fig. 11, the smart card chip provided in the present application ("the present invention" in fig. 11) has better pressure resistance in the spot pressure test and the three-round pressure test than the smart card chip provided in the related art ("the general process" in fig. 11).
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. A processing method of a smart card chip is characterized by comprising the following steps:
providing a smart card chip having at least one metal top layer;
depositing a passivation layer on the at least one metal top layer;
carrying out planarization treatment on the passivation layer;
removing the passivation layer above the target metal top layer in the at least one metal top layer through an etching process to expose the target metal top layer;
coating a polyimide layer on the passivation layer and the target metal top layer;
and removing the polyimide layer above the target metal top layer to form a pin through hole, so that the target metal top layer is exposed outside through the pin through hole.
2. The method of claim 1, wherein the passivation layer comprises a silicon dioxide layer, and wherein depositing the passivation layer on the at least one top metal layer comprises:
depositing the silicon dioxide layer on the at least one metal top layer by a High Density Plasma Chemical Vapor Deposition (HDPCVD) process, and/or a Plasma Enhanced (PECVD) process.
3. The method of claim 2, wherein the planarizing the passivation layer comprises:
and carrying out the planarization treatment on the silicon dioxide layer by a Chemical Mechanical Polishing (CMP) process.
4. The method of claim 3, wherein the passivation layer further comprises a silicon nitride layer or a silicon oxynitride layer on the silicon dioxide layer;
after the polishing treatment is performed on the silicon dioxide layer by the Chemical Mechanical Polishing (CMP) process, the method further comprises the following steps:
depositing the silicon nitride layer or the silicon oxynitride layer on the silicon dioxide layer by the PECVD process;
the removing the passivation layer above the target metal top layer in the at least one metal top layer through an etching process includes:
and removing the silicon dioxide layer and the silicon nitride layer or the silicon oxynitride layer above the target metal top layer in the at least one metal top layer by the etching process.
5. The method of claim 4, wherein the removing the silicon dioxide layer and the silicon nitride layer or silicon oxynitride layer over a target one of the at least one metal top layer by the etching process comprises:
coating photoresist on the silicon nitride layer or the silicon oxynitride layer;
exposing the photoresist above the target metal top layer;
removing the photoresist above the target metal top layer through a developing solution to expose the silicon nitride layer or the silicon oxynitride layer above the target metal top layer;
removing the silicon nitride layer or the silicon oxynitride layer and the silicon dioxide layer above the target metal top layer through the etching process;
and removing the photoresist on the silicon nitride layer or the silicon oxynitride layer.
6. The method of any one of claims 1 to 5, wherein said removing the polyimide layer over the top layer of the target metal comprises:
exposing the polyimide layer above the target metal top layer;
and removing the polyimide layer above the target metal top layer by using a developing solution.
7. The method of claim 6, wherein after exposing the polyimide layer over the top layer of the target metal, further comprising:
and curing the polyimide layer by an ultraviolet UV curing process.
8. A smart card chip, comprising a smart card chip block, at least one metal top layer disposed on the smart card chip block, a passivation layer disposed on the metal top layer, and a polyimide layer disposed on the passivation layer;
the polyimide layer includes a pin via for exposing a target metal top layer of the at least one metal top layer.
9. The smart card chip of claim 8, wherein the passivation layer comprises a silicon dioxide layer and a silicon nitride layer or a silicon oxynitride layer.
10. The smart card chip of claim 9, wherein the silicon dioxide layer is a silicon dioxide layer that has been abrasive treated by a CMP process after deposition.
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| CN201911042325.5A CN110729179A (en) | 2019-10-30 | 2019-10-30 | Smart card chip processing method and smart card chip |
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| CN201911042325.5A CN110729179A (en) | 2019-10-30 | 2019-10-30 | Smart card chip processing method and smart card chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115632003A (en) * | 2022-12-22 | 2023-01-20 | 紫光同芯微电子有限公司 | Chip packaging method and device, readable medium and electronic equipment |
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| US20030013291A1 (en) * | 2001-07-12 | 2003-01-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Passivation and planarization process for flip chip packages |
| US20040195595A1 (en) * | 2003-04-02 | 2004-10-07 | Rhodes Howard E | Passivation planarization |
| CN102148203A (en) * | 2010-02-08 | 2011-08-10 | 台湾积体电路制造股份有限公司 | Semiconductor chip and method for forming conductive pillar |
| CN104934316A (en) * | 2014-03-18 | 2015-09-23 | 上海华虹宏力半导体制造有限公司 | Passivation layer etching method for settling photoresist insufficiency |
| CN105097492A (en) * | 2014-05-16 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Chip manufacture process and chip |
| US20170162540A1 (en) * | 2015-12-03 | 2017-06-08 | Mediatek Inc. | Wafer-level chip-scale package with redistribution layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115632003A (en) * | 2022-12-22 | 2023-01-20 | 紫光同芯微电子有限公司 | Chip packaging method and device, readable medium and electronic equipment |
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