CN110708067A

CN110708067A - Double-sequencing interval selection capacitance correction method applied to analog-to-digital converter

Info

Publication number: CN110708067A
Application number: CN201910998717.2A
Authority: CN
Inventors: 樊华; 王琛; 李博川; 冯全源; 冯浪; 刁小芃; 岑远军
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2019-10-21
Filing date: 2019-10-21
Publication date: 2020-01-17

Abstract

The invention discloses a double-sequencing interval selection capacitance correction method applied to an analog-to-digital converter, relates to the field of microelectronics and solid electronics, and particularly relates to a capacitance setting method in a mixed capacitance-resistance successive approximation analog-to-digital converter in the field. The invention adopts unit capacitors to form a positive and negative capacitor array of the mixed capacitor resistance type successive approximation analog-to-digital converter, and selects the Most Significant Bit (MSB) of each level of effective bits, the Least Significant Bit (LSB) of the second most significant bit (MSB-1) … … and the Dummy capacitors which form the analog-to-digital converter at intervals after two times of sequencing. Compared with the traditional SAR ADC, the static performance and the dynamic performance are both obviously improved; compared with the traditional analog and digital correction algorithms, the adjustment and correction method provided by the invention only needs to perform sequencing twice, is simpler to operate, and greatly saves the area and the power consumption.

Description

Double-sequencing interval selection capacitance correction method applied to analog-to-digital converter

Technical Field

The invention relates to the field of microelectronics and solid electronics, in particular to a capacitor setting method in a mixed capacitor resistance type successive approximation analog-digital converter in the field.

Background

In the intelligent era, digital signals are involved in many aspects of life. Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) are bridges connecting Digital signals and Analog signals, and are important bases of the Digital world. The successive approximation analog-to-digital converter (SAR ADC) has the advantages of high precision, low power consumption, small size and the like, has medium speed, and is widely applied to embedded low-power-consumption applications such as implantable medical equipment, intelligent sensors and the like.

Switching power supply high frequency noise, analog input signal noise, power supply output instability, component mismatch, etc., will affect the accuracy of the ADC. In the design of the SAR ADC, the comprehensive consideration of performance indexes such as accuracy, speed, power consumption, area, etc., and the selection of ADC structure, correction algorithm, etc. are problems that the designer needs to face. The document [ j.shen et al, "a 16-bit16MS/s SAR ADC with on-chip calibration in 55nm CMOS,"2017Symposium on vlsi calibration, Kyoto,2017, pp.c282-C283 ] proposes a calibration algorithm with low input capacitance and high efficiency on-chip foreground, using a reference switch independent of the signal of the storage capacitor to increase speed and reduce area, with a significant improvement in performance after correction, but an increase in overall power consumption. Documents [ w.tung and s.huang, "An Energy-efficiency 11-bit 10-MS/s SAR ADC with a montonic Switching Split Capacitor Array,"2018IEEE International Symposium on Circuits and Systems (ISCAS), Florence,2018, pp.1-5 ] propose An asynchronous differential SAR ADC, using a Monotonic Switching program and a separate Capacitor structure at the same time, achieving the purpose of reducing area and Energy consumption, and propose a digital calibration method, minimizing the influence caused by Capacitor mismatch and bridge-type parasitic capacitors, but the method is more complicated, increases the complexity of layout design, and the improvement of linearity and dynamic parameters is not obvious. Patent 201910772581.3 proposes a capacitance correction method with median selection in 2019, which effectively improves the static performance and dynamic performance of an ADC by multiple sorting and multiple median selection. However, up to 6 capacitor orderings and 5 capacitor combinations greatly increase the power consumption of the ADC and reduce the conversion rate of the ADC.

Disclosure of Invention

The invention designs a double-sequencing interval selection capacitor correction method applied to a successive approximation analog-to-digital converter aiming at the defects of poor performance, high power consumption, complex capacitor layout design, large volume and the like in the prior art.

The technical scheme of the invention is a double-sequencing interval selection capacitance correction method applied to an analog-to-digital converter, which comprises the following steps:

step 1: the unit capacitors are adopted to form a positive capacitor array and a negative capacitor array in the mixed capacitor resistance type successive approximation analog-to-digital converter, the positive capacitor array and the negative capacitor array respectively comprise n unit capacitors, and the unit capacitors are labeled as follows: c_u1、C_u2、C_u3……C_u(n-1)、C_un；

Step 2: carrying out first sequencing: unit capacitance C_uiAre arranged in ascending order according to the capacitance value and are numbered as

Two unit capacitors to be located at the middle position

Respectively as the LSB and Dummy capacitors of the converter; then the rest capacitors are combined end to obtain n/2-1 new capacitor groups C_i：

And

combination is C₁、

And

combination is C₂、

And

combination is C₃……

And

combination is C_(n/2-1)；

And step 3: and (5) carrying out second sequencing: arranging n/2-1 new capacitor groups in ascending order according to the capacitance values, and numbering the capacitor groups in sequence as follows:

and 4, step 4: for the sorted capacitor banks, from the first capacitor bankStarting interval selection, and selecting current n/4 capacitor groups as the most significant bit MSB of the converter;

and 5: for the remaining capacitor banks, from the first capacitor bank

Starting interval selection, and selecting current n/8 capacitor groups as the second most significant bit MSB-1 of the converter;

step 6: repeating the step 5, and selecting the capacitors at intervals from the first capacitor in the rest capacitor groups, wherein each time the capacitors are selectedHalving the number of banks as the remaining significant bits of the converter: MSB-2, MSB-3 … …, until one capacitor bank remains

As the second least significant bit LSB +1 of the converter;

and 7: and performing analog-to-digital conversion by using the obtained MSB, MSB-1, MSB-2, MSB-3 … … LSB and dummy capacitors as a capacitor array of the successive approximation analog-to-digital converter.

Compared with the traditional SAR ADC, the double-sequencing interval selection capacitance correction method provided by the invention has the advantages that both the static performance and the dynamic performance are obviously improved; compared with the traditional analog and digital correction algorithms, the adjustment and correction method provided by the invention only needs to perform sequencing twice, is simpler to operate, and greatly saves the area and the power consumption.

Drawings

Fig. 1 is a schematic diagram of a hybrid capacitance-resistance SAR ADC.

Fig. 2 is a schematic diagram of double-sequencing interval selection according to the present invention.

FIG. 3 is a schematic diagram of a two-step comparison of unit capacitors Cu1 and Cu 2; (a) the upper electrode plates of all the unit capacitors in the positive and negative capacitor arrays are connected with the VCM, the lower electrode plate of the Cu1 in the positive capacitor array is connected with the VREFP, the lower electrode plates of other unit capacitors are connected with the VREFN, the lower electrode plate of the Cu1 in the negative capacitor array is connected with the VREFN, and the lower electrode plates of other unit capacitors are connected with the VREFP; (b) and the upper electrode plates of all the unit capacitors in the positive and negative capacitor arrays are disconnected and connected with the VCM, the lower electrode plate of the Cu2 in the positive capacitor array is connected with the VREFP, the lower electrode plates of other unit capacitors in the positive capacitor array are connected with the VREFN, the lower electrode plate of the Cu2 in the negative capacitor array is connected with the VREFN, and the lower electrode plates of other unit capacitors in the negative capacitor array are connected with the VREFP.

Fig. 4 is a simulation result of static performance of an 18-bit SAR ADC.

Fig. 5 is a simulation result of static performance of a 16-bit SAR ADC.

Fig. 6 is a simulation result of static performance of a 14-bit SAR ADC.

Fig. 7 is a simulation result of the dynamic performance of the 18-bit SAR ADC.

Fig. 8 is a simulation result of the dynamic performance of the 16-bit SAR ADC.

Fig. 9 is a simulation result of the dynamic performance of the 14-bit SAR ADC.

Detailed Description

The invention provides a double-sequencing interval selection capacitance correction method, which is used for detailing a traditional binary array by taking an 18-bit mixed capacitance resistance type successive approximation analog-to-digital converter consisting of a high 8-bit capacitance DAC and a low 10-bit resistance DAC as an example.

The structure of the M + N mixed capacitor-resistor successive approximation analog-to-digital converter with the high M-bit capacitor DAC and the low N-bit resistor DAC is shown in fig. 1. If M is 8 and N is 10, it represents an 18-bit SAR ADC composed of a high-8-bit capacitor DAC and a low-10-bit resistor DAC. Each of the 8-bit high positive and negative capacitor arrays includes 128 unit capacitors, and the 128 unit capacitors are labeled as: c _ u1, C _ u2, C _ u3 … …, C _ u127 and C _ u128 (shown as (1) in FIG. 2). The capacitance values of the 128 unit capacitors should be equal, but in practical cases, due to the influence of various factors, the 128 unit capacitors are not always completely equal but follow a normal distribution.

The first ascending sort is performed on the 128 unit capacitors: the comparison of the capacitance and the capacitance is accomplished by a capacitance comparison method (as shown in FIG. 3) similar to the documents [ H. -. Lee, D.A.Hodges and P.R.Gray, "A Self-calibration 15Bit CMOS A/D Converter" "IEEE Journal of Solid-State Circuits,1984,19(6):813-819], and the 128 unit capacitances are sorted in ascending order and are sequentially labeled as follows: c _ u1^ C _ u2^ C _ u3^ … … C _ u127^ C _ u128^ C _ u1^ C _ u2^ C _ u3^ C _ … … ^ C _ u127^ C _ u128^ C _ u (shown in FIG. 2 (2)). Taking two unit capacitors C _ u64^ and C _ u65^ located at the middle position as the Least Significant Bit (LSB) and Dummy capacitor of the converter respectively, and then combining the rest capacitors end to obtain 63 new capacitor groups C _ i: c _ u1^ and C _ u128^ are combined into C _1, C _ u2^ and C _ u127^ are combined into C _2, C _ u3^ and C _ u126^ are combined into C _3 … … C _ u63^ and C _ u66^ are combined into C _ 63.

In fig. 2:

(1) each of the positive and negative capacitor arrays has 128 unit capacitors, denoted as C_ui。

(2) First sorting: the 128 unit capacitors are arranged in ascending order according to the capacitance value and are marked as C_ui ^*；

Two capacitors C to be located at the middle position_u64，C_u65As LSB and Dummy capacitors of the converter, respectively;

combining the rest capacitors end to obtain 63 new capacitor groups marked as C_i。

(3) And (3) second sequencing: arranging the new 63 capacitor groups in ascending order according to the capacitance value, and marking as C_i ^*；

The capacitor banks are selected at intervals, and 32 capacitor banks (64 unit capacitors) are selected as the MSB of the converter.

(4) The remaining capacitor banks are spaced and 16 capacitor banks (32 unit capacitors) are selected as the MSB-1 of the converter.

(5) The remaining capacitor banks are spaced to select 8 capacitor banks (16 unit capacitors) as the MSB-2 of the converter.

(6) And selecting the rest capacitor groups at intervals to obtain other valid bits of the converter: MSB-3, MSB-4, MSB-5.

And sequencing the 63 capacitor groups in ascending order for the second time, and sequentially marking as: c _1^ C _2^ C _3^ … … C _62^ C _63^ C _3^ C, after which interval is selected (as shown in (3)): selecting 32 capacitor groups (64 unit capacitors) as the Most Significant Bits (MSB) of the converter at intervals starting from the first capacitor group (C _1 ^); selecting 16 capacitor groups (32 unit capacitors) as the second most significant bit (MSB-1) of the converter at intervals from the first capacitor group (C _2 ^) in the remaining capacitor groups; the above interval selection method is continuously repeated in the remaining capacitor banks, starting with the first capacitor bank, and the number of the selected capacitor banks is halved each time to be used as the remaining valid bits of the converter: MSB-2, MSB-3 … …, until one capacitor bank (C _32 ^) remains as the next least significant bit (LSB +1) of the converter.

In fig. 1, if M is 8 and N is 8, it represents a 16-bit mixed-capacitor resistance type successive approximation analog-to-digital converter composed of a high 8-bit capacitor and a low 8-bit resistor; if M is 8 and N is 6, the successive approximation analog-to-digital converter is a 14-bit mixed capacitance resistance type successive approximation analog-to-digital converter composed of a high 8-bit capacitance and a low 6-bit resistance. The 16-bit (M-8, N-8) and 14-bit (M-8, N-6) mixed capacitance resistance type successive approximation analog-to-digital converters are corrected by adopting a capacitance calibration method which is completely the same as the 18-bit (M-8, N-10) mixed capacitance resistance type successive approximation analog-to-digital converter and is selected at a double-sequencing interval.

In Matlab, 18-bit, 16-bit and 14-bit mixed capacitance-resistance type successive approximation analog-to-digital converters are simulated, the capacitance mismatch rates () are respectively set to be 0.1%, 0.15% and 0.2%, and the simulation times of static simulation (differential nonlinearity (DNL) and Integral Nonlinearity (INL)) are set to be 100 times, and the simulation times of dynamic simulation (spurious-free dynamic range (SFDR) and signal-to-noise harmonic ratio (SNDR)) are set to be 500 times.

The results of the static simulation are shown in fig. 4(18 bits), fig. 5(16 bits), and fig. 6(14 bits), and summarized in table 1.

For 18-bit SAR ADC, the double-sequencing interval selection provided by the invention respectively improves the maximum root-mean-square (RMS) of DNL and the maximum root-mean-square (RMS) of INL by 95.1%, 97.1% to 0.43dB and 0.40 dB. For a 16-bit SAR ADC, the double-sequencing interval selection respectively improves the DNL maximum root mean square and the INL maximum root mean square by 94.4%, 96.3% to 0.22dB and 0.18 dB. For 14-bit SAR ADC, the double-sequencing interval selection respectively improves the DNL maximum root mean square and the INL maximum root mean square by 87.3%, 89.7% to 0.16dB and 0.15 dB.

The dynamic simulation results are shown in fig. 7(18 bits), fig. 8(16 bits), and fig. 9(14 bits), and summarized in table 2.

For the 18-bit SAR ADC, the double-sequencing interval selection provided by the invention respectively improves the minimum value and the average value of the SFDR by 28.76dB, 33.79dB to 106.40dB and 122.52 dB; the SNDR minimum value and average value are improved by 28.38dB, 25.86dB to 102.44dB and 108.80 dB. For a 16-bit SAR ADC, double-sequencing interval selection is performed to respectively increase the minimum value and the average value of the SFDR to 26.50dB, 32.21dB to 101.65dB and 117.16 dB; the SNDR minimum value and average value are improved by 24.31dB, 18.66dB to 95.21dB and 97.84 dB. For 14-bit SAR ADC, double-sequencing interval selection is adopted to respectively increase the minimum value and the average value of SFDR by 26.13dB, 25.76dB to 98.24dB and 108.58 dB; the SNDR minimum value and average value are improved by 17.00dB, 9.62dB to 85.64dB and 86.00 dB.

Tables 3 and 4 summarize the static and dynamic performance enhancement comparisons of the double-sequencing interval selection proposed herein and the medium-level selection proposed in patent 201910772581.3, wherein the maximum root mean square of DNL and the maximum root mean square of INL enhancement in table 3, and the enhancement of the SFDR mean and the SNDR mean in table 4, respectively. It can be seen that the double-sequencing interval selection proposed by the present invention is almost the same as the middle selection proposed by patent 201910772581.3 in terms of static and dynamic performance improvement, but the double-sequencing interval selection proposed by the present invention only requires two-time sequencing, which is much lower than the six-time sequencing required by the middle selection proposed by patent 201910772581.3, thereby greatly saving power consumption and improving the conversion rate.

TABLE 1 DNL & INL 100 Monte Carlo simulation maximum root mean Square summary

TABLE 2 summary of SFDR and SNDR 500 Monte Carlo simulations

TABLE 3 double-sequencing interval selection vs. median selection for SAR ADC static performance improvement (Monte Carlo simulation times are 100)

TABLE 4 double-row interval selection and median selection for SAR ADC dynamic performance enhancement comparison (Monte Carlo simulation times are 500)

Claims

1. A double-sequencing interval selected capacitance correction method applied to an analog-to-digital converter comprises the following steps:

Two unit capacitors to be located at the middle positionRespectively as the LSB and Dummy capacitors of the converter; then the rest capacitors are combined end to obtain n/2-1 new capacitor groups C_i：

And

combination is C₁、

And

combination is C₂、And

in combination ofAnd

combination is C_(n/2-1)；

and 4, step 4: for the sorted capacitor banks, from the first capacitor bank

Starting interval selection, and selecting current n/4 capacitor groups as the most significant bit MSB of the converter;

and 5: for the remaining capacitor banks, from the first capacitor bankStarting interval selection, and selecting current n/8 capacitor groups as the second most significant bit MSB-1 of the converter;

step 6: and 5, repeating the step 5, selecting the capacitor groups at intervals from the first capacitor group in the rest capacitor groups, and halving the number of the selected capacitor groups each time to be used as the rest effective bits of the converter: MSB-2, MSB-3 … …, until one capacitor bank remains

As the second least significant bit LSB +1 of the converter;