CN110708033B - Automatic resistance correction method for bandwidth reconfigurable filter and circuit thereof - Google Patents
Automatic resistance correction method for bandwidth reconfigurable filter and circuit thereof Download PDFInfo
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Abstract
The invention discloses a resistance automatic correction method and a circuit thereof for a bandwidth reconfigurable filter. The invention solves the problem of resistance precision with wide adjustable range, improves the mapping resistance array on the basis of the traditional binary resistance array, and greatly reduces the total number of the resistors; the method comprises the steps of improving a resistor mapping logic, mapping resistors with different resistance requirements by using functions at two ends through piecewise function fitting, multiplexing dividers at the same time, and realizing the mapping logic requirements on the premise of not increasing the number of the dividers. After correction in specific implementation, the relative error of the adjustable resistor is within 5%. The circuit of the invention can be widely applied to filters with reconfigurable bandwidth.
Description
Technical Field
The invention relates to a resistance correction technology, in particular to a resistance automatic correction technology with a wide adjustable range. The field in which it is directly applied is filters with reconfigurable bandwidth; in particular to a resistance automatic correction method and a circuit thereof for a bandwidth reconfigurable filter.
Background
The mismatch of resistance cannot be ignored due to the shrinkage of the integrated circuit process node. When the characteristic size is 65nm, the relative error of the unit resistance is about 10-20%. For circuits where the resistance value requires precision, it is necessary to correct the resistance.
For a filter with a reconfigurable bandwidth, resistors with different sizes need to be used under different bandwidths, the variation range of the resistors is large, the adjustment range is usually hundreds of ohms to tens of kiloohms, and the relative error in the variation range is required to be within 5%. The adjustable resistor is generally implemented by controlling each bit of binary resistor in a binary resistor array formed by unit resistors with the same size, and realizing the adjustment of the equivalent resistor by using the parallel connection of the binary resistors. The binary resistor array has the disadvantage that when the required resistance is large, a larger resistor needs to be connected in parallel to ensure the precision requirement, for example, to achieve the relative error of 4R resistor within 5%, 8R, 16R, 32R and 64R need to be additionally connected in parallel to meet the requirement.
Disclosure of Invention
The invention aims to solve the technical problem of inventing a resistance automatic correction technology with wide adjustable range, and the purpose is mainly to be used for a filter with reconfigurable bandwidth.
The technical scheme adopted by the invention for solving the technical problems is as follows: a resistance automatic correction method for a bandwidth reconfigurable filter comprises the following steps:
the automatic correction method comprises the following steps:
s1, accessing a reference level, controlling a variable level controlled by a first signal through a correction resistor array, and outputting a comparison signal;
s2, outputting a first signal to control a correction resistor array by receiving the comparison signal so that the variable level gradually approaches to the reference level; outputting a second signal to control the reference level and the variable level to be reversely connected; outputting a third signal as a digital code corresponding to the specific resistance value;
s3, receiving a third signal, configuring a target resistance value, and generating a control signal of the mapping resistor array according to mapping logic;
s4, configuring according to the control signal of the step S3, and configuring the equivalent resistor R corresponding to the mapping resistor array M 。
In addition, the technical solution adopted by the present invention to solve the above technical problems is further: a resistance auto-correction circuit for a bandwidth reconfigurable filter:
the circuit comprises a comparator unit, a correction resistor array, a resistor control logic unit, a resistor mapping logic unit and a mapping resistor array;
the comparator unit is used for accessing a reference level, a variable level and an inversion signal and outputting a comparison signal;
the correction resistor array comprises a plurality of unit resistors R with the same size and is connected with the variable level input end of the comparator unit and the first signal output end of the resistor control logic unit;
the resistance control logic unit comprises a comparison signal input end, a first signal output end, a second signal output end and a third signal output end;
the resistance mapping logic unit comprises a third signal input end, a configuration target resistance input end and a control signal output end;
the mapping resistor array configures an equivalent resistor R corresponding to the mapping resistor array according to the control signal output by the control signal output end M 。
The invention has the beneficial effects that:
the invention relates to an automatic resistor correction technology which mainly comprises a comparator unit, a correction resistor array, a resistor control logic unit, a resistor mapping logic unit and a mapping resistor array. It has the following characteristics:
1. the invention improves the resistance mapping logic, compares the relation between the filter resistor array and the digital code, uses the piecewise function to carry out fitting, and uses the two-segment function to carry out mapping on the resistor sizes in different ranges. And meanwhile, the division is multiplexed for calculation, and the algorithm requirement is met on the premise of not increasing the number of the dividers.
2. The invention improves the mapping resistor array and greatly reduces the number of unit resistors. Compared with the conventional binary resistor array, taking fig. 2 as an example, in order to achieve the same accuracy in the conventional binary array, the maximum resistance needs to reach 64R, and the maximum resistance in the present invention is 8R.
3. After the circuit specifically implemented by the invention is applied to the filter, the change range of the resistance can meet hundreds of ohms to dozens of kilohms, the relative error of the resistance in the change range is ensured to be within 5 percent, and the broadband reconfigurable requirement of the filter is met.
Drawings
FIG. 1 is a flow chart of a method of the present invention for automatic resistance correction for a bandwidth reconfigurable filter;
FIG. 2 is an overall schematic block diagram of an automatic resistance correction circuit for a bandwidth reconfigurable filter according to the present invention;
FIG. 3 is a block diagram of the algorithm for correcting the resistor array of the present invention;
FIG. 4 is a mapping resistor array of the present invention;
FIG. 5 is a curve-fitting graph of the mapping relationship between the mapping resistors and the control codes of the present invention, wherein FIG. 5 (a) shows the curve relationship between the control codes and the resistor sizes corresponding to the mapping resistor array; FIG. 5 (b) shows the corresponding fitted graph;
FIG. 6 is an algorithmic block diagram of a mapping resistor array of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely apparent, the technical solutions in the embodiments of the present invention are described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The embodiments of the present invention are not limited to the following description, which will be further described with reference to the accompanying drawings.
The principle of the resistance auto-calibration technique embodied by the present invention is shown in fig. 2. The circuit comprises a comparator unit and a correction resistor array R ADJ Resistance control logic unit, resistance mapping logic unit and mapping resistance array R M 。
The comparator unit is used for accessing a reference level V REF Variable level V ADJ And an inversion signal Ctrl that outputs a comparison signal Comp _ result;
in one embodiment, the reference level V REF Through outsideConnecting resistor R EXT And an external current I EXT And (5) controlling.
In addition, the invention needs to change the level V ADJ Successive approximation reference level V REF Therefore, when the resistor array R is corrected ADJ The magnitude of this particular resistance value, when set to a particular value, is dependent on the correction current I ADJ External resistor R EXT And an external current I EXT 。
Further, as shown in fig. 3, the correction resistor array includes a plurality of unit resistors R of the same size and is connected to the variable level V of the comparator unit ADJ And a first signal D of the resistance control logic unit<7:0>An output end;
in one implementation manner, the correction resistor array is composed of 8 unit resistors, and through an equivalent manner, equivalent resistors which are sequentially reduced from left to right and similar to binary resistors can be generated, wherein the equivalent resistors can be 32R, 16R, 8R, 4R, 2R, R, R/2,R/4 respectively; of course, the maximum and minimum resistance can be adjusted, for example, the maximum resistance is 64R, the minimum resistance is R/2, or the maximum resistance is 16R, and the minimum resistance is R/8.
In another implementation manner, the calibration resistor array may also be formed by 16 unit resistors, and accordingly, the target resistance value and the corresponding number of resistors and resistance values of the mapping resistor array need to be matched accordingly.
Further, as shown in fig. 2 and fig. 3, the resistance control logic unit includes a comparison signal input terminal, a first signal (Ctrl signal) output terminal, a second signal (D <7:0> signal) output terminal, and a third signal (Ru <7:0> signal) output terminal;
equivalent resistance R ADJ Unit resistance R and digital code D<7:0>The relationship of (1) is:
the resistance control logic unit comprises a programmable counter Program CNT, an accumulator, a judger (D _ a > Count/2), a digital code generator D _ auto <7:0>, an Average processor Average, a first register Reg1 and a second register Reg2; the programmable counter is used for determining the occurrence frequency of the comparison signal Comp _ result and outputting an inversion signal, namely a second signal, and is used for controlling two input signals (a reference level and a variable level) of the reverse connection comparator unit; the accumulator is used for determining the number Count of logic 1 appearing in the comparison signal Comp _ result; the judger is used for determining whether the result D _ a of the accumulator is greater than 1/2 of the result Count of the programmable counter, namely, the judgment that D _ a is greater than Count/2; the digital code generator outputs a digital code corresponding to the specific resistance value, namely a first signal according to the output result of the judger; the first register is used for storing the digital code output by the corresponding digital code generator before the inversion signal is output; the second register is used for storing the digital code output by the corresponding digital code generator after the inversion signal is output; the average processor is used for carrying out average operation on the results stored by the first register and the second register and outputting a digital code corresponding to a specific resistance value, namely a third signal.
In one implementation, the accumulator includes an adder and a flip-flop DFF; the input end of the adder is connected with the output end of the comparator unit and the output end of the trigger, the input end of the trigger is also connected with the programmable counter, and the output end of the trigger is connected with the judger.
An embodiment of the correction resistor is given below, when the input signal V of the comparator is equal to the unit resistor R of the same size forming the correction resistor array ADJ And V REF When close, the output result Comp _ result of the comparator unit has the same probability of logic 0 and logic 1. By using this feature, the results of the comparator units are counted, the programmable counter Program CNT determines the counted total Cout, and the accumulator result D _ a represents the number of logical 1's that the comparator result Comp _ result appears within the total Cout. Initial state, calibration matrixThe switch corresponding to R/4 of the minimum resistor in the row is closed, the other resistors are opened, the counter Program CNT starts counting, and when the counting result reaches a determined value Cout, if the accumulation result D _ a exceeds 1/2 of the total counting number Cout, the correction resistance value R is represented ADJ Too large, requiring a small adjustment, corresponding to D<0>Setting 1, and closing a switch of a resistor R/4; responsible for correcting the resistance value R ADJ When too small, the switch of resistor R/4 is open. And analogizing in turn, starting from the switch corresponding to the R/4 resistor, switching bit by bit to enable the voltage V of the correction resistor ADJ Successive approximation V REF . Finally, the output logic 0 and logic 1 of the comparator are uniformly distributed, and the correction is completed.
In addition, the offset of the comparator can cause deviation of the correction result, and the influence caused by the offset of the comparator is eliminated. After one correction is completed, the first register Reg1 is used to store the correction result. Control signal Ctrl is inverted, and signal V is input at two ends of comparator ADJ And V REF Reversely connecting, correcting once again, storing the second correction result by using a second register Reg2, averaging the two results, and outputting a digital code Ru corresponding to a specific resistance value<7:0>。
The resistance mapping logic unit comprises a third signal input end, a configuration target resistance input end and a control signal output end; the resistance mapping logic unit comprises a configuration resistor, a multiplier, a judger and a multiplexing divider; the multiplier is used for multiplying the third signal; the judger is used for judging the multiplication result and the size of the configuration resistor so as to correspondingly generate a gating signal; and the multiplexing divider is used for correspondingly dividing each gating signal to obtain a final control signal of the mapping resistor array.
The mapping resistor array configures an equivalent resistor R corresponding to the mapping resistor array according to the control signal output by the control signal output end M 。
The mapping resistor array comprises binary parallel structure resistors and series-parallel combined structure resistors, wherein the binary parallel structure resistors comprise N binary resistors which are connected in parallel; the series-parallel connection structure resistor comprises N resistors with the same size which are connected in parallel, and a unit resistor is also connected between every two resistors with the same size in series, wherein the value of the resistor with the same size in the series-parallel connection structure resistor is the same as the value of the Nth binary resistance.
In one embodiment, as shown in FIG. 4, the unit resistance of the mapping resistor array is R, and the adjustment range of the resistance is about R/32 to 5R. Compared with the traditional binary resistor array, the improvement is that the small resistor (binary parallel structure) still adopts a binary parallel structure, and the large resistor (series-parallel combined structure resistor) adopts a series-parallel combined form formed by R and 2R. When each switch is closed independently, the corresponding resistance is R/16, R/8, R/4, R/2, R, 2R, 3R, 4R, 5R, 6R, 7R and 8R. This structure can provide more adjustment steps when the mapping resistance ranges from 2R to 5R, thereby ensuring accuracy. If a conventional binary structure is used, the maximum resistance would have to be 64R to achieve the same accuracy.
The curve relationship between the control code corresponding to the mapping resistor array and the resistor size is shown in fig. 5 (a), the curve is fitted, the fitting curve is shown in fig. 5 (b), and the fitting relationship after derivation is as follows:
when configured target resistance value R CFG Greater than 1.5R U When the resistors 2R to 5R are mapped, the resistors R/16, R/8, R/4, R/2 and R of the binary structure part are all opened, and the equivalent resistor R M R is determined by series- parallel resistors 2R, 3R, 4R, 5R, 6R, 7R and 8R M The size of (d); when the resistance R is configured CFG Less than 1.5R U While, the equivalent resistance R M The resistance of the series-parallel connection part is extremely small, and the equivalent resistance can be directly calculated in a binary mode.
The mapping logic algorithm embodied by the present invention is shown in fig. 6, and according to the fitting relationship of formula (3), when it is to be implemented by digital circuit,the direct description requires two high precision dividers. In the embodiment of the invention, the same divider is multiplexed, and the resistor R is configured according to the input signal CFG Digital code R corresponding to specific resistance U Generating a gating signal, selecting dividend word1 and divisor word2, and then carrying out different calculations on quotient quo according to the gating signal to obtain a final mapping resistor R M Control signal D of OUT <11:0>The invention reduces the number of dividers by a multiplexing mode, thereby effectively reducing the hardware consumption.
In one embodiment, the calibration resistor array and the mapping resistor array use the same size unit resistor, approximately 5k Ω.
It is understood that, in the present invention, some features of the method and the circuit thereof may be mutually cited, and the present invention is not exemplified.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable storage medium, and the storage medium may include: ROM, RAM, magnetic or optical disks, and the like.
The above-mentioned embodiments, which further illustrate the objects, technical solutions and advantages of the present invention, should be understood that the above-mentioned embodiments are only preferred embodiments of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. The automatic resistance correction circuit for the bandwidth reconfigurable filter is characterized by comprising a comparator unit, a correction resistance array, a resistance control logic unit, a resistance mapping logic unit and a mapping resistance array;
the comparator unit is used for accessing a reference level, a variable level and an inversion signal and outputting a comparison signal;
the correction resistor array comprises a plurality of unit resistors R with the same size, and is connected with the variable level input end of the comparator unit and the first signal output end of the resistor control logic unit;
the resistance control logic unit comprises a comparison signal input end, a first signal output end, a second signal output end and a third signal output end;
the resistance mapping logic unit comprises a third signal input end, a configuration target resistance input end and a control signal output end;
the mapping resistor array configures an equivalent resistor R corresponding to the mapping resistor array according to the control signal output by the control signal output end M ；
The resistance control logic unit comprises a programmable counter, an accumulator, a judger, a digital code generator, a mean value processor, a first register and a second register; the programmable counter is used for determining the occurrence frequency of the comparison signal Comp _ result and outputting an inversion signal, namely a second signal, and is used for reversely connecting two paths of input signals of the comparator unit; the accumulator is used for determining the number of logic 1 occurring in the comparison signal Comp _ result; the judger is used for determining whether the result of the accumulator is greater than 1/2 of the result of the programmable counter; the digital code generator outputs a digital code corresponding to the specific resistance value, namely a first signal according to the output result of the judger; the first register is used for storing a digital code output by a corresponding digital code generator before the inversion signal is output; the second register is used for storing the digital code output by the corresponding digital code generator after the inversion signal is output; the average processor is used for carrying out average operation on the results stored by the first register and the second register and outputting a digital code corresponding to the specific resistance value, namely a third signal.
2. The automatic resistance correction circuit for a bandwidth reconfigurable filter according to claim 1, wherein the accumulator includes an adder and a flip-flop; the input end of the adder is connected with the output end of the comparator unit and the output end of the trigger, the input end of the trigger is also connected with the programmable counter, and the output end of the trigger is connected with the judger.
3. The automatic resistance correction circuit for a bandwidth reconfigurable filter according to claim 1, wherein the resistance mapping logic unit comprises a configuration resistor, a multiplier, a judger and a multiplexing divider; the multiplier is used for multiplying the third signal; the judger is used for judging the multiplication result and the size of the configuration resistor so as to correspondingly generate a gating signal; and the multiplexing divider is used for correspondingly dividing each gating signal to obtain a final control signal of the mapping resistor array.
4. The automatic resistance correction circuit for the bandwidth reconfigurable filter according to claim 1, wherein the mapping resistor array comprises a binary parallel structure resistor and a series-parallel combined structure resistor, and the binary parallel structure resistor comprises N binary resistors connected in parallel; the series-parallel connection structure resistor comprises N resistors with the same size which are connected in parallel, and a unit resistor is also connected between every two resistors with the same size in series, wherein the value of the resistor with the same size in the series-parallel connection structure resistor is the same as the value of the Nth binary resistance.
5. A resistance automatic correction method for a bandwidth reconfigurable filter, for implementing a resistance automatic correction circuit for a bandwidth reconfigurable filter according to any one of claims 1 to 4, characterized in that the automatic correction method comprises the steps of:
s1, accessing a reference level, controlling a variable level controlled by a first signal through a correction resistor array, and outputting a comparison signal;
s2, outputting a first signal to control a correction resistor array by receiving the comparison signal so that the variable level gradually approaches to the reference level; outputting a second signal to control the reference level and the variable level to be reversely connected; outputting a third signal as a digital code corresponding to the specific resistance value;
s3, receiving a third signal, configuring a target resistance value, and generating a control signal of the mapping resistor array according to mapping logic;
s4, configuring according to the control signal of the step S3, and configuring the equivalent resistor R corresponding to the mapping resistor array M 。
6. The method according to claim 5, wherein the step of gradually approximating the reference level with variable level in step S2 comprises switching the binary resistors in the correction resistor array from small to large, gradually controlling the binary resistors to open and close, and gradually outputting the first signal "1" or "0"; until the correction resistor voltage, i.e. the variable level, is successively approximated to the reference level, wherein the first signal "1" indicates the closing of the binary resistor and the first signal "0" indicates the opening of the binary resistor.
7. The method as claimed in claim 5, wherein the step S2 comprises inverting the reference level and the variable level by the second signal, outputting digital codes before and after the inversion respectively, averaging the two digital codes, and finally outputting the digital code corresponding to the specific resistance value.
8. The method of claim 5, wherein the generation of the control signal for mapping the resistor array comprises:
wherein D is OUT A control signal representing a mapped resistor array; r is CFG Target resistance value, R, representing configuration U Indicating the digital code corresponding to the specific resistance value.
9. A filter for bandwidth reconfiguration according to claim 8The method for automatically correcting the resistance is characterized in that the configuration process of the step S4 comprises the step of outputting a control signal for mapping the resistance array when the configured target resistance value resistance is more than 1.5 times of the digital code corresponding to the specific resistance value; determining equivalent resistance R by controlling series-parallel connection structure resistance in improved mapping resistor array M The size of (d); when the configured target resistance value resistance is less than or equal to 1.5 times of the digital code corresponding to the specific resistance value, outputting a control signal of the mapping resistor array; determining equivalent resistance R by controlling binary structure resistance in improved mapping resistance array M The size of (2).
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| CN113098450B (en) * | 2021-03-15 | 2023-03-31 | 西安电子科技大学 | Reconfigurable electromagnetic super-surface biasing method |
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