CN110707088A - Three-dimensional memory device and manufacturing method thereof - Google Patents
Three-dimensional memory device and manufacturing method thereof Download PDFInfo
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- CN110707088A CN110707088A CN201910826314.XA CN201910826314A CN110707088A CN 110707088 A CN110707088 A CN 110707088A CN 201910826314 A CN201910826314 A CN 201910826314A CN 110707088 A CN110707088 A CN 110707088A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The invention provides a three-dimensional memory device and a manufacturing method thereof, wherein the device comprises a first voltage wire, a second voltage wire and a plurality of dummy wires, wherein the first voltage wire is used as a high-voltage wire, the second voltage wire is used as a low-voltage wire, the first voltage wire and the second voltage wire are positioned on the same straight line, the dummy wires are distributed at two sides of the first voltage wire and the second voltage wire, any dummy wire which is adjacent to the first voltage wire and the second voltage wire only has a relative part with one of the first voltage wire and the second voltage wire in a second direction, or has no relative part with the first voltage wire and the second voltage wire in the second direction. According to the invention, through improving the layout of the wires, the nominal wires adjacent to the high-voltage wires and the low-voltage wires are not opposite to the high-voltage wires and the low-voltage wires, so that the wire-to-wire breakdown voltage between the high-voltage/low-voltage wires and the nominal wires can be effectively increased under the condition of not increasing the wire spacing, the area of a chip can be effectively controlled, and the original high-voltage wires and the original low-voltage wires cannot be influenced.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuits, and relates to a three-dimensional memory device and a manufacturing method thereof.
Background
In a three-dimensional logic and NAND flash memory (3D NAND) technology, Metal lines on an upper layer of a high voltage Metal oxide semiconductor (HV MOS) in a complementary Metal oxide semiconductor Page Buffer circuit (CMOS Page Buffer circuit) are very long Floating Dummy lines (Floating Dummy) except for a high voltage Metal Line (HV Metal Line) HV and a low voltage Metal Line (LV Metal Line), and the Floating Dummy lines are affected by a coupling effect (coupling effect) of the high voltage Metal lines, so that a Line-to-Line breakdown voltage (Vbd) between the two Metal lines of the high voltage/Dummy lines (HV/Dummy) or between the two Metal lines of the Dummy lines/low voltage (Dummy/LV) is reduced, thereby causing a problem of time-dependent dielectric breakdown (TDDB).
The current solution is mainly to increase the distance between the wires, but as the number of layers of the 3D NAND technology is more and more, the number of wires at the back section of the device is greatly increased, and the increase of the distance is no longer possible.
Therefore, how to design a new three-dimensional memory device and a method for fabricating the same to improve the above problems becomes an important technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional memory device and a method for fabricating the same, which are used to solve the problem that the floating dummy trace in the prior art is affected by the coupling effect of the high-voltage metal line, so that the line-to-line breakdown voltage (Vbd) is reduced, thereby causing time-dependent dielectric breakdown (TDDB).
To achieve the above and other related objects, the present invention provides a three-dimensional memory device, comprising:
a first voltage trace extending along a first direction;
the second voltage wire is positioned on the same straight line with the first voltage wire, and the voltage of the second voltage wire is lower than that of the first voltage wire;
a plurality of dummy traces distributed on both sides of the first voltage trace and the second voltage trace, wherein any one of the dummy traces adjacent to the first voltage trace and the second voltage trace has only a relative portion with one of the first voltage trace and the second voltage trace in a second direction, or has no relative portion with both the first voltage trace and the second voltage trace in the second direction, and the second direction is perpendicular to the first direction.
Optionally, the plurality of dummy traces include a first dummy trace, a second dummy trace, a third dummy trace and a fourth dummy trace that are adjacent to the first voltage trace and the second voltage trace, where the first dummy trace and the second dummy trace are located on a same straight line, the third dummy trace and the fourth dummy trace are located on a same straight line, the first dummy trace and the third dummy trace are located on two opposite sides of the first voltage trace and have a relative portion in the second direction with the first voltage trace, and the second dummy trace and the fourth dummy trace are located on two opposite sides of the second voltage trace and have a relative portion in the second direction with the second voltage trace.
Optionally, the three-dimensional memory device further includes at least one center dummy trace, where the center dummy trace is located on the same line as the first voltage trace and the second voltage trace and located between the first voltage trace and the second voltage trace.
Optionally, the first dummy trace, the second dummy trace, the third dummy trace and the fourth dummy trace have opposite portions to the central dummy trace in the second direction.
Optionally, the plurality of dummy traces further includes a fifth dummy trace, the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.
Optionally, the first dummy trace and the fourth dummy trace have no opposite portion to the center dummy trace in the second direction, and the second dummy trace and the third dummy trace have opposite portions to the center dummy trace in the second direction.
Optionally, the plurality of dummy traces further includes a fifth dummy trace, the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.
Optionally, a page buffer high voltage NMOS transistor is disposed in the three-dimensional memory device, a drain of the transistor is connected below the first voltage trace through a first contact, and a source of the transistor is connected below the second voltage trace through a second contact.
Optionally, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.
Optionally, the three-dimensional memory device further includes a third voltage trace, a voltage of the third voltage trace is equal to a voltage of the second voltage trace, the third voltage trace is parallel to the second voltage trace, and the third voltage trace is spaced from the second voltage trace by at least one dummy trace.
Optionally, the third voltage trace and the second voltage trace are connected by at least one dummy trace and at least two connecting portions, two sides of at least one connecting portion are respectively connected with the second voltage trace and one dummy trace, and two sides of at least one connecting portion are respectively connected with one dummy trace and the third voltage trace.
The invention also provides a manufacturing method of the three-dimensional memory device, which comprises the following steps:
providing a substrate;
forming a wiring layer above the substrate, wherein the wiring layer includes a first voltage trace, a second voltage trace and a plurality of dummy traces, the second voltage trace and the first voltage trace are located on the same straight line, the voltage of the second voltage trace is lower than that of the first voltage trace, the dummy traces are distributed on two sides of the first voltage trace and the second voltage trace, any one of the dummy traces adjacent to the first voltage trace and the second voltage trace has a relative portion only with one of the first voltage trace and the second voltage trace in a second direction, or has no relative portion with both the first voltage trace and the second voltage trace in the second direction, and the second direction is perpendicular to the first direction.
Optionally, the routing layer is obtained by forming a conductive layer over the substrate and patterning the conductive layer.
Optionally, the routing layer is obtained by forming a mask layer with an opening pattern over the substrate and forming a conductive material in the opening pattern.
Optionally, the plurality of dummy traces include a first dummy trace, a second dummy trace, a third dummy trace and a fourth dummy trace that are adjacent to the first voltage trace and the second voltage trace, where the first dummy trace and the second dummy trace are located on a same straight line, the third dummy trace and the fourth dummy trace are located on a same straight line, the first dummy trace and the third dummy trace are located on two opposite sides of the first voltage trace and have a relative portion in the second direction with the first voltage trace, and the second dummy trace and the fourth dummy trace are located on two opposite sides of the second voltage trace and have a relative portion in the second direction with the second voltage trace.
Optionally, the three-dimensional memory device further includes at least one center dummy trace, where the center dummy trace is located on the same line as the first voltage trace and the second voltage trace and located between the first voltage trace and the second voltage trace.
Optionally, the first dummy trace, the second dummy trace, the third dummy trace and the fourth dummy trace have opposite portions to the central dummy trace in the second direction.
Optionally, the plurality of dummy traces further includes a fifth dummy trace, the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.
Optionally, the first dummy trace and the fourth dummy trace have no opposite portion to the center dummy trace in the second direction, and the second dummy trace and the third dummy trace have opposite portions to the center dummy trace in the second direction.
Optionally, the plurality of dummy traces further includes a fifth dummy trace, the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.
Optionally, a page buffer high voltage NMOS transistor is disposed in the substrate, the first voltage trace is connected to a top of a drain of the transistor through a first contact, and the second voltage trace is connected to a top of a source of the transistor through a second contact.
As described above, according to the three-dimensional memory device and the manufacturing method thereof of the present invention, by improving the layout of the traces, the dummy trace adjacent to the high-voltage trace or the low-voltage trace does not face the high-voltage trace and the low-voltage trace at the same time, so that the line-to-line breakdown voltage (Vbd) between the high-voltage trace and the dummy trace or between the dummy trace and the low-voltage trace can be effectively increased without increasing the distance between the traces, the chip area can be effectively controlled, and the original high-voltage trace and low-voltage trace are not affected.
Drawings
Fig. 1 is a layout diagram of a trace plane of an exemplary three-dimensional memory device.
Fig. 2 is a diagram showing simulation results of the three-dimensional memory device shown in fig. 1.
Fig. 3 is a layout diagram of traces in a three-dimensional memory device according to a first embodiment of the invention.
Fig. 4 is a layout diagram of traces in a second embodiment of the three-dimensional memory device according to the present invention.
Fig. 5 is a layout diagram of traces in a third embodiment of the three-dimensional memory device according to the present invention.
Fig. 6 is a diagram showing simulation results of the three-dimensional memory device shown in fig. 5.
Fig. 7 is a layout diagram of traces in a fourth embodiment of the three-dimensional memory device according to the present invention.
Description of the element reference numerals
101 first voltage trace
102 second voltage trace
103 first contact part
104 second contact part
105. 106, 107, 108, 109, 110, 111 dummy trace
112 third voltage trace
113. 114, 115 connection part
Width of W routing
D routing space
201 first voltage trace
202 second voltage trace
203 first contact part
204 second contact portion
205 first dummy trace
206 second dummy trace
207 third dummy trace
208 fourth dummy trace
209. 210, 211, 212 dummy trace
213 third voltage trace
301 first voltage trace
302 second voltage trace
303 first contact part
304 second contact part
305 intermediate dummy trace
306 first dummy trace
307 second dummy trace
308 third dummy trace
309 fourth dummy trace
310. 311, 312, 313 dummy trace
314 third voltage trace
401 first voltage trace
402 second voltage trace
403 first contact part
404 second contact part
405 intermediate dummy trace
406 first dummy trace
407 second dummy trace
408 third dummy trace
409 fourth dummy trace
410. 411, 412, 413 dummy trace
414 third voltage trace
415 fifth dummy trace
416. 417, 418 connection part
501 first voltage trace
502 second voltage trace
503 first contact part
504 second contact part
505 intermediate dummy trace
506 first dummy trace
507 second dummy trace
508 third dummy trace
509 fourth dummy trace
510. 511, 512, 513 dummy trace
514 third voltage trace
515 fifth virtual routing
X second direction
Y first direction
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation can be changed freely, and the layout of the components can be changed freely.
As shown in fig. 1, a layout plan of traces of an exemplary three-dimensional memory device is shown, where the three-dimensional memory device includes a first voltage trace 101 and a second voltage trace 102 that are located on a same straight line, where the first voltage trace 101 is used as a high voltage trace, the second voltage trace 102 is used as a low voltage trace, and the first voltage trace 101 and the second voltage trace 102 respectively provide a high voltage and a low voltage for a semiconductor device below the first voltage trace through a first contact 103 and a second contact 104 below the first voltage trace.
As an example, the trace width W and the trace pitch D are shown in fig. 1.
As an example, the three-dimensional memory device further includes a plurality of dummy traces distributed on two opposite sides of the first voltage trace 101 and the second voltage line trace 102, where the dummy trace 105 is adjacent to left sides of the first voltage trace 101 and the second voltage line trace 102 and faces the first voltage trace 101 and the second voltage line trace 102 at the same time, the dummy trace 106 and the dummy trace 107 are adjacent to right sides of the first voltage trace 101 and the second voltage line trace 102 and faces the first voltage trace 101 and the second voltage line trace 102 at the same time, and the dummy trace 108, the dummy trace 109, the dummy trace 111 and the dummy trace 111 have other traces spaced from the first voltage trace 101 or the second voltage line trace 102.
As an example, the three-dimensional memory device further includes a third voltage trace 112 distributed on the right side of the first voltage trace 101 and the second voltage line trace 102, the third voltage trace 112 also serves as a low voltage trace, and other traces are spaced between the third voltage trace 11 and the first voltage trace 101 or the second voltage line trace 102.
As shown in fig. 2, a diagram illustrating simulation results of the three-dimensional memory device shown in fig. 1 is shown. A high voltage HV applied to the first voltage trace 101 is 22V, a low voltage LV applied to the second voltage trace 102 is 0V, and the second voltage trace 102 and the third voltage trace 112 are connected by a connection portion 113, the dummy trace 107, a connection portion 114, the dummy trace 111, and a connection portion 115, which shows that, due to a coupling effect, a voltage of the dummy trace 105 is 6.5V, a voltage of the dummy trace 106 is 11.27V, and a voltage of the dummy trace 110 is 4.7V.
Since the metal TDDB breakdown location (where the electric field is the strongest) is between two wires with the largest voltage difference, in the simulation result of fig. 2, the maximum voltage difference Δ V between the two wires is (22-6.5) V is 15.5V, and therefore the device is prone to breakdown between the first voltage wire 101 and the dummy wire 105. The dummy trace 105 is adjacent to the first voltage trace 101, and has a longer length, and is opposite to the first voltage trace 101 and the second voltage line 102.
According to the invention, through the simulation of the device and the analysis of the simulation result, the virtual wires which are adjacent to the high-voltage wires and the low-voltage wires and are most influenced by the coupling effect are considered to be the virtual wires which are adjacent to the two sides of the high-voltage wires and the low-voltage wires, so that the adjacent virtual wires which face the high-voltage wires and the low-voltage wires at the same time are removed by adopting a cutting method. The technical solution of the present invention will be described below by way of more specific examples.
Example one
In this embodiment, a three-dimensional memory device is provided, please refer to fig. 3, which shows a layout diagram of a trace plane of the three-dimensional memory device, where the three-dimensional memory device includes a first voltage trace 201, a second voltage trace 202 and a plurality of dummy traces, where the first voltage trace 201 extends along a first direction Y, the second voltage trace 202 and the first voltage trace 201 are located on a same straight line, and the plurality of dummy traces are distributed on two sides of the first voltage trace 201 and the second voltage trace 202.
Specifically, the voltage of the second voltage wire is lower than that of the first voltage wire, the first voltage wire 201 serves as a high-voltage wire, and the second voltage wire 202 serves as a low-voltage wire.
As an example, a page buffer high voltage NMOS transistor is disposed in the three-dimensional memory device, a drain of the transistor is connected below the first voltage trace 201 through a first contact 203, and a source of the transistor is connected below the second voltage trace 202 through a second contact 204.
As an example, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.
Specifically, any one of the dummy traces adjacent to the first voltage trace 201 and the second voltage trace 202 has a relative portion with only one of the first voltage trace and the second voltage trace in a second direction X, or has no relative portion with both the first voltage trace and the second voltage trace in the second direction, and the second direction X is perpendicular to the first direction Y.
In this embodiment, the plurality of dummy traces includes a first dummy trace 205, a second dummy trace 206, a third dummy trace 207, and a fourth dummy trace 208 adjacent to the first voltage trace and the second voltage trace, where the first dummy trace 205 and the second dummy trace 206 are located on a same straight line, the third dummy trace 207 and the fourth dummy trace 208 are located on a same straight line, the first dummy trace 205 and the third dummy trace 207 are respectively located on two opposite sides of the first voltage trace 201 and have a relative portion with the first voltage trace 201 in the second direction X, and the second dummy trace 206 and the fourth dummy trace 208 are respectively located on two opposite sides of the second voltage trace 202 and have a relative portion with the second voltage trace 202 in the second direction X.
As an example, the plurality of dummy traces further includes a dummy trace 209, a dummy trace 210, a dummy trace 211, and a dummy trace 212 that are not directly adjacent to the first voltage trace 201 or the second voltage trace 202.
As an example, the three-dimensional memory device further includes a third voltage trace 213, the third voltage trace 213 being a low voltage trace, and a voltage of the third voltage trace being equal to a voltage of the second voltage trace. The third voltage trace 213 is parallel to the second voltage trace 202, and the third voltage trace 213 is spaced apart from the second voltage trace 202 by at least one dummy trace.
Of course, the dummy trace not adjacent to the high voltage trace and the low voltage trace on the same straight line may also adopt other layouts, and the low voltage trace not located on the same straight line may also adopt other layouts, and the protection scope of the present invention should not be limited too much here.
In the three-dimensional memory device of the embodiment, the dummy wirings adjacent to the high-voltage wirings or the low-voltage wirings are all different and face the high-voltage wirings and the low-voltage wirings, so that the line-to-line breakdown voltage (Vbd) between the high-voltage wirings and the dummy wirings or between the dummy wirings and the low-voltage wirings can be effectively increased under the condition of not increasing the distance between the wirings, the effective control of the area of a chip is facilitated, the new wiring layout is only equivalent to setting small cut-off points in some wirings, and the original high-voltage wirings and low-voltage wirings cannot be influenced.
Example two
The present embodiment and the first embodiment adopt substantially the same technical solutions, except that there is no dummy trace interval between the high voltage trace and the low voltage trace on the same straight line in the first embodiment, but in the present embodiment, a dummy trace is disposed between the high voltage trace and the low voltage trace on the same straight line, in other words, a cut point is disposed in the original low voltage trace.
Referring to fig. 4, a layout plan view of a three-dimensional memory device in this embodiment is shown, where the three-dimensional memory device includes a first voltage trace 301, a second voltage trace 302, at least one central dummy trace 305, and a plurality of dummy traces, where the first voltage trace 201 extends along a first direction Y, the first voltage trace 301, the second voltage trace 302, and the central dummy trace 305 are located on a same straight line, the central dummy trace 305 is located between the first voltage trace 301 and the second voltage trace 302, and the plurality of dummy traces are distributed on two sides of the first voltage trace 301 and the second voltage trace 302.
Specifically, the voltage of the second voltage trace is lower than that of the first voltage trace, the first voltage trace 301 serves as a high voltage trace, and the second voltage trace 302 serves as a low voltage trace.
As an example, a page buffer high voltage NMOS transistor is disposed in the three-dimensional memory device, a drain of the transistor is connected below the first voltage trace 301 through a first contact 303, and a source of the transistor is connected below the second voltage trace 302 through a second contact 304.
As an example, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.
Specifically, any one of the dummy traces adjacent to the first voltage trace and the second voltage trace has a relative portion with respect to only one of the first voltage trace and the second voltage trace in a second direction X, or has no relative portion with respect to both the first voltage trace and the second voltage trace in the second direction X, and the second direction X is perpendicular to the first direction Y.
In this embodiment, the plurality of dummy traces includes a first dummy trace 306, a second dummy trace 307, a third dummy trace 308 and a fourth dummy trace 309, where the first dummy trace 306 and the second dummy trace 307 are located on the same straight line, the third dummy trace 308 and the fourth dummy trace 309 are located on the same straight line, the first dummy trace 306 and the third dummy trace 308 are respectively located on two opposite sides of the first voltage trace 301, and the second dummy trace 307 and the fourth dummy trace 309 are respectively located on two opposite sides of the second voltage trace 302.
Further, the first dummy trace 306, the second dummy trace 307, the third dummy trace 308 and the fourth dummy trace 309 are all opposite to the center dummy trace 305 in the second direction X.
As an example, the plurality of dummy traces further includes a dummy trace 310, a dummy trace 311, a dummy trace 312, and a dummy trace 313 that are not directly adjacent to the first voltage trace 301 or the second voltage trace 302.
As an example, the three-dimensional memory device further includes a third voltage trace 314, where the third voltage trace 314 is a low voltage trace and a voltage of the third voltage trace is equal to a voltage of the second voltage trace. The third voltage trace 314 is parallel to the second voltage trace 302, and the third voltage trace 314 is spaced apart from the second voltage trace 302 by at least one of the dummy traces.
Of course, the dummy trace not adjacent to the high voltage trace and the low voltage trace on the same straight line may also adopt other layouts, and the low voltage trace not located on the same straight line may also adopt other layouts, and the protection scope of the present invention should not be limited too much here.
The layout of the trace plane of the three-dimensional memory device of this embodiment, relative to the layout of the trace plane shown in fig. 1, is equivalent to cutting off the dummy trace 105 and the second voltage trace 102, wherein, cutting the dummy trace 105 can destroy the relationship between the high voltage trace and the low voltage trace facing the original dummy trace 105, and cutting the second voltage trace 102 is equivalent to changing a part of the original low voltage trace into the dummy trace, the relationship of the original dummy trace 106 facing both the high voltage trace and the low voltage trace can be destroyed, thereby effectively improving the line-to-line breakdown voltage (Vbd) between the high-voltage lines and the dummy lines or between the dummy lines and the low-voltage lines without increasing the space between the lines, being beneficial to effectively controlling the chip area, and the new routing layout is only equivalent to the arrangement of small cut-off points in some routing, and the original high-voltage routing and low-voltage routing cannot be influenced.
EXAMPLE III
The second embodiment adopts a substantially same technical solution as the second embodiment, except that a fourth dummy trace directly adjacent to the low-voltage trace in the second embodiment is longer, and in the second embodiment, the plurality of dummy traces further includes a fifth dummy trace, the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace, which is equivalent to setting a breakpoint in the original fourth dummy trace, and dividing the longer fourth dummy trace into two dummy traces.
Referring to fig. 5, a layout plan view of a three-dimensional memory device in this embodiment is shown, where the three-dimensional memory device includes a first voltage trace 401, a second voltage trace 402, at least one central dummy trace 405, and a plurality of dummy traces, where the first voltage trace 201 extends along a first direction Y, the first voltage trace 401, the second voltage trace 402, and the central dummy trace 405 are located on a same straight line, the central dummy trace 405 is located between the first voltage trace 401 and the second voltage trace 402, and the plurality of dummy traces are distributed on two sides of the first voltage trace 401 and the second voltage trace 402.
Specifically, the voltage of the second voltage trace is lower than that of the first voltage trace, the first voltage trace 401 serves as a high-voltage trace, and the second voltage trace 402 serves as a low-voltage trace.
As an example, a page buffer high voltage NMOS transistor is disposed in the three-dimensional memory device, a drain of the transistor is connected below the first voltage trace 401 through a first contact 403, and a source of the transistor is connected below the second voltage trace 402 through a second contact 404.
As an example, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.
Specifically, any one of the dummy traces adjacent to the first voltage trace and the second voltage trace has a relative portion with respect to only one of the first voltage trace and the second voltage trace in a second direction X, or has no relative portion with respect to both the first voltage trace and the second voltage trace in the second direction X, and the second direction X is perpendicular to the first direction Y.
In this embodiment, the plurality of dummy traces include a first dummy trace 406, a second dummy trace 407, a third dummy trace 408, a fourth dummy trace 409 and a fifth dummy trace 415, where the first dummy trace 406 and the second dummy trace 407 are located on the same straight line, the third dummy trace 408, the fourth dummy trace 409 and the fifth dummy trace 415 are located on the same straight line, and the fifth dummy trace 415 is located between the third dummy trace 408 and the fourth dummy trace 409. The first dummy trace 406 and the third dummy trace 408 are respectively located at two opposite sides of the first voltage trace 401, and the second dummy trace 407 and the fourth dummy trace 409 are respectively located at two opposite sides of the second voltage trace 402.
Further, the first dummy trace 406 and the third dummy trace 408 have opposite portions to the first voltage trace 401 and the center dummy trace 405 in the second direction X, and the second dummy trace 407 and the fourth dummy trace 409 have opposite portions to the second voltage trace 402 and the center dummy trace 405 in the second direction X. There is no opposite portion of the dummy trace 515 in the second direction X with respect to the first voltage trace and the second voltage trace.
As an example, the plurality of dummy traces further includes a dummy trace 410, a dummy trace 411, a dummy trace 412, and a dummy trace 413 that are not directly adjacent to the first voltage trace 401 or the second voltage trace 402.
As an example, the three-dimensional memory device further includes a third voltage trace 414, where the third voltage trace 414 is a low voltage trace and the voltage of the third voltage trace is equal to the voltage of the second voltage trace. The third voltage trace 414 is parallel to the second voltage trace 402, and the third voltage trace 414 is spaced from the second voltage trace 402 by at least one dummy trace.
Of course, the dummy trace not adjacent to the high voltage trace and the low voltage trace on the same straight line may also adopt other layouts, and the low voltage trace not located on the same straight line may also adopt other layouts, and the protection scope of the present invention should not be limited too much here.
Referring to fig. 6, a diagram illustrating simulation results of the three-dimensional memory device shown in fig. 5 is shown. The high voltage HV applied to the first voltage trace 401 is 22V, the low voltage LV applied to the second voltage trace 402 is 0V, the second voltage trace 402 and the third voltage trace 414 are connected by the connection portion 416, the dummy trace 107, the connection portion 114, the dummy trace 111 and the connection portion 115, and a simulation result shows that, due to a coupling effect, the voltage of the first dummy trace 406 is 13.14V, the voltage of the second dummy trace 407 is 5.8V, the voltage of the center dummy trace 405 is 7.8V, the voltage of the third dummy trace 408 is 13.08V, and the voltage of the dummy trace 412 is 5.9. It can be seen that the maximum voltage difference Δ V (22-13.08) V (8.92V) is generated between the first voltage trace 401 and the third dummy trace 408. Compared with the maximum voltage difference of 15.5V of the trace layout shown in fig. 1, the trace layout of the present embodiment greatly reduces the voltage difference between the traces, thereby effectively suppressing the TDDB effect.
The layout of the three-dimensional memory device in this embodiment is equivalent to cutting off the dummy trace 105, the second voltage trace 102 and the dummy trace 107, as compared with the layout of the trace plane shown in fig. 1, wherein cutting off the dummy trace 105 can destroy the relationship between the original dummy trace 105 and the high-voltage trace facing the high-voltage trace, cutting off the second voltage trace 102 is equivalent to changing a part of the original low-voltage trace into the dummy trace, which can destroy the relationship between the original dummy trace 106 and the low-voltage trace facing the high-voltage trace, and cutting off the dummy trace 107 can reduce the length of the dummy trace 107, further optimize the distribution of the coupling voltage, thereby effectively increasing the line-to-line breakdown voltage (Vbd) between the high-voltage trace and the dummy trace, or between the dummy trace and the low-voltage trace without increasing the space between the traces, and is beneficial to effectively controlling the chip area, and the new routing layout is only equivalent to the arrangement of small cut-off points in some routing, and the original high-voltage routing and low-voltage routing cannot be influenced.
Example four
The present embodiment and the third embodiment adopt substantially the same technical solutions, except that in the third embodiment, the first dummy trace has a relative portion with respect to the first voltage trace and the center dummy trace in the second direction X at the same time, the fourth dummy trace has a relative portion with respect to the second voltage trace and the center dummy trace in the second direction X at the same time, in this embodiment, the first dummy trace has a relative portion with respect to the first voltage trace in the second direction X but has no relative portion with respect to the center dummy trace in the second direction X, and the fourth dummy trace has a relative portion with respect to the second voltage trace in the second direction X but has no relative portion with respect to the center dummy trace in the second direction X.
Referring to fig. 7, a layout plan view of a three-dimensional memory device in this embodiment is shown, where the three-dimensional memory device includes a first voltage trace 501, a second voltage trace 502, at least one central dummy trace 505 and a plurality of dummy traces, where the first voltage trace 201 extends along a first direction Y, the first voltage trace 501, the second voltage trace 502 and the central dummy trace 505 are located on a same straight line, the central dummy trace 505 is located between the first voltage trace 501 and the second voltage trace 502, and the plurality of dummy traces are distributed on two sides of the first voltage trace 501 and the second voltage trace 502.
Specifically, the voltage of the second voltage trace is lower than that of the first voltage trace, the first voltage trace 501 serves as a high voltage trace, and the second voltage trace 502 serves as a low voltage trace.
As an example, a page buffer high voltage NMOS transistor is disposed in the three-dimensional memory device, a drain of the transistor is connected below the first voltage trace 501 through a first contact 503, and a source of the transistor is connected below the second voltage trace 502 through a second contact 504.
As an example, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.
Specifically, any one of the dummy traces adjacent to the first voltage trace and the second voltage trace has a relative portion with respect to only one of the first voltage trace and the second voltage trace in a second direction X, or has no relative portion with respect to both the first voltage trace and the second voltage trace in the second direction X, and the second direction X is perpendicular to the first direction Y.
In this embodiment, the plurality of dummy traces includes a first dummy trace 506, a second dummy trace 507, a third dummy trace 508, a fourth dummy trace 509, and a fifth dummy trace 515, where the first dummy trace 506 and the second dummy trace 507 are located on the same straight line, the third dummy trace 508, the fourth dummy trace 509, and the fifth dummy trace 515 are located on the same straight line, the fifth dummy trace 515 is located between the third dummy trace 508 and the fourth dummy trace 509, the first dummy trace 506 and the third dummy trace 508 are located on two opposite sides of the first voltage trace 501, and the second dummy trace 507 and the fourth dummy trace 509 are located on two opposite sides of the second voltage trace 502.
Further, the first dummy trace 506 and the first voltage trace 501 have opposite portions in the second direction X but are not adjacent to opposite portions of the center dummy trace 505 and the second voltage trace 502 in the second direction X, the second dummy trace 507 and the center dummy trace 505 and the second voltage trace 502 have opposite portions in the second direction X, the third dummy trace 508 and the first voltage trace 501 and the center dummy trace 505 have opposite portions in the second direction X but have no dummy opposite portion in the second direction X with the second voltage trace 502, and the fourth dummy trace 509 and the second voltage trace 502 have opposite portions in the second direction X but have no opposite portion in the second direction X with the center dummy trace 505. There is no opposite portion of the dummy trace 515 in the second direction X with respect to the first voltage trace and the second voltage trace.
As an example, the plurality of dummy traces further includes a dummy trace 510, a dummy trace 511, a dummy trace 512, and a dummy trace 513 that are not directly adjacent to the first voltage trace 501 or the second voltage trace 502.
As an example, the three-dimensional memory device further includes a third voltage trace 514, the third voltage trace 514 being a low voltage trace, the third voltage trace having a voltage equal to the voltage of the second voltage trace. The third voltage trace 514 is parallel to the second voltage trace 502, and the third voltage trace 514 is spaced from the second voltage trace 502 by at least one of the dummy trace spacings.
Of course, the dummy trace not adjacent to the high voltage trace and the low voltage trace on the same straight line may also adopt other layouts, and the low voltage trace not located on the same straight line may also adopt other layouts, and the protection scope of the present invention should not be limited too much here.
The wiring plane layout of the three-dimensional memory device of the embodiment optimizes the position of the breakpoint relative to the wiring plane layout of the three-dimensional memory device of the third embodiment, further cuts off the coupling path between the first dummy wiring and the center dummy wiring, and further cuts off the coupling path between the center dummy wiring and the fourth dummy wiring, so that the line-to-line breakdown voltage (Vbd) between the high-voltage wiring and the dummy wiring or between the dummy wiring and the low-voltage wiring can be effectively increased under the condition of not increasing the distance between the wirings, thereby being beneficial to effectively controlling the area of a chip, and the new wiring layout is only equivalent to setting small cut-off points in some wirings, and the original high-voltage wiring and low-voltage wiring can not be influenced.
EXAMPLE five
In this embodiment, a method for manufacturing a three-dimensional memory device is provided, which is used to manufacture the three-dimensional memory device according to any one of the first to fourth embodiments, and includes the following steps:
s1: providing a substrate;
s2: forming a wiring layer above the substrate, wherein the wiring layer comprises a first voltage wiring, a second voltage wiring and a plurality of dummy wirings, the second voltage wiring and the first voltage wiring are positioned on the same straight line, the voltage of the second voltage wiring is lower than that of the first voltage wiring, the dummy wirings are distributed on two sides of the first voltage wiring and the second voltage wiring, all the dummy wirings directly adjacent to the first voltage wiring are not directly adjacent to the second voltage wiring, and all the dummy wirings directly adjacent to the second voltage wiring are not directly adjacent to the first voltage wiring.
As an example, the routing layer may be obtained by forming a conductive layer over the substrate and patterning the conductive layer.
As an example, the routing layer may also be obtained by forming a mask layer having an opening pattern over the substrate and forming a conductive material in the opening pattern.
As an example, the plurality of dummy traces includes a first dummy trace, a second dummy trace, a third dummy trace and a fourth dummy trace that are adjacent to the first voltage trace and the second voltage trace, the first dummy trace and the second dummy trace are located on a same straight line, the third dummy trace and the fourth dummy trace are located on a same straight line, the first dummy trace and the third dummy trace are located on two opposite sides of the first voltage trace and have a relative portion with the first voltage trace in the second direction X, the second dummy trace and the fourth dummy trace are located on two opposite sides of the second voltage trace and have a relative portion with the second voltage trace in the second direction X.
As an example, the three-dimensional memory device further includes at least one center dummy trace, where the center dummy trace is located on the same line as the first voltage trace and the second voltage trace and located between the first voltage trace and the second voltage trace.
As an example, the first dummy trace, the second dummy trace, the third dummy trace and the fourth dummy trace have opposite portions with respect to the center dummy trace in the second direction X. Or the first dummy trace and the fourth dummy trace have no relative part with the center dummy trace in the second direction X, and the second dummy trace and the third dummy trace have relative part with the center dummy trace in the second direction X.
As an example, the plurality of dummy traces further includes a fifth dummy trace, the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.
As an example, a page buffer high voltage NMOS transistor is disposed in the three-dimensional memory device, a drain of the transistor is connected below the first voltage trace through a first contact, and a source of the transistor is connected below the second voltage trace through a second contact.
As an example, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.
As an example, the routing layer further includes a third voltage trace, a voltage of the third voltage trace is equal to a voltage of the second voltage trace, the third voltage trace is parallel to the second voltage trace, and the third voltage trace and the second voltage trace are separated by at least one dummy trace.
As an example, the third voltage trace and the second voltage trace are connected by at least one dummy trace and at least two connection portions, two sides of at least one connection portion are respectively connected with the second voltage trace and one dummy trace, and two sides of at least one connection portion are respectively connected with one dummy trace and the third voltage trace.
The manufacturing method of the device in this embodiment can be used for manufacturing the three-dimensional memory device in any one of the first to fourth embodiments, different routing layer designs can be realized by simply changing the photolithographic pattern, and the manufacturing method has the advantages of simple process and no increase of manufacturing cost.
In summary, in the three-dimensional memory device and the manufacturing method thereof of the present invention, by improving the layout of the traces, the dummy trace adjacent to the high-voltage trace or the low-voltage trace does not face the high-voltage trace and the low-voltage trace at the same time, so that the line-to-line breakdown voltage (Vbd) between the high-voltage trace and the dummy trace or between the dummy trace and the low-voltage trace can be effectively increased without increasing the distance between the traces, the chip area can be effectively controlled, and the original high-voltage trace and low-voltage trace are not affected. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (21)
1. A three-dimensional memory device, comprising:
a first voltage trace extending along a first direction;
the second voltage wire is positioned on the same straight line with the first voltage wire, and the voltage of the second voltage wire is lower than that of the first voltage wire;
a plurality of dummy traces distributed on both sides of the first voltage trace and the second voltage trace, wherein any one of the dummy traces adjacent to the first voltage trace and the second voltage trace has only a relative portion with one of the first voltage trace and the second voltage trace in a second direction, or has no relative portion with both the first voltage trace and the second voltage trace in the second direction, and the second direction is perpendicular to the first direction.
2. The three-dimensional memory device of claim 1, wherein: the plurality of dummy traces include a first dummy trace, a second dummy trace, a third dummy trace and a fourth dummy trace that are adjacent to the first voltage trace and the second voltage trace, the first dummy trace and the second dummy trace are located on the same straight line, the third dummy trace and the fourth dummy trace are located on the same straight line, the first dummy trace and the third dummy trace are located on two opposite sides of the first voltage trace and have a relative portion with the first voltage trace in the second direction, and the second dummy trace and the fourth dummy trace are located on two opposite sides of the second voltage trace and have a relative portion with the second voltage trace in the second direction.
3. The three-dimensional memory device of claim 2, wherein: the three-dimensional memory device further comprises at least one center dummy trace, wherein the center dummy trace, the first voltage trace and the second voltage trace are positioned on the same straight line and are positioned between the first voltage trace and the second voltage trace.
4. The three-dimensional memory device of claim 3, wherein: the first dummy trace, the second dummy trace, the third dummy trace and the fourth dummy trace are all opposite to the central dummy trace in the second direction.
5. The three-dimensional memory device of claim 4, wherein: the dummy traces further include a fifth dummy trace, the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.
6. The three-dimensional memory device of claim 3, wherein: the first dummy trace and the fourth dummy trace have no relative part with the center dummy trace in the second direction, and the second dummy trace and the third dummy trace have relative part with the center dummy trace in the second direction.
7. The three-dimensional memory device of claim 6, wherein: the dummy traces further include a fifth dummy trace, the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.
8. The three-dimensional memory device of claim 1, wherein: the three-dimensional memory device is provided with a page buffer high-voltage NMOS transistor, the drain electrode of the transistor is connected below the first voltage wire through a first contact part, and the source electrode of the transistor is connected below the second voltage wire through a second contact part.
9. The three-dimensional memory device of claim 1, wherein: the voltage of the first voltage wire is greater than or equal to 20V, and the voltage of the second voltage wire is less than or equal to 10V.
10. The three-dimensional memory device of claim 1, wherein: the three-dimensional memory device further comprises a third voltage wire, wherein the voltage of the third voltage wire is equal to the voltage of the second voltage wire, the third voltage wire is parallel to the second voltage wire, and the third voltage wire and the second voltage wire are separated by at least one dummy wire.
11. The three-dimensional memory device of claim 10, wherein: the third voltage wire is connected with the second voltage wire through at least one dummy wire and at least two connecting portions, two sides of at least one connecting portion are respectively connected with the second voltage wire and one dummy wire, and two sides of at least one connecting portion are respectively connected with one dummy wire and the third voltage wire.
12. A method for manufacturing a three-dimensional memory device is characterized by comprising the following steps:
providing a substrate;
forming a wiring layer above the substrate, wherein the wiring layer includes a first voltage trace, a second voltage trace and a plurality of dummy traces, the second voltage trace and the first voltage trace are located on the same straight line, the voltage of the second voltage trace is lower than that of the first voltage trace, the dummy traces are distributed on two sides of the first voltage trace and the second voltage trace, any one of the dummy traces adjacent to the first voltage trace and the second voltage trace has a relative portion only with one of the first voltage trace and the second voltage trace in a second direction, or has no relative portion with both the first voltage trace and the second voltage trace in the second direction, and the second direction is perpendicular to the first direction.
13. The method of fabricating a three-dimensional memory device of claim 12, wherein: and forming a conductive layer above the substrate, and patterning the conductive layer to obtain the routing layer.
14. The method of fabricating a three-dimensional memory device of claim 12, wherein: and forming a mask layer with an opening pattern above the substrate, and forming a conductive material in the opening pattern to obtain the wiring layer.
15. The method of fabricating a three-dimensional memory device of claim 12, wherein: the plurality of dummy traces include a first dummy trace, a second dummy trace, a third dummy trace and a fourth dummy trace that are adjacent to the first voltage trace and the second voltage trace, the first dummy trace and the second dummy trace are located on the same straight line, the third dummy trace and the fourth dummy trace are located on the same straight line, the first dummy trace and the third dummy trace are located on two opposite sides of the first voltage trace and have a relative portion with the first voltage trace in the second direction, and the second dummy trace and the fourth dummy trace are located on two opposite sides of the second voltage trace and have a relative portion with the second voltage trace in the second direction.
16. The method of fabricating a three-dimensional memory device of claim 15, wherein: the three-dimensional memory device further comprises at least one center dummy trace, wherein the center dummy trace, the first voltage trace and the second voltage trace are positioned on the same straight line and are positioned between the first voltage trace and the second voltage trace.
17. The method of fabricating a three-dimensional memory device of claim 16, wherein: the first dummy trace, the second dummy trace, the third dummy trace and the fourth dummy trace are all opposite to the central dummy trace in the second direction.
18. The method of fabricating a three-dimensional memory device of claim 17, wherein: the dummy traces further include a fifth dummy trace, the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.
19. The method of fabricating a three-dimensional memory device of claim 16, wherein: the first dummy trace and the fourth dummy trace have no relative part with the center dummy trace in the second direction, and the second dummy trace and the third dummy trace have relative part with the center dummy trace in the second direction.
20. The method of fabricating a three-dimensional memory device of claim 12, wherein: the dummy traces further include a fifth dummy trace, the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.
21. The method of fabricating a three-dimensional memory device of claim 12, wherein: the substrate is provided with a page buffer high-voltage NMOS transistor, the first voltage wire is connected above the drain electrode of the transistor through a first contact part, and the second voltage wire is connected above the source electrode of the transistor through a second contact part.
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| US20140346677A1 (en) * | 2013-05-21 | 2014-11-27 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| CN107430878A (en) * | 2015-06-30 | 2017-12-01 | 桑迪士克科技有限责任公司 | Nonvolatile memory system and method |
| CN107968047A (en) * | 2017-11-23 | 2018-04-27 | 长江存储科技有限责任公司 | A kind of SADP page buffers cutting-off method and structure |
| CN110098193A (en) * | 2018-01-29 | 2019-08-06 | 爱思开海力士有限公司 | The semiconductor memory system of three-dimensional structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140346677A1 (en) * | 2013-05-21 | 2014-11-27 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| CN107430878A (en) * | 2015-06-30 | 2017-12-01 | 桑迪士克科技有限责任公司 | Nonvolatile memory system and method |
| CN107968047A (en) * | 2017-11-23 | 2018-04-27 | 长江存储科技有限责任公司 | A kind of SADP page buffers cutting-off method and structure |
| CN110098193A (en) * | 2018-01-29 | 2019-08-06 | 爱思开海力士有限公司 | The semiconductor memory system of three-dimensional structure |
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