CN110703870A

CN110703870A - JBOD mainboard and storage system

Info

Publication number: CN110703870A
Application number: CN201910867325.2A
Authority: CN
Inventors: 张帅豪
Original assignee: Suzhou Wave Intelligent Technology Co Ltd
Current assignee: Suzhou Wave Intelligent Technology Co Ltd
Priority date: 2019-09-12
Filing date: 2019-09-12
Publication date: 2020-01-17

Abstract

The application discloses a JBOD mainboard and a storage system. The JBOD mainboard that this application discloses includes: the independent expander chip comprises an uplink port and a downlink port which are connected with the independent expander chip; at least three uplink ports and at least three downlink ports are arranged, and communicated domains are isolated among different uplink ports; configuring a communication domain among different downlink ports; the uplink port is connected with the host through an SAS cable; the downstream port is connected with the lower JBOD mainboard through an SAS cable so as to realize expansion of the JBOD mainboard. The application expands the uplink and downlink ports, reduces the design cost, power consumption, complexity, IO depth and time delay in the use process of the JBOD mainboard, and can not cause the problems of difficulty in heat dissipation and the like. Accordingly, the storage system disclosed by the application also has the technical effects.

Description

JBOD mainboard and storage system

Technical Field

The application relates to the technical field of storage, in particular to a JBOD mainboard and a storage system.

Background

In the prior art, in order to improve the expansion capability of the JBOD motherboard, the JBOD motherboard is usually connected to more subordinate JBOD motherboards, which increases the design cost, power consumption and complexity of the JBOD motherboard, increases the IO depth, and prolongs the time delay in the use process.

Therefore, how to reduce the cost, power consumption and complexity of the JBOD motherboard is a problem to be solved by those skilled in the art.

Disclosure of Invention

In view of the above, an object of the present application is to provide a JBOD motherboard and a storage system, so as to reduce the cost, power consumption and complexity of the JBOD motherboard. The specific scheme is as follows:

in a first aspect, the present application provides a JBOD motherboard, comprising:

the independent expander chip comprises an uplink port and a downlink port which are connected with the independent expander chip;

at least three uplink ports and at least three downlink ports are arranged, and communicated domains are isolated among different uplink ports; configuring a communication domain among different downlink ports;

the uplink port is connected with the host through an SAS cable;

the downstream port is connected with the lower JBOD mainboard through an SAS cable so as to realize expansion of the JBOD mainboard.

Preferably, four uplink ports are provided, which are: the first uplink port and the second uplink port are connected with the host through SAS cables.

Preferably, the first uplink port is connected with a first controller in the host through an SAS cable, and the second uplink port is connected with a second controller in the host through an SAS cable; the first controller and the second controller belong to a first controller group in the host.

Preferably, if the host includes a first controller, a second controller, a third controller and a fourth controller, the third uplink port is connected to the third controller through an SAS cable, and the fourth uplink port is connected to the fourth controller through an SAS cable; the third controller and the fourth controller belong to a second controller group in the host.

Preferably, the host is connected to a copy of the JBOD motherboard by a SAS cable.

Preferably, the independent expander chip is connected with an HDD disk and/or an SSD disk.

Preferably, there are six downstream ports.

Preferably, the upstream port is connected to the SAS switch via an SAS cable, and the SAS switch is connected to the host via an SAS cable.

In a second aspect, the present application provides a storage system comprising: a host and a JBOD motherboard as any of the above.

Preferably, the host is a storage device host and/or a server host.

According to the above technical scheme, the present application provides a JBOD mainboard, includes: the independent expander chip comprises an uplink port and a downlink port which are connected with the independent expander chip; at least three uplink ports and at least three downlink ports are arranged, and communicated domains are isolated among different uplink ports; configuring a communication domain among different downlink ports; the uplink port is connected with the host through an SAS cable; the downstream port is connected with the lower JBOD mainboard through an SAS cable so as to realize expansion of the JBOD mainboard.

Therefore, only one expander chip is arranged in the JBOD mainboard provided by the application, at least three uplink ports and at least three downlink ports are arranged, and different uplink ports are isolated in a communication domain; and communication domains are configured among different downlink ports, so that the uplink ports and the downlink ports are expanded, and the problem of endless loop during scanning the uplink ports is avoided. It should be noted that, when a plurality of uplink ports are set by using an expander chip, if different uplink ports are connected to each other, a problem of dead cycle occurs when scanning the uplink ports, that is: when the current upstream port is scanned, another upstream port is scanned at the same time, so that the scanning operation is difficult to stop. Therefore, the communication domain isolation is carried out between different uplink ports, and the problem can be avoided. Due to the above problems, in the prior art, a plurality of expander chips are often arranged in the JBOD motherboard to realize expansion of uplink and downlink ports, although the IO depth is not increased, the design cost, power consumption and complexity of the JBOD motherboard are still increased, and moreover, when the plurality of expander chips work in the same JBOD motherboard, the JBOD motherboard is over-high in temperature and difficult to dissipate heat. Meanwhile, the JBOD mainboard disclosed by the application is directly connected with the host through the uplink port, so that the use of an SAS switch is avoided, and the storage cost is saved; in addition, the IO depth is not increased by the expansion of the uplink and downlink ports, so that the time delay is not increased. It can be seen that this application can reduce design cost, consumption, complexity, the IO degree of depth and the time delay in the use of JBOD mainboard, still can not bring and be difficult to heat dissipation scheduling problem.

Accordingly, the storage system provided by the application also has the technical effects.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a first JBOD motherboard disclosed in the present application;

FIG. 2 is a schematic diagram of a second JBOD motherboard disclosed in the present application;

fig. 3 is a schematic diagram of a storage system disclosed in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

At present, the prior art can connect more subordinate JBOD mainboards at the JBOD mainboard for improving the expansion capability of the JBOD mainboard, so that the design cost, power consumption and complexity of the JBOD mainboard can be increased, the IO depth can be increased, and the time delay in the using process can be prolonged. Therefore, the JBOD mainboard is provided, and the cost, the power consumption and the complexity of the JBOD mainboard can be reduced.

Referring to fig. 1, an embodiment of the present application discloses a first JBOD motherboard, including: an independent expander chip 101, an upstream port 102 and a downstream port 103 connected to the independent expander chip 101; at least three upstream ports 102 and at least three downstream ports 103 are provided, and at least three upstream ports 102 are any one of the upstream ports 102 as 1021, 1022, and 1023 … … in fig. 1, that is, 1021, 1022, and 1023 … … in fig. 1; at least three downstream ports 103 are any one of the downstream ports 103 as 1031, 1032, 1033 … … in fig. 1, that is, 1031, 1032, 1033 … … in fig. 1, respectively.

Connecting domain isolation is carried out between different uplink ports; configuring a communication domain among different downlink ports; the upstream port 102 is connected to the host 104 via an SAS cable; the downstream port 103 is connected to a lower level JBOD motherboard 105 through an SAS cable to implement expansion of the JBOD motherboard.

Each downstream port is connected to a lower level JBOD motherboard, and 1051, 1052, and 1053 … … in fig. 1 are each any one of the plurality of lower level JBOD motherboards 105.

In one embodiment, a separate expander chip is connected to the HDD disk and/or the SSD disk 106.

In this embodiment, the upstream port may be further connected to the SAS switch through an SAS cable, and the SAS switch is connected to the host through the SAS cable. It is more convenient to connect the upstream port and the host using the SAS switch, although the cost will increase accordingly.

It should be noted that the expander chip is an expansion interconnection chip conforming to the SAS specification, and includes a plurality of phys, one Phy is a transceiver, and each Phy has a corresponding identification number; one expander chip has a unique SASaddress. Each phy is a port for connecting an SAS cable, so that when the expander chip is connected to other devices, the phy is connected. For example: the expander chip is connected to the upstream port 1021, i.e., connected through a certain phy, i.e., each device uniquely corresponds to each phy.

Wherein, a plurality of phy can compose a SAS Port, each SAS Port has a corresponding tag, and different phys in the same SASPort have the same tag but each corresponds to an identification number.

Since this embodiment uses only one expander chip, the expander chip with a large number of phy is preferably selected, for example: PM 8056.

It can be seen that the JBOD motherboard disclosed in this embodiment has only one expander chip, and at least three uplink ports and at least three downlink ports are provided, and different uplink ports are isolated from each other by a communication domain; and communication domains are configured among different downlink ports, so that the uplink ports and the downlink ports are expanded, and the problem of endless loop during scanning the uplink ports is avoided. Meanwhile, the JBOD mainboard disclosed by the application is directly connected with the host through the uplink port, so that the use of an SAS switch is avoided, and the storage cost is saved; in addition, the IO depth is not increased by the expansion of the uplink and downlink ports, so that the time delay is not increased. It can be seen that this application can reduce design cost, consumption, complexity, the IO degree of depth and the time delay in the use of JBOD mainboard, still can not bring and be difficult to heat dissipation scheduling problem.

Referring to fig. 2, an embodiment of the present application discloses a second JBOD motherboard, including: an independent expander chip 201, an upstream port and a downstream port connected to the independent expander chip 201; the uplink ports are four, which are respectively: the first uplink port 2021, the second uplink port 2022, the third uplink port 2023 and the fourth uplink port 2024, and the first uplink port 2021 and the second uplink port 2022 are connected to the host through SAS cables.

In one embodiment, the first upstream port 2021 is connected to a first controller 2031 in the host via an SAS cable, and the second upstream port 2022 is connected to a second controller 2032 in the host via an SAS cable; the first controller 2031 and the second controller 2032 belong to a first controller group in the host.

It is to be understood that if the host includes the first controller 2031, the second controller 2032, the third controller 2033, and the fourth controller 2034, the third upstream port 2023 is connected to the third controller 2033 by an SAS cable, and the fourth upstream port 2024 is connected to the fourth controller 2034 by an SAS cable; the third controller 2033 and the fourth controller 2034 belong to a second controller group in the host computer.

In the present embodiment, six downlink ports are provided, which are respectively 2041, 2042, 2043, 2044, 2045, and 2046 in fig. 2.

Connecting domain isolation is carried out between different uplink ports; configuring a communication domain among different downlink ports; the uplink port is connected with the host through an SAS cable; the downstream port is connected with the lower JBOD mainboard through an SAS cable so as to realize expansion of the JBOD mainboard.

Each downstream port is connected to a lower level JBOD motherboard, and 2051, 2052, 2053, 2054, 2055, and 2056 in fig. 2 are each any one of the plurality of lower level JBOD motherboards.

In one embodiment, a separate expander chip is connected to the HDD disk and/or the SSD disk 206.

As can be seen from the above, the JBOD motherboard disclosed in this embodiment has only one expander chip, and at least three uplink ports and at least three downlink ports are provided, and different uplink ports are isolated from each other by a communication domain; and communication domains are configured among different downlink ports, so that the uplink ports and the downlink ports are expanded, and the problem of endless loop during scanning the uplink ports is avoided. Meanwhile, the JBOD mainboard disclosed by the application is directly connected with the host through the uplink port, so that the use of an SAS switch is avoided, and the storage cost is saved; in addition, the IO depth is not increased by the expansion of the uplink and downlink ports, so that the time delay is not increased. It can be seen that this application can reduce design cost, consumption, complexity, the IO degree of depth and the time delay in the use of JBOD mainboard, still can not bring and be difficult to heat dissipation scheduling problem.

In the following, a storage system provided by an embodiment of the present application is introduced, and a storage system described below and a JBOD motherboard described above may be referred to each other.

The embodiment of the application discloses a storage system, including: host computer and JBOD mainboard as disclosed in any one of the above embodiments. Wherein, the host is a storage device host and/or a server host.

Referring to fig. 3, a copy of the JBOD motherboard, i.e., "Share EXP boards" in fig. 3, is provided in the embodiment of the present application; "Share EXP A" in FIG. 3, JBOD motherboard; "Cluster" is the host, and "StorageEncl 0" is the first controller group; "StorageEncl 1" is the second controller group; "CTR 0" is the first controller, "CTR 1" is the second controller, "CTR 2" is the third controller, "CTR 3" is the fourth controller; "SASHBA" is an implementation form of a SAS connection port.

It should be noted that, if the host deploys the X86 system, the SAS initiator in the X86 system generally provides an SAS connection port or a standard PCIE interface expansion card with a CTRL onboard SAS controller chip, where "SAS HBA" is an implementation form of providing an SAS connection port for the standard PCIE interface expansion card.

P0-P3 are the numbers of the various ports on the host. "X4" and "X25" are the specifications of SAS cables; "EXP1.A" is the lower JBOD mainboard connected with the JBOD mainboard; "EXP 1. B" is the lower JBOD mainboard with the copy of JBOD mainboard connected; each lower level JBOD mainboard can be continuously connected with the next level JBOD mainboard through an EXP0 port.

That is, when the host is connected to the copy of the JBOD motherboard via the SAS cable, the connection can be made with reference to the connection manner of the host to the JBOD motherboard.

The expander chip in this embodiment is PM8056, which has 68 phys. Of course, if the cost is not considered, more expander chips can be arranged in the JBOD motherboard, and then the heat dissipation problem of the JBOD motherboard needs to be considered, such as: more fans are arranged beside the JBOD mainboard or the rotating speed of the fans is increased.

In the embodiment, 4 uplink ports are designed on the JBOD mainboard, such as UP0-UP3 in FIG. 3; 6 downstream ports, such as EXP0-EXP5 in FIG. 3. 4 uplink ports can enable the JBOD mainboard to be simultaneously connected to 4 controllers in an abutting mode; more subordinate JBOD mainboards can be connected with 6 downlink ports, so that the cascade depth is reduced, and the IO depth is reduced. Therefore, phy in PM8056 is utilized to the utmost extent, and the number of uplink and downlink ports is expanded. The asymmetric design can reduce the complexity of the JBOD mainboard and is more suitable for the practical application environment.

It should be noted that, the existing JBOD motherboard generally has only "1 + 1" design: namely an upstream port and a downstream port; or a "2 + 2" design: i.e. two upstream ports and two downstream ports. When the design is 2+2, the problem of the connected domain of the two uplink ports needs to be considered, but because only two uplink ports exist, even if the above mentioned problem of the dead cycle does not matter, but when the number of the uplink ports is large, the problem of the dead cycle greatly affects the JBOD mainboard, so the connected domain isolation is performed between different uplink ports, and the problem is solved.

In FIG. 3, "Share EXP A" and "Share EXP centers" are identical and belong to the first level hard disk frame; "EXP 1.A" and "EXP 1.B" both belong to the second level hard disk box. The first-level hard disk frame can share four controllers in the host, so the second-level hard disk frame connected below the first-level hard disk frame can also share four controllers in the host. Sharing multiple controllers may still provide back-end data services in the event that a portion of the controllers fail. Among them, the JBOD motherboard is an important component of the hard disk frame.

As can be seen from the above, the present embodiment discloses a storage system, which does not need to use an SAS switch, and sets a copy of a JBOD motherboard, and when the JBOD motherboard fails, the copy can be continuously used to provide services, thereby improving the reliability and service capability of the storage system. The single expander chip does not add extra hardware cost and power consumption, and can optimize the overall cost. Under the same condition, the system can reduce the cascade depth, thereby reducing IO paths and having better time delay advantage.

References in this application to "first," "second," "third," "fourth," etc., if any, are intended to distinguish between similar elements and not necessarily to describe a particular order or sequence. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, or apparatus.

It should be noted that the descriptions in this application referring to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of readable storage medium known in the art.

The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1.A JBOD motherboard, comprising:

the uplink port is connected with the host through an SAS cable;

and the downstream port is connected with a lower JBOD mainboard through the SAS cable so as to realize the expansion of the JBOD mainboard.

2. The JBOD motherboard of claim 1, wherein the upstream ports are four, respectively: the SAS port comprises a first uplink port, a second uplink port, a third uplink port and a fourth uplink port, wherein the first uplink port and the second uplink port are connected with the host through the SAS cable.

3. The JBOD motherboard of claim 2, wherein the first upstream port is coupled to a first controller in the host via the SAS cable, and the second upstream port is coupled to a second controller in the host via the SAS cable; the first controller and the second controller belong to a first controller group in the host.

4. The JBOD motherboard of claim 3 wherein if the host comprises the first controller, the second controller, a third controller, and a fourth controller, the third upstream port is connected to the third controller via the SAS cable, and the fourth upstream port is connected to the fourth controller via the SAS cable; the third controller and the fourth controller belong to a second controller group in the host.

5. The JBOD motherboard of claim 4 wherein the host is connected to a copy of the JBOD motherboard by the SAS cable.

6. The JBOD motherboard of claim 1, wherein the standalone expander chip is connected with a HDD disk and/or an SSD disk.

7. The JBOD motherboard of claim 1 wherein there are six downstream ports.

8. The JBOD motherboard of claim 1 wherein the upstream port is coupled to a SAS switch via the SAS cable, the SAS switch coupled to the host via the SAS cable.

9. A storage system, comprising: a host and a JBOD motherboard as claimed in any one of claims 1 to 8.

10. The storage system according to claim 9, wherein the host is a storage device host and/or a server host.