CN110690223A - Embedded memory - Google Patents
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- CN110690223A CN110690223A CN201910911217.0A CN201910911217A CN110690223A CN 110690223 A CN110690223 A CN 110690223A CN 201910911217 A CN201910911217 A CN 201910911217A CN 110690223 A CN110690223 A CN 110690223A
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- H—ELECTRICITY
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- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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Abstract
An embedded memory, comprising: a main processor; an embedded flash memory structure; a plurality of second bare flash structures; the embedded flash memory structure comprises a controller and a plurality of first bare flash memory structures; the first bare flash structures and the second bare flash structures are respectively provided with a flash memory array; the controller comprises a plurality of input ends and a plurality of output ends, and the plurality of output ends comprise a plurality of embedded output ends and a plurality of non-embedded output ends; the embedded output ends are connected with the flash memory arrays in the first bare flash memory structures; the main processor is connected with part of input ends of the controller in the embedded flash memory structure; the flash memory arrays in the second bare flash memory structures are correspondingly connected with the non-embedded output ends of the controllers in the embedded flash memory structures. The embedded memory can reduce the workload of the main processor when expanding capacity, can reduce the signal crosstalk (crosstalk) of the main processor end, only needs one controller, and saves the cost.
Description
Technical Field
The invention relates to the field of memories, in particular to an embedded memory.
Background
NAND flash memory is a better storage device than hard disk drives, and is widely used in electronic products as people seek nonvolatile storage products with low power consumption, light weight and good performance.
After the 3D NAND memory is manufactured, a wafer generally needs to be divided to form a plurality of discrete NAND Flash memory structures, and then the NAND Flash memory structures and a main processor need to be bound on a PCB and connected through a metal line on the PCB to form an embedded memory, where the embedded memory includes an emmc (embedded Multi Media card) memory, a ufs (universal Flash storage) memory, and a BGA SSD (Ball Grid Array SSD) memory according to different interface modes.
In an actual memory product, an embedded flash memory product is connected with a main processor through an embedded interface. Fig. 1 is a schematic diagram of a conventional embedded memory structure, which includes a main processor 11, and an embedded flash memory structure 12 connected to the main processor 11, where the embedded flash memory structure 12 includes a controller 13 and a flash memory array 14 connected to the controller 13, the flash memory array may be, for example, a NAND flash memory array, and a connection interface between the main processor 11 and the controller 13 of the embedded flash memory structure 12 and a connection interface between the controller 13 and the flash memory array 14 are both embedded interfaces. In the actual use process, in order to increase the storage capacity of the embedded memory, it is often necessary to expand the capacity of the embedded memory, but now the expansion of the capacity of the embedded memory becomes more and more difficult, in the existing expansion manner, the number of embedded flash memory structures or products is increased, as shown in fig. 2, a plurality of controllers 13 corresponding to a plurality of embedded flash memory structures or products 12 are respectively connected to the host processor 11 through a plurality of embedded interfaces, which may increase the load (load) of the host processor and easily bring crosstalk (crosstalk) of signals. In addition, the increase of embedded flash memory structures or products results in excessive occupied memory space, occupies additional space and increases packaging burden.
Disclosure of Invention
The technical problem to be solved by the invention is how to reduce the burden of a main processor in an embedded memory and the crosstalk of signals.
The invention provides an embedded memory, comprising:
a main processor;
an embedded flash memory structure;
a plurality of second bare flash structures;
the embedded flash memory structure comprises a controller and a plurality of first bare flash memory structures;
the first bare flash structures and the second bare flash structures are respectively provided with a flash memory array;
the controller comprises a plurality of input ends and a plurality of output ends, and the plurality of output ends comprise a plurality of embedded output ends and a plurality of non-embedded output ends;
the embedded output ends are connected with the flash memory arrays in the first bare flash memory structures;
the main processor is connected with part of input ends of the controller in the embedded flash memory structure;
and the flash memory arrays in the second bare flash memory structures are correspondingly connected with the non-embedded output end of the controller in the embedded flash memory structure.
Optionally, the main processor is configured to send an operation instruction to the embedded flash memory structure and the plurality of second bare flash memory structures, and the controller is configured to analyze the operation instruction and operate a corresponding flash memory array in the embedded flash memory structure or the plurality of second bare flash memory structures according to the analyzed operation instruction.
Optionally, the operation instruction includes a read instruction, a write instruction, and an erase instruction, and the operation includes a read operation, a write operation, and an erase operation.
Optionally, the main processor is further configured to send data to the embedded flash memory structure and the plurality of second bare flash memory structures and receive data read from the embedded flash memory structure and the plurality of second bare flash memory structures.
Optionally, the connection mode between the main processor and the controller of the embedded flash memory structure is parallel connection or asynchronous serial connection.
Optionally, a mode of data transmission between the main processor and the controller of the embedded flash memory structure is a half-duplex mode or a full-duplex mode.
Optionally, the flash memory array is a NAND flash memory array, an MRAM flash memory array, a PRAM flash memory array, an RRAM flash memory array, or a FeRAM flash memory array.
Optionally, the flash memory array in the first bare flash memory structure is of a different type than the flash memory array in the second bare flash memory structure.
Optionally, the flash memory device further comprises a PCB, the PCB is provided with a first circuit and a plurality of second circuits, the main processor, the embedded flash memory structure and the plurality of second bare flash memory structures are located on the PCB, and the main processor is connected with part of input ends of the controller of the embedded flash memory structure through the first circuit; and the flash memory arrays in the second bare flash memory structures are correspondingly connected with the non-embedded output end of the controller in the embedded flash memory structure through a plurality of second lines.
Optionally, the first line and the second line each include a plurality of command transmission lines and data transmission lines.
Optionally, the controller and the plurality of first bare flash memory structures are packaged together through a packaging layer, and the plastic packaging layer exposes a plurality of bonding pads connected with an input interface and a non-embedded output interface of the controller.
Optionally, the plastic package layer has a plurality of interconnections for connecting the plurality of non-embedded output terminals of the controller with the embedded flash memory arrays in the plurality of first bare flash memory structures.
Optionally, the operation priority of the first bare flash structure and the operation priority of the second bare flash structure are preset in the main processor, and the bare flash structure which is read and written preferentially is controlled by the controller.
Optionally, the operation priority is automatically changed according to an actual application situation or an actual operation situation.
Optionally, the operation priority includes preferentially reading and writing the plurality of first bare flash structures, and then reading and writing the plurality of second bare flash structures when the storage capacity reaches a predetermined threshold.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the embedded memory, the embedded flash memory structure comprises the controller and the first bare flash memory structures, the flash memory arrays are arranged in the first bare flash memory structures and the second bare flash memory structures, the controller comprises the input ends and the output ends, the output ends comprise the embedded output ends and the non-embedded output ends, and the embedded output ends are connected with the flash memory arrays in the first bare flash memory structures; the main processor is connected with part of input ends of the controller in the embedded flash memory structure; and the flash memory arrays in the second bare flash memory structures are correspondingly connected with the non-embedded output end of the controller in the embedded flash memory structure. The embedded memory can expand the embedded memory capacity by connecting a plurality of second bare flash memory structures, and the second bare flash memory structures are correspondingly connected with the non-embedded output end of the controller in the embedded flash memory structure and cannot be directly connected with the main processor, so that the workload of the main processor is reduced, the signal crosstalk (crosstalk) of the main processor can be reduced, only one controller is needed, the cost is saved, and the packaging volume can be reduced.
The embedded memory further comprises a PCB board, wherein the PCB board is provided with a first circuit and a plurality of second circuits, the main processor, the embedded flash memory structure and the plurality of second bare flash memory structures are positioned on the PCB board, and the main processor is connected with part of input ends of the controller of the embedded flash memory structure through the first circuits; and the flash memory arrays in the second bare flash memory structures are correspondingly connected with the output ends of other parts of the controller in the embedded flash memory structure through a plurality of second lines. Through setting up the PCB board, can be very easy with main processor, embedded flash memory structure, a plurality of naked flash memory structures of second connect and form embedded memory, and the PCB board can set up a plurality of idle second circuits, and the one end of second circuit is connected with the corresponding output port in the controller, and when the storage capacity of embedded memory needs the dilatation, the other end of second circuit is used for connecting the naked flash memory structure of second that increases newly, is convenient for carry out the dilatation to embedded memory.
Drawings
FIGS. 1-2 are schematic structural diagrams of a conventional embedded memory;
FIG. 3 is a diagram illustrating an embedded memory according to an embodiment of the present invention.
Detailed Description
As mentioned in the background, the corresponding controllers 13 of the embedded flash memory structures or products 12 are connected to the main processor 11 through the embedded interfaces, which may burden (load) the main processor and may cause crosstalk (crosstalk) of signals. In addition, the increase of embedded flash memory structures or products results in excessive occupied memory space, occupies additional space and increases packaging burden.
Therefore, the invention provides an embedded memory, wherein the embedded flash memory structure comprises a controller and a plurality of first bare flash memory structures, the first bare flash memory structures and the second bare flash memory structures are respectively provided with a flash memory array, the controller comprises a plurality of input ends and a plurality of output ends, the output ends comprise an embedded output end and a non-embedded output end, and the embedded output end is connected with the flash memory arrays in the first bare flash memory structures; the main processor is connected with part of input ends of the controller in the embedded flash memory structure; and the flash memory arrays in the second bare flash memory structures are correspondingly connected with the non-embedded output end of the controller in the embedded flash memory structure. The embedded memory can expand the embedded memory capacity by connecting a plurality of second bare flash memory structures, and the second bare flash memory structures are correspondingly connected with the non-embedded output end of the controller in the embedded flash memory structure and cannot be directly connected with the main processor, so that the workload of the main processor is reduced, the signal crosstalk (crosstalk) of the main processor can be reduced, only one controller is needed, the cost is saved, and the packaging volume can be reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Example one
FIG. 3 is a diagram illustrating an embedded memory according to an embodiment of the present invention.
Referring to fig. 3, the embedded memory of the present embodiment includes: the flash memory comprises a main processor 101, an embedded flash memory structure 201 and a plurality of second bare flash memory structures 301, wherein the embedded flash memory structure 201 comprises a controller 202 and a plurality of first bare flash memory structures 203, the plurality of first bare flash memory structures 203 are provided with flash memory arrays 21, the plurality of second bare flash memory structures 301 are provided with flash memory arrays 31, the controller 202 comprises a plurality of input ends 205 and a plurality of output ends, the plurality of output ends 206 comprise embedded output ends 206 and non-embedded output ends 207, and the embedded output ends 206 are connected with the flash memory arrays 21 in the plurality of first bare flash memory structures 203;
in the present embodiment, only one embedded flash memory structure 201 is shown. In other embodiments, there may be several embedded flash memory structures 201, and each embedded flash memory structure 201 may include several first bare flash memory structures 203 and connect several second bare flash memory structures 301.
The host processor 101 is coupled to a portion of the input 205 of the controller 202 in the embedded flash memory structure 201.
The flash memory array 21 in the embedded flash memory structure 201 is an embedded flash memory array, and the flash memory arrays 31 in the second bare flash memory structures 301 are non-embedded flash memory arrays and are independent of the embedded flash memory array 21. The second bare flash structures 301 are also independent of each other. In other embodiments, the first bare flash structures and the second bare flash structures form a whole, and storage tasks are coordinated to be completed. The number of the first bare flash structures 203 in the embedded flash memory structure 201 is one or more than one, and the number of the second bare flash structures 301 is one or more than one.
The flash arrays 3131 in the number of second bare flash structures 301 are correspondingly connected to the non-embedded outputs 206 of the controller 202 in the embedded flash structure 201.
In this embodiment, the plurality of first bare flash structures 203 and the plurality of second bare flash structures 301 are both NAND flash structures, and the flash memory arrays in the plurality of corresponding first bare flash structures 203 and the plurality of second bare flash structures 301 are NAND flash arrays. In other embodiments, the flash memory arrays in the first bare flash memory structures 203 and the second bare flash memory structures 301 may also be NOR flash memory arrays, MRAM flash memory arrays, PRAM flash memory arrays, RRAM flash memory arrays, or FeRAM flash memory arrays.
In other embodiments, flash array 31 and flash array 21 may be the same or may be different types of flash arrays. Meanwhile, the types of the flash memory arrays 21 in the first bare flash memory structure 201 may or may not be the same. The flash array 31 types in the number of second bare flash structures 301 may or may not be identical. For example: flash array 21 is a NAND flash memory and flash array 31 is an MRAM flash array or the like. Based on this, the embedded memory can control multiple types of flash memory arrays through the same controller, and the storage advantages of multiple storage types can be fully utilized. For example, the operation priorities of the first bare flash memory structure and the second bare flash memory structure are preset in the main processor, the bare flash memory structure which is read and written preferentially is controlled by the controller, the operation priorities can be changed according to actual application conditions or actual operation conditions such as data to be stored, environment and the like, the change can be automatic change or manual change by an operator, in a specific embodiment, the operation priorities include that the first bare flash memory structures are read and written preferentially, and the second bare flash memory structures are read and written when the storage capacity reaches a preset threshold.
A plurality of first bare Flash structures (Raw Flash Product)203 and second bare Flash structures 301 are all manufactured through a semiconductor integration process, and the specific process comprises the following steps: firstly, forming a plurality of flash memory structures and a plurality of bonding pads connected with the flash memory structures on a wafer through a semiconductor process, wherein the bonding pads are used for connecting an external chip or circuit with the flash memory structures; then cutting the wafer to form a plurality of separated flash memory particles; and then packaging each flash memory particle by adopting a plastic packaging layer, wherein the plastic packaging layer exposes the bonding pads to form a plurality of bare flash memory structures. It should be noted that the middle bare flash memory structure (the first bare flash memory structures 203 and the second bare flash memory structure 301) of the present invention is a flash memory chip having only a flash memory array and related (simple) peripheral circuits, and such a flash memory chip has a relatively simple manufacturing process, high manufacturing efficiency, low manufacturing cost, and is convenient for mass production.
In one embodiment, the NAND flash memory structure comprises: a semiconductor substrate; the semiconductor device comprises a semiconductor substrate, a control gate, an isolation layer and a stacked structure, wherein the control gate and the isolation layer are stacked on the semiconductor substrate, and the stacked structure comprises a core region and a step region positioned on one side of the core region; a plurality of via holes through the stacked structure of the core region; a channel hole storage structure in a channel hole, the channel hole storage structure comprising a charge storage layer on a sidewall surface of the channel hole and a channel layer on a surface of a charge storage sidewall; a plurality of array common sources penetrating through the stacked structure of the core region and the step region; a dielectric layer overlying the stacked structure; the contact plugs are positioned in the dielectric layer and connected with different step areas; a plurality of word lines located on the dielectric layer and connected with the corresponding contact plugs; a corresponding number of bit lines connected to the channel hole storage structure (channel layer) in each channel hole.
The charge storage layer comprises a blocking oxide layer positioned on the surface of the side wall of the channel hole, a charge trapping layer positioned on the surface of the side wall of the blocking oxide layer and a tunneling oxide layer positioned on the surface of the side wall of the charge trapping layer; the channel layer fills the remaining channel holes.
The material of the semiconductor substrate may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate is single crystal silicon (Si).
The isolation layer may be made of one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. In this embodiment, the isolation layer is made of silicon oxide.
The control grid comprises a high-K dielectric layer and a metal grid positioned on the surface of the high-K dielectric layer, and the metal grid can be made of one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni. HfO as the material of the high-K dielectric layer2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO. In other embodiments, the control gate may include a silicon oxide dielectric layer and a polysilicon gate overlying the dielectric layer.
Embedded Flash memory structure (Embedded Flash Product)201 includes controller 202 and a plurality of first bare Flash memory structure 203, and is specific Embedded Flash memory structure 201 is the packaging structure that controller 202 and a plurality of first bare Flash memory structure 203 encapsulate together. The controller 202 is also a semiconductor chip fabricated by a semiconductor integrated manufacturing process on a wafer, and after the wafer fabricated with a plurality of controllers is divided and packaged to form a plurality of discrete controllers 202, the controller 202 and the first bare flash memory structures 203 are encapsulated together by a plastic encapsulation layer, the plastic packaging layer can be made of epoxy resin, polyimide, benzocyclobutene and polybenzoxazole, the molding compound has interconnects therein connecting the controller embedded output 206 with the flash memory arrays 21 in the first bare flash structures 203, the molding compound exposes pads connected to the input interface and non-embedded output 207 of the controller 202, each of which may have solder balls formed thereon, which may then be soldered to corresponding metal traces on the PCB, such that controller 202 is coupled to host processor 101 and number of second bare flash structures 301.
The controller 202 includes a plurality of input terminals 205 and a plurality of output terminals, the plurality of output terminals 206 includes an embedded output terminal 206 and a non-embedded output terminal 207, a portion of the input terminals 205 are connected to the main processor 101, the embedded output terminal 206 is connected to the flash memory arrays 21 in the plurality of first bare flash memory structures 203, and the non-embedded output terminal 207 is correspondingly connected to the flash memory arrays 31 in the plurality of second bare flash memory structures 301. It should be noted that the number of the input terminals 205 and the output terminals of the controller 202 is set according to the requirement, and particularly, the number of the non-embedded output terminals 207 is set according to the number of the second bare flash structure 301 additionally connected as required.
The Host Processor (Host Processor)101 is configured to send an operation instruction to the embedded flash memory structure 201 and the plurality of second bare flash memory structures 301, and the controller 202 is configured to analyze the operation instruction and operate a corresponding flash memory array in the embedded flash memory structure 201 or the plurality of second bare flash memory structures 301 according to the analyzed operation instruction.
The operation instructions comprise a reading instruction, a writing instruction and an erasing instruction, and the operation comprises a reading operation, a writing operation and an erasing operation.
The host processor 101 is further configured to send data to the embedded flash memory structure 201 and the plurality of second bare flash memory structures 301 and receive data read from the embedded flash memory structure 201 and the plurality of second bare flash memory structures 301.
In one embodiment, the host processor 101 is connected to the controller 202 of the embedded flash memory structure 201 in a parallel connection or an asynchronous serial connection. A mode of data transmission between the main processor 101 and the controller 202 of the embedded flash memory structure 201 is a half-duplex mode or a full-duplex mode, and in a specific embodiment, when the connection mode between the main processor 101 and the controller 202 of the embedded flash memory structure 201 is parallel connection, the mode of data transmission between the main processor 101 and the controller 202 of the embedded flash memory structure 201 is a half-duplex mode; when the connection mode between the main processor 101 and the controller 202 of the embedded flash memory structure 201 is asynchronous serial connection, the mode of data transmission between the main processor 101 and the controller 202 of the embedded flash memory structure 201 is full duplex mode.
According to the embedded memory, the embedded flash memory structure 201 comprises a controller 202 and a plurality of first bare flash memory structures 203, the flash memory arrays 21 are arranged in the first bare flash memory structures 203 and the second bare flash memory structures 301, the controller 202 comprises a plurality of input ends 205 and a plurality of output ends, the output ends 206 comprise embedded output ends 206 and non-embedded output ends 207, and the embedded output ends 206 are connected with the flash memory arrays 21 in the first bare flash memory structures 203; the main processor 101 is connected with a part of input terminals 205 of the controller 202 in the embedded flash memory structure 201; the flash arrays 31 in the second plurality of bare flash structures 301 are correspondingly coupled to the non-embedded output 207 of the controller 202 in embedded flash structure 201. That is, the embedded memory of the present invention can expand the embedded storage capacity by connecting the plurality of second bare flash structures 301, and since the plurality of second bare flash structures 301 are correspondingly connected to the non-embedded output 207 of the controller 202 in the embedded flash structure 201 and are not directly connected to the main processor 101, the workload of the main processor 101 is reduced, the signal crosstalk (crosstalk) at the main processor 101 end can be reduced, and only one controller 202 is needed, thereby saving the cost and reducing the volume of the package.
In an embodiment, the embedded memory further includes a PCB 401, the PCB 401 has a first line 401 and a plurality of second lines 402, the main processor 101, the embedded flash memory structure 201 and the plurality of second bare flash memory structures 301 are located on the PCB 401, and the main processor 101 is connected to a part of the input end 205 of the controller 202 of the embedded flash memory structure 201 through the first line 401; the flash memory arrays 31 in the second bare flash structures 301 are correspondingly connected to the non-embedded output 2076 of the controller 202 in the embedded flash structure 201 through second lines 402. By arranging the PCB 401, the main processor 101, the embedded flash memory structure 201, and the plurality of second bare flash memory structures 301 can be easily connected to form an embedded memory, and the capacity of the embedded memory can be conveniently expanded.
Several second bare flash structures 301 are connected to corresponding outputs in the controller 202 via different second lines 402. The PCB 401 may be provided with a plurality of idle second lines 402, one end of each second line 402 is connected to a corresponding non-embedded output terminal 207 in the controller 202, and when the storage capacity of the embedded memory needs to be expanded, the other end of each second line 402 is used to connect to the newly added second bare flash memory structure 301.
The first circuit 401 and the second circuit 402 each include a plurality of metal circuits located in the PCB 401 or on the surface of the PCB 401. In an embodiment, the first line 401 and the second line 402 each include a plurality of command transmission lines and data transmission lines.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (15)
1. An embedded memory, comprising:
a main processor;
an embedded flash memory structure;
a plurality of second bare flash structures;
the embedded flash memory structure comprises a controller and a plurality of first bare flash memory structures;
the first bare flash structures and the second bare flash structures are respectively provided with a flash memory array;
the controller comprises a plurality of input ends and a plurality of output ends, and the plurality of output ends comprise a plurality of embedded output ends and a plurality of non-embedded output ends;
the embedded output ends are connected with the flash memory arrays in the first bare flash memory structures;
the main processor is connected with part of input ends of the controller in the embedded flash memory structure;
and the flash memory arrays in the second bare flash memory structures are correspondingly connected with the non-embedded output end of the controller in the embedded flash memory structure.
2. The embedded memory of claim 2, wherein the main processor is configured to send an operation instruction to the embedded flash memory structure and the second bare flash memory structures, and the controller is configured to parse the operation instruction and operate a corresponding flash memory array of the embedded flash memory structure or the second bare flash memory structures according to the parsed operation instruction.
3. The embedded memory of claim 2, wherein the operation instructions include a read instruction, a write instruction, and an erase instruction, the operations including a read operation, a write operation, and an erase operation.
4. The embedded memory of claim 2, wherein the main processor is further to send data to and receive data read from the embedded flash memory structure and the number of second bare flash memory structures.
5. The embedded memory of claim 1, wherein the host processor is connected to the controller of the embedded flash memory structure in a parallel connection or an asynchronous serial connection.
6. The embedded memory of claim 5, wherein a mode in which data is transmitted between the host processor and the controller of the embedded flash memory structure is a half-duplex mode or a full-duplex mode.
7. The embedded memory of claim 1, wherein the flash memory array is a NAND flash memory array, an MRAM flash memory array, a PRAM flash memory array, an RRAM flash memory array, or an FeRAM flash memory array.
8. The embedded memory of claim 1 or 7, wherein the flash memory array in the first bare flash memory structure is of a different type than the flash memory array in the second bare flash memory structure.
9. The embedded memory of claim 1, further comprising a PCB board having a first trace and a plurality of second traces thereon, wherein the host processor, the embedded flash memory structure and the plurality of second bare flash memory structures are located on the PCB board, and wherein the host processor is connected to a portion of an input terminal of a controller of the embedded flash memory structure via the first trace; and the flash memory arrays in the second bare flash memory structures are correspondingly connected with the non-embedded output end of the controller in the embedded flash memory structure through a plurality of second lines.
10. The embedded memory of claim 9, wherein the first line and the second line each include a number of command transmission lines and data transmission lines.
11. The embedded memory of claim 1, wherein the controller and the number of first bare flash structures are packaged together by a packaging layer that exposes a number of pads that connect to an input interface and a non-embedded output interface of the controller.
12. The embedded memory of claim 11, wherein the molding layer has interconnects therein connecting the non-embedded outputs of the controller to the embedded flash memory arrays in the first bare flash memory structures.
13. The embedded memory according to claim 11, wherein the operation priority of the first bare flash memory structure and the second bare flash memory structure is preset in the main processor, and the bare flash memory structure that is preferentially read and written is controlled by the controller.
14. The embedded memory of claim 13, wherein the operating priority is automatically changed according to actual application conditions or actual operating conditions.
15. The embedded memory of claim 13, wherein the operational priority comprises preferentially reading and writing the number of first bare flash memory structures and re-reading and writing the number of second bare flash memory structures when a storage capacity reaches a predetermined threshold.
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| CN201910911217.0A CN110690223B (en) | 2019-09-25 | 2019-09-25 | Embedded memory |
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