KR20090127023A - Memory device of multi-layer structure and method for driving thereof - Google Patents

Abstract

PURPOSE: A multi-layered memory device and an operation method thereof are provided to improve operation performance of the memory device, by enabling at least one memory cell array to perform read/write operation at the same time. CONSTITUTION: A first semiconductor substrate(10) has a memory cell array comprising a number of memory cells. A second semiconductor substrate(20) is stacked on the first semiconductor substrate, and has a bit line and a page buffer connected to the bit line in correspondence to the memory cell array. A bit line contact is formed between the first semiconductor substrate and the second semiconductor substrate. The bit line contact connects the page buffer and memory cell array.

Description

Memory device of multi-layer structure and method for driving thereof

Embodiments of the present invention relate to a multi-layered memory device and a method of operating the same, and more particularly, to a multi-layered memory device and a method of operating the memory cell array and the page buffer stacked on different semiconductor substrates.

A flash memory device is a type of nonvolatile memory device that can maintain stored information regardless of power supply. Unlike other nonvolatile memory devices, ROM, an electronic device can quickly and easily change stored information. Has

Flash memory devices may be classified into a NOR type structure and a NAND type structure according to a method in which memory cells are connected to a bit line and a source line.

Here, the NAND flash memory device (hereinafter, NAND flash) has a structure in which memory cells are connected in series between a bit line and a common source line. In other words, the NAND flash cell array includes a plurality of memory cell arrays, and each memory cell array includes a plurality of memory cells connected in series.

Due to the serial connection structure of the NAND flash, the NAND flash can have the highest degree of integration among existing semiconductor devices, and adopts an operation method of simultaneously changing the information stored in the plurality of memory cells, thereby updating the information. The speed may be faster than the NOR flash.

However, in the NAND flash, the page buffer and the memory cell array are formed on the same plane, and the bit lines are shared as much as possible in one page buffer in order to increase the density of the memory cell array. Accordingly, the program operation or the read operation of the NAND flash may be limited by the resistance component and the capacitor component of the bit line.

In addition, in order to overcome the above problem, a method of adding a page buffer is used, but this increases the size of the NAND flash, thereby lowering the density of the memory cell array.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device having a multilayer structure that can improve the degree of integration and improve the operation reliability.

Another object of the present invention is to provide a method of operating a memory device having such a multilayer structure.

According to one or more exemplary embodiments, a memory device having a multilayer structure includes a first semiconductor substrate having at least one memory cell array including a plurality of memory cells and a first semiconductor substrate, A bit line and at least one page buffer connected to the bit line are formed between the second semiconductor substrate and the first semiconductor substrate and the second semiconductor substrate formed to correspond to the memory cell array, and bits connecting the page buffer and the memory cell array. It includes a line contact.

According to another aspect of the present invention, there is provided a memory device having a multilayer structure including a first semiconductor substrate having at least one pair of memory cell arrays having a plurality of memory cells, and a first semiconductor substrate. A second semiconductor substrate stacked on the bit line and at least one page buffer connected to the bit line; and a sub bit line formed between the first semiconductor substrate and the second semiconductor substrate; A bit line contact is formed between the first semiconductor substrate and the second semiconductor substrate and connects at least one page buffer and a pair of memory cell arrays.

According to another aspect of the present invention, there is provided a method of operating a memory device having a multilayer structure, wherein a first page buffer operates in response to a first control signal output from a controller, Sending and receiving first data; and operating a second page buffer in response to a second control signal output from a controller, and sending and receiving second data with a second memory cell array. Operate simultaneously with the first page buffer to exchange second data with the second memory cell array, or operate while the first page buffer and the first memory cell array transmit and receive first data to operate the second memory cell array. Send and receive second data.

According to another aspect of the present invention, there is provided a method of operating a memory device having a multi-layer structure, wherein a first page buffer operates in response to a first control signal output from a controller. The second page buffer is operated in response to the second control signal output from the controller during the step of exchanging the first data and the operation of exchanging the first data between the first page buffer and the first memory cell array. A third control signal output from the controller when the second page buffer receives and stores the second data through the bit line and the first page buffer and the first memory cell array exchange the first data; In response, the second page buffer transmits the second data to the first page buffer via the bit line.

According to the multi-layered memory device and its operation method, a semiconductor device having at least one page buffer and a semiconductor substrate having at least one memory cell array are stacked to correspond to each other to form a memory device having a multi-layered structure. In addition, there is an effect of improving the integration degree of the memory cell array and reducing the resistance component and the capacitor component of the bit line to improve the operation reliability of the memory device.

In addition, the operation of at least one page buffer may be independently controlled, and thus, the at least one memory cell array may simultaneously perform read / write operations, thereby improving operation performance of the multi-layered memory device. It can be effective.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the embodiments of the present invention, reference should be made to the accompanying drawings which illustrate embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a memory device having a multilayer structure according to an embodiment of the present invention, and FIG. 2A is a circuit diagram of one memory cell array among the plurality of memory cell arrays shown in FIG. 1, and FIG. A schematic block diagram of one page buffer of the plurality of page buffers shown in FIG. 1 is shown.

Referring to FIG. 1, a memory device 100 having a multilayer structure includes a memory region A in which a plurality of memory cell arrays 10_1, 10_2,... 10_N are formed, and a plurality of page buffers 20_1, 20_2,... The formed page buffer regions B may be provided in different semiconductor substrates 10 and 20, and may be stacked to correspond to each other.

A plurality of memory cell arrays 10_1, 10_2,... 10_N may be formed in the first semiconductor substrate 10 of the memory area A, respectively. Each of the plurality of memory cell arrays 10_1, 10_2,... 10_N may be connected to each of the plurality of page buffers 20_1, 20_2,... 20_N formed in the second semiconductor substrate 20 of the page buffer area B. Member, for example, via a bit line contact 30 to be described below.

2A illustrates one memory cell array 10_N among the plurality of memory cell arrays 10_1, 10_2,... 10_N. In the present exemplary embodiment, only one memory cell array 10_N is shown among the plurality of memory cell arrays 10_1, 10_2,... 10_N illustrated in FIG. 1, but the remaining memory cell arrays 10_1, 10_2 illustrated in FIG. 1 are illustrated. ) Is also substantially the same as the structure of one memory cell array 10_N shown in Figure 2a.

Referring to FIG. 2A, a plurality of memory cells MC, for example, a plurality of memory cells MC formed of a plurality of memory cell transistors MC may be arranged in the memory cell array 10_N. The plurality of memory cells MC may be connected to the row decoder 50 through a plurality of word lines WL0, WL1,..., WLn-1, WLn, respectively.

An active region AR may be formed in the memory cell array 10_N, and a string select line SSL, a ground select line GSL, and a common source line CSL may be arranged perpendicularly to the active region AR. have.

A plurality of word lines WL0, WL1,... WLn-1, WLn may be arranged between the string select line SSL and the ground select line GSL.

In the active area AR, a plurality of memory cells MC connected to each of the plurality of word lines WL0, WL1,... WLn-1, and WLn may be arranged, and a string selection connected to the string selection line SSL may be arranged. The ground select transistor GST connected to the transistor SST and the ground select line GSL may be arranged.

The string select transistor SST, the plurality of memory cells MC, and the ground select transistor GST may be connected in series to form one string S. The drain of the string select transistor SST of the string S is connected to the bit line BL of the page buffer region B to be described later through the bit line contact 30. The source of the ground select transistor GST is connected to the common source line CSL.

Referring back to FIG. 1, a plurality of page buffers 20_1, 20_2,... 20_N may be formed on the semiconductor substrate of the page buffer area B so as to correspond to the plurality of memory cell arrays 10_1, 10_2. have.

2B shows a schematic block diagram of one page buffer 20_N out of a plurality of page buffers 20_1, 20_2,... 20_N. Although only one page buffer 20_N is shown among the plurality of page buffers 20_1, 20_2,... 20_N illustrated in FIG. 1, the remaining page buffers 20_! And 20_2 shown in FIG. ) Is also substantially the same as the structure of one page buffer 20_N shown in Figure 2b.

Referring to FIG. 2B, the page buffer 20_N may include a register circuit 22 and a bit line select circuit 21. One side of the page buffer 20_N is connected to the bit line BL, and the other side of the page buffer 20_N is connected to the memory area illustrated in FIGS. 1 and 2A through a pair of connection members, for example, a pair of bit line contacts 30a and 30b. Memory cell array 10_N in (A).

The register circuit 22 includes a precharge circuit 22c, a sensing circuit 22b, and a latch circuit 22a. The sensing circuit 22b may include a plurality of NMOS transistors. In addition, although not shown in the drawings, the register circuit 22 may further include a plurality of switches (not shown) and a reset circuit (not shown).

The bit line select circuit 21 may include, for example, a plurality of NMOS transistors.

In the above-described page buffer 20_N, the bit line selection circuit 21 may close one bit line contact 30a or 30b of the pair of bit line contacts 30a and 30b during a read (read) operation or a program operation. A sensing node (not shown) of the sensing circuit 22b is connected.

The register circuit 22 senses and stores read data from one bit line contact 30a or 30b connected to the sensing node. In addition, the register circuit 22 may include a memory cell array connected to one bit line contact 30a or 30b of the pair of bit line contacts 30a and 30b, for example, the memory cell array 10_N shown in FIG. 2A. Save the data to be programmed in.

That is, the read data is transferred to the register circuit 22 through the sensing node or the program data is transferred to one bit line contact 30a or 30b of the pair of bit line contacts 30a and 30b through the sensing node. Can be.

Referring back to FIG. 1, the row decoder 50 is connected to the memory area A, so that the plurality of word lines WL0, each of the plurality of memory cell arrays 10_1, 10_2. Signals can be transmitted to WL1, ..., WLn-1, WLn).

3 is a cross-sectional view of a semiconductor device having a multilayer structure according to an embodiment of the present invention.

1 to 3, the multi-layered memory device 100 of the present exemplary embodiment may include a first semiconductor substrate 10 having a memory region A and a second semiconductor substrate 20 having a page buffer region B. Referring to FIGS. ) May be stacked to correspond to each other.

The first semiconductor substrate 10 and the second semiconductor substrate 20 may be made of any one or more semiconductor materials selected from Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, InP, and the like, but is not limited thereto. It is also possible to use an SOI substrate.

In addition, a plurality of wells (not shown) may be formed in the first semiconductor substrate 10 or the second semiconductor substrate 20. Such a plurality of wells may optimize characteristics of a plurality of transistors formed in the first semiconductor substrate 10 or the second semiconductor substrate 20. For example, a pocket p well may be formed in the first semiconductor substrate 10, and n wells and p wells may be formed in the second semiconductor substrate 20, respectively.

A plurality of gate structures, for example, a plurality of first and second gate structures 13 and 15 may be formed in the first semiconductor substrate 10. The plurality of first gate structures 13 and the plurality of second gate structures 15 may be formed through, for example, a photolithography process.

The first gate structure 13 corresponds to the gate structure of each of the plurality of memory cells MC shown in FIG. 2A, and the second gate structure 15 corresponds to the string select transistor SST or the ground select shown in FIG. 2A. It may correspond to the transistor GST.

The first gate structure 13 and the second gate structure 15 may be formed of, for example, a plurality of metal film patterns, for example, polysilicon, tungsten (W), titanium nitride (TiN), tantalum (Ta), or tantalum nitride ( TaN) or a plurality of metal film patterns formed of a composite film thereof may be formed in a stacked structure sequentially.

Heights of the first gate structure 13 and the second gate structure 15 may be substantially similar, but are not limited thereto. However, when the heights of the first gate structure 13 and the second gate structure 15 are substantially similar, the chemical mechanical polishing during the process of forming the first gate structure 13 and the second gate structure 15 is performed. In the Polishing (CMP) process, height detection of endpoints, for example, the first gate structure 13 and the second gate structure 15 may be facilitated.

A plurality of first junction regions 17 may be formed in the first semiconductor substrate 10 exposed by the plurality of first gate structures 13 and the second gate structures 15. The plurality of first junction regions 17 may be formed by implanting impurities in the exposed first semiconductor substrate 10.

The plurality of first gate structures 13 and the second gate structures 15 share the first junction region 17 with each other. In other words, the string select transistor SST, the plurality of memory cell transistors MC, and the ground select transistor GST shown in FIG. 2A are connected in series in a form of sharing the first junction region 17 with each other. S) can be configured.

In addition, the string S is connected to the bit line BL of the page buffer area B through the first bit line junction area 17a and the bit line contact 30 to be described later among the plurality of first junction areas 17. Can be connected. In particular, the second gate structures 15 of the pair of neighboring strings S, for example, the string select transistors SST, may be formed to share one first bit line junction region 17a. .

An interlayer insulating layer 19 is formed on the plurality of first gate structures 13, the plurality of second gate structures 15, and the plurality of first junction regions 17. The interlayer insulating layer 19 may be formed at a height capable of covering the plurality of first gate structures 13 and the plurality of second gate structures 15.

The first bit line contact 31 etches a predetermined region of the interlayer insulating layer 19, for example, an area of the interlayer insulating layer 19 corresponding to the first bit line junction region 17a of the plurality of first junction regions 17. Can be formed. In other words, the first bit line contact 31 may be removed by etching the interlayer insulating layer 19 formed on the first bit line junction region 17a and connected to the exposed first bit line junction region 17a. It can be formed of a conductive material, such as vias or plugs. That is, the first bit line contact 31 may be formed between the first bit line junction region 17a and the second semiconductor substrate 20 formed in the first semiconductor substrate 10.

The first gate structure 13, the second gate structure 15, the first junction region 17, the first bit line junction region 17a, the interlayer insulating layer 19, and the first bit line contact 31 described above. The first semiconductor substrate 10 may be completed.

The second semiconductor substrate 20 may be bonded and stacked on the first semiconductor substrate 10. The second semiconductor substrate 20 may be bonded onto the first semiconductor substrate 10 by, for example, a silicon bonding process.

The second semiconductor substrate 20 includes one string S including the plurality of first gate structures 13 and the plurality of second gate structures 15 of the first semiconductor substrate 10 described above, that is, FIG. 2A. A page buffer 20_N shown in FIG. 2B may be formed corresponding to one memory cell array 10_N shown in FIG.

A plurality of third gate structures 23 may be formed on the second semiconductor substrate 20. Here, the plurality of third gate structures 23 may correspond to a plurality of driving transistors (not shown) formed in the page buffer 20_N.

The third gate structure 23 is formed of, for example, a plurality of metal film patterns, for example, polysilicon, tungsten (W), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) or a composite film thereof. A plurality of metal film patterns may be formed in a stacked structure sequentially.

A plurality of second junction regions 27 is formed in the second semiconductor substrate 20 exposed by the plurality of third gate structures 23. In addition, the plurality of third gate structures 23 share the second junction region 27 with each other. The second junction region 27 may be formed to be substantially the same as the first junction region 17 of the first semiconductor substrate 10. That is, the second junction region 27 may be formed by implanting impurities into the second semiconductor substrate 20 exposed by the third gate structure 23.

The second bit line junction region 27a of the plurality of second junction regions 27 may be positioned to correspond to the first bit line junction region 17a of the first semiconductor substrate 10. The second bit line junction region 27a of the second semiconductor substrate 20 may be connected to the bit line BL to be described later through a bit line contact, for example, a second bit line contact 33.

An interlayer insulating film 29 is formed on the plurality of third gate structures 23 and the plurality of second junction regions 27.

The second bit line contact 33 etches and removes a predetermined region of the interlayer insulating layer 29, for example, the interlayer insulating layer 29 formed on the second bit line junction region 27a, and exposes the exposed second bit line junction region. It may be formed to be connected to (27a). The second bit line contact 33 may be formed of a predetermined conductive material, such as via or plug. That is, the second bit line contact 33 may be formed in the second semiconductor substrate 20 between the bit line BL and the second bit line junction region 27a.

The bit line BL connected to the second bit line contact 33 is formed on the interlayer insulating layer 29.

Meanwhile, the first bit line contact 31 formed on the first semiconductor substrate 10 may be connected to the second bit line contact 33 through another bit line contact, for example, a third bit line contact 35. have.

For example, the third bit line contact 35 may be formed in the second semiconductor substrate 20 between the first bit line contact 31 and the second bit line contact 33. In other words, one side of the third bit line contact 35 formed on the second semiconductor substrate 20 is connected to one side of the first bit line contact 31, and the other side is connected to one side of the second bit line contact 33. Can be connected. Accordingly, the first bit line contact 31 may be connected to the second bit line contact 33 through the third bit line contact 35. The third bit line contact 35 may be a via formed in the second semiconductor substrate 20.

The second semiconductor substrate including the plurality of third gate structures 23, the plurality of second junction regions 27, the interlayer insulating layer 29, the second bit line contacts 33, and the bit lines BL. 20 can be completed.

Thereafter, according to process steps well known to those skilled in the art of semiconductor devices, forming a plurality of steps, for example, wirings to enable input and output of an electrical signal, and packaging the semiconductor substrates. The memory device of a multi-layer structure can be completed by performing the operation.

In the multi-layered memory device 100 of the present embodiment, a plurality of page buffers 20_1, 20_2,... 20_N and a bit line BL are formed on a semiconductor substrate on which a plurality of memory cell arrays 10_1, 10_2,... 10_N are formed. ) Is formed by stacking other semiconductor substrates on which the) is formed, thereby reducing the resistance component and capacitance of the bit line BL driving in each of the plurality of page buffers 20_1, 20_2,..., 20_N, and thus, a plurality of memory cells. The read or program operation efficiency of each of the arrays 10_1, 10_2,... 10_N is increased.

In addition, the plurality of page buffers 20_1, 20_2,... 20_N and the plurality of memory cell arrays 10_1, 10_2,... 10_N are formed on different semiconductor substrates, thereby providing a plurality of memory cell arrays 10_1, 10_2, … The density of 10_N) can be increased.

Hereinafter, a memory device having a multilayer structure according to another exemplary embodiment of the present invention will be described with reference to FIG. 4. FIG. 4 is a cross-sectional view of another example of the memory device having the multilayer structure illustrated in FIG. 3. In the present embodiment, for the convenience of description, members substantially the same as those shown in FIG. 3 are denoted by the same reference numerals, and thus description thereof is omitted.

Referring to FIG. 4, in the memory device 101 of the multilayer structure according to the present exemplary embodiment, the first semiconductor substrate 10 on which the memory region A is formed and the second semiconductor substrate 20 on which the page buffer region B are formed are mutually different. It may be formed to be stacked to correspond.

In the first semiconductor substrate 10, a plurality of gate structures, for example, a plurality of first gate structures 13 and 14 and a plurality of second gate structures 15 and 16 of each of the strings S adjacent to each other, may be formed. Can be. That is, the first semiconductor substrate 10 includes a plurality of gate structures of a pair of memory cell arrays, for example, a plurality of first gate structures 13 and 14, which share the first bit line junction region 17a to be described later. A plurality of second gate structures 15 and 16 may be formed.

Here, each of the plurality of first gate structures 13 and 14 corresponds to a gate structure of the plurality of memory cells MC illustrated in FIG. 2A, and each of the plurality of second gate structures 15 and 16 is illustrated in FIG. 2A. It may correspond to the illustrated string select transistor SST or ground select transistor GST.

A plurality of first junction regions 17 may be formed in the first semiconductor substrate 10 exposed by the plurality of first gate structures 13 and 14 and the second gate structures 15 and 16. The plurality of first junction regions 17 may be formed by implanting impurities in the exposed first semiconductor substrate 10.

The plurality of first gate structures 13 and 14 and the second gate structures 15 and 16 share the first junction region 17 with each other.

In addition, each of the second gate structures 15 and 16 of the pair of neighboring strings S, for example, each of the string select transistors SST, may be formed to share one first bit line junction region 17a. May be

An interlayer insulating layer 19 is formed on the plurality of first gate structures 13 and 14, the plurality of second gate structures 15 and 16, and the plurality of first junction regions 17. The interlayer insulating layer 19 may be formed at a height capable of covering the plurality of first gate structures 13 and 14 and the plurality of second gate structures 15 and 16.

The first bit line contact 31 etches a predetermined region of the interlayer insulating layer 19, for example, an area of the interlayer insulating layer 19 corresponding to the first bit line junction region 17a of the plurality of first junction regions 17. Can be formed. In other words, the first bit line contact 31 may be removed by etching the interlayer insulating layer 19 formed on the first bit line junction region 17a and connected to the exposed first bit line junction region 17a. It can be formed of a conductive material, such as vias or plugs.

On the interlayer insulating film 19, a sub bit line Sub_BL connected to the first bit line contact 31 is formed. The sub bit line Sub_BL may be connected to the first bit line junction region 17a through the first bit line contact 31.

The second semiconductor substrate 20 may be bonded and stacked on the sub bit line Sub_BL of the first semiconductor substrate 10. The second semiconductor substrate 20 may be bonded onto the first semiconductor substrate 10 by, for example, silicon bonding or the like.

The second semiconductor substrate 20 includes a pair of strings S, each of which includes a plurality of first gate structures 13 and a plurality of second gate structures 15 of the first semiconductor substrate 10 described above, that is, One page buffer corresponding to the pair of memory cell arrays may be formed.

A plurality of third gate structures 23 may be formed on the second semiconductor substrate 20. Here, the plurality of third gate structures 23 may correspond to a plurality of driving transistors (not shown) formed in the page buffer.

A plurality of second junction regions 27 is formed in the second semiconductor substrate 20 exposed by the plurality of third gate structures 23. In addition, the plurality of third gate structures 23 share the second junction region 27 with each other. The second junction region 27 may be formed to be substantially the same as the first junction region 17 of the first semiconductor substrate 10.

An interlayer insulating layer 29 is formed on the plurality of third gate structures 23 and the plurality of second junction regions 27.

The second bit line contact 33 etches and removes a predetermined region of the interlayer insulating layer 29, for example, the interlayer insulating layer 29 formed on the second bit line junction region 27a, and exposes the exposed second bit line junction region. It may be formed to be connected to (27a). The second bit line contact 33 may be formed of a predetermined conductive material, such as via or plug.

The bit line BL connected to the second bit line contact 33 is formed on the interlayer insulating layer 29.

The second bit line contact 33 may be in contact with the above-described sub bit line Sub_BL of the first semiconductor substrate 10 through another bit line contact, for example, the third bit line contact 35. In other words, the third bit line contact 35 is formed in the second semiconductor substrate 20 between the second bit line junction region 27a and the sub bit line Sub_BL, and the sub bit line Sub_BL and the second bit line are formed on the second semiconductor substrate 20. The bit line contacts 33 may be connected to each other through the third bit line contact 35. The third bit line contact 35 may be a via formed in the second semiconductor substrate 20.

The second semiconductor substrate including the plurality of third gate structures 23, the plurality of second junction regions 27, the interlayer insulating layer 29, the second bit line contacts 33, and the bit lines BL ( 20) can be completed.

Although not shown in FIGS. 3 and 4, the multilayer memory device 100 or 101 of the present invention may further include a controller (reference numeral 60 of FIG. 5). The controller may be connected to each of a plurality of page buffers formed on the second semiconductor substrate 20, and output a control signal for controlling the operation of each page buffer.

Hereinafter, an operation method of a multilayer memory device of the present invention will be described in detail with reference to FIGS. 5 to 7.

5 is a schematic block diagram of the memory device of the multilayer structure illustrated in FIGS. 1 to 4, FIG. 6 is an operational flowchart of the memory device of FIG. 5, and FIG. 7 is a multilayer according to another embodiment of FIG. 6. Operation flowchart of the structure memory device.

Referring to FIG. 5, a memory device 100 having a multilayer structure according to the present invention may include a first semiconductor substrate 10, a second semiconductor substrate 20, a controller 60, and at least one bit line 71, 72, or 73. ) May be included.

As described above with reference to FIGS. 1 to 4, a plurality of memory cell arrays 10_1, 10_2,... 10_N may be formed on the first semiconductor substrate 10, and on the second semiconductor substrate 20. A plurality of page buffers 20_1, 20_2,... 20_N may be formed, respectively. Each of the plurality of memory cell arrays 10_1, 10_2,... 10_N and each of the plurality of page buffers 20_1, 20_2,... 20_N may be connected to correspond to each other.

The controller 60 may output a control signal CS for controlling the operations of each of the plurality of page buffers 20_1, 20_2,... 20_N formed on the second semiconductor substrate 20. For example, the controller 60 may be connected to each of the plurality of page buffers 20_1, 20_2,... 20_N of the second semiconductor substrate 20 through at least one control line 65, and the plurality of page buffers. (20_1, 20_2, ... 20_N) The control signal CS for independently controlling each operation may be output to each page buffer 20_1, 20_2, ... 20_N through at least one control line 65. have.

Accordingly, each of the plurality of page buffers 20_1, 20_2,... 20_N receives a data signal from at least one bit line 71, 72, or 73 according to the control signal CS output from the controller 60. A write operation is performed to output and write to each of the corresponding memory cell arrays 10_1, 10_2,... 10_N, or store data from each of the corresponding memory cell arrays 10_1, 10_2,... A read operation of reading the data signal may be performed.

At least one bit line 71, 72, or 73 may be connected to each of the plurality of page buffers 20_1, 20_2,..., 20_N. For example, the memory device 100 of the multilayer structure of the present exemplary embodiment may include a first bit line 71, a second bit line 72, and a third bit line 73. However, the present invention is not limited thereto.

The first bit line 71, the second bit line 72, and the third bit line 73 may be connected to each of the plurality of page buffers 20_1, 20_2,... 20_N, and provided from the controller 60. According to the control signal CS, a data signal, for example, an input data signal is provided to each of the plurality of page buffers 20_1, 20_2,... 20_N, or a data signal from each of the plurality of page buffers 20_1, 20_2, ... 20_N. For example, an output data signal may be provided.

Hereinafter, a method of operating the multilayered memory device 100 described above with reference to FIGS. 5 and 6 will be described.

The controller 60 may grasp the state of each of the plurality of page buffers 20_1, 20_2,..., 20_N (S10). For example, the controller 60 outputs a signal capable of grasping the current state of each of the plurality of page buffers 20_1, 20_2,... 20_N, and feeds back a plurality of page buffers 20_1, 20_2, ... 20_N. From each response, the current state of each of the plurality of page buffers 20_1, 20_2,... 20_N can be determined. In this embodiment, as an example, each of the plurality of page buffers 20_1, 20_2,... 20_N is an initial state, that is, a state in which no operation is performed.

The controller 60 performs operations of each of the plurality of page buffers 20_1, 20_2,... 20_N through control line 65 connected to each of the plurality of page buffers 20_1, 20_2,. The write operation (or program operation) or the read operation may be controlled.

For example, the controller 60 may control the operation of the first page buffer 20_1 by outputting the first control signal CS1 (S20). In addition, the controller 60 may control the operation of the second page buffer 20_2 by outputting the second control signal CS2 (S30).

The first control signal CS1 and the second control signal CS2 may be output from the controller 60 to the first page buffer 20_1 and the second page buffer 20_2 at the same time, or the controller 60 The first control signal CS1 is first outputted to the first page buffer 20_1, and the second control signal CS2 is first generated while the first page buffer 20_1 operates according to the first control signal CS1. It may be output to the two page buffer 20_2.

The first page buffer 20_1 may exchange data signals with the corresponding first memory cell array 10_1 according to the first control signal CS1 output from the controller 60.

For example, the first page buffer 20_1 receives a data signal from the first bit line 71 according to the first control signal CS1 output from the controller 60 and writes to the first memory cell array 10_1. It may be performed (S23). In addition, the first page buffer 20_1 may perform a read operation of the data signal stored in the first memory cell array 10_1 according to the first control signal CS1 output from the controller 60 (S21). The read data signal may be output to the outside through the first bit line 71.

The second page buffer 20_2 may exchange data signals with the corresponding second memory cell array 10_2 according to the second control signal CS2 output from the controller 60.

For example, the second page buffer 20_2 receives a data signal from the second bit line 72 according to the second control signal CS2 output from the controller 60 and writes the data signal to the second memory cell array 10_2. An operation may be performed (S33). In addition, the second page buffer 20_2 may perform a read operation of the data signal stored in the second memory cell array 10_2 according to the second control signal CS2 output from the controller 60 (S31). The read data signal may be output to the outside through the second bit line 72.

As described above, the second page buffer 20_2 performs a read / write operation simultaneously with the first page buffer 20_1 by the second control signal CS2 output from the controller 60 or the first page buffer 20_2. While the page buffer 20_1 performs the read / write operation, the read / write operation may be performed according to the second control signal CS2.

That is, in the present exemplary embodiment, the first page buffer 20_1 and the second page buffer 20_2 may be configured according to a control signal output from the controller 60, for example, the first control signal CS1 or the second control signal CS2. By independently controlling the operation, the second memory cell array 10_2 may also perform the read / write operation while the first memory cell array 10_1 performs the read / write operation, thereby enabling the memory of the multilayer structure. The operating performance of the device 100 can be improved.

An operation of the multilayer memory device 100 according to another exemplary embodiment of the present invention will be described with reference to FIGS. 5 and 7.

The controller 60 may grasp the state of each of the plurality of page buffers 20_1, 20_2,..., 20_N (S10). For example, the controller 60 outputs a signal capable of grasping the current state of each of the plurality of page buffers 20_1, 20_2,... 20_N, and feeds back a plurality of page buffers 20_1, 20_2,... 20_N) From each response, the current state of each of the plurality of page buffers 20_1, 20_2,... In this embodiment, as an example, each of the plurality of page buffers 20_1, 20_2,... 20_N is an initial state, that is, a state in which no operation is performed.

The controller 60 performs operations of each of the plurality of page buffers 20_1, 20_2,... 20_N through control line 65 connected to each of the plurality of page buffers 20_1, 20_2,. The write operation (or program operation) or the read operation may be controlled.

For example, the controller 60 may control the operation of the first page buffer 20_1 by outputting the first control signal CS1 (S20). In addition, the controller 60 may control the operation of the second page buffer 20_2 by outputting the second control signal CS2 (S30).

The first control signal CS1 and the second control signal CS2 may be output from the controller 60 to the first page buffer 20_1 and the second page buffer 20_2 at the same time, or the controller 60 The first control signal CS1 is first outputted to the first page buffer 20_1, and the second control signal CS2 is first generated while the first page buffer 20_1 operates according to the first control signal CS1. It may be output to the two page buffer 20_2.

The first page buffer 20_1 may exchange data signals with the corresponding first memory cell array 10_1 according to the first control signal CS1 output from the controller 60.

For example, the first page buffer 20_1 receives a data signal from the first bit line 71 according to the first control signal CS1 output from the controller 60 and writes to the first memory cell array 10_1. It may be performed (S23).

In addition, the first page buffer 20_1 may perform a read operation of the data signal stored in the first memory cell array 10_1 according to the first control signal CS1 output from the controller 60 (S21). The read data signal may be output to the outside through the first bit line 71.

The second page buffer 20_2 is controlled by the second control signal CS2 output from the controller 60 in operation S30, and receives the data signal from the second bit line 72 to temporarily store the data signal in operation S31. ).

As described above, the second page buffer 20_2 may be configured to simultaneously read / write the first page buffer 20_1 and the second bit line according to the second control signal CS2 output from the controller 60. The data signal may be temporarily received from the second bit line 72 while the data signal is received from the second bit line 72 while the first page buffer 20_1 performs the read / write operation.

When the read operation or the write operation of the first page buffer 20_1 whose operation is controlled by the first control signal CS1 is completed, the controller 60 may output the third control signal CS2. The third control signal CS2 may control operations of the first page buffer 20_1 and the second page buffer 20_2 (S40).

For example, the second page buffer 20_2 is temporarily stored through one bit line among the first bit line 71 to the third bit line 73 according to the third control signal CS2 output from the controller 60. The data signal may be transmitted to the first page buffer 20_1 (S41).

The first page buffer 20_1 receiving the data signal transmitted from the second page buffer 20_2 receives the data signal transmitted according to the third control signal CS2 output from the controller 60. In operation S43, the write operation of writing to the terminal 10_1 may be performed.

That is, in the present embodiment, when the first page buffer 20_1 is operated by the first control signal CS1 output from the controller 60, a data signal corresponding to the first page buffer 20_1 is externally received. Even if it is input, it is temporarily stored in the second page buffer 20_2 and later transferred to the first page buffer 20_1 to be recorded, thereby improving the operation performance of the memory device 100 having a multilayer structure.

8 is a block diagram illustrating an electronic system including a memory device having a multilayer structure according to an embodiment of the present invention, and FIGS. 9A to 9J include a memory device having a multilayer structure according to an embodiment of the present invention. Various embodiments of electronic systems are shown.

8 to 9J, the multi-layered memory device 100 or 101 according to the present invention may be implemented as, for example, a memory card including a secure digital (SD) card or a multi-media card (MMC). . In addition, the memory card may include a smart card.

The memory card 100 or 101 using a multi-layered memory device is a video camera (FIG. 9A), a TV or IPTV (FIG. 9B), an MP3 player (FIG. 9C), an electronic game machine or navigation (FIG. 9D), an electronic musical instrument. (FIG. 9E), a portable communication terminal such as a mobile telephone (FIG. 9F), a personal computer (FIG. 9G), a personal digital assistant (FIG. 9H), a voice recorder (FIG. 9I), or a PC card ( Or a memory card reader (FIG. 9J).

Thus, a video camera (FIG. 9A), TV or IPTV (FIG. 9B), MP3 player (FIG. 9C), electronic game machine or navigation (FIG. 9D), electronic musical instrument (FIG. 9E), portable communication terminal (FIG. 9F), PC ( 9G), a PDA (FIG. 9H), a voice recorder (FIG. 9I), a PC card (or memory card reader; FIG. 9J), and the like, each of which may be connected to the card interface 420 and the card interface 420 ( Or a connection unit 410, the memory card 100 or 101 is electrically connected to a slot (or connection unit 410) and is connected to the video camera (FIG. 9A), TV or IPTV (FIG. 9B) via the card interface 420. ), MP3 player (FIG. 9C), electronic game machine or navigation (FIG. 9D), electronic musical instrument (FIG. 9E), portable communication terminal (FIG. 9F), PC (FIG. 9G), PDA (FIG. 9H), voice recorder (FIG. 9I). Or a CPU (or microprocessor; not shown) included in each electronic circuit 430 such as a PC card (or a memory card reader; FIG. 9J); You may receive a defined data or commands.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a schematic diagram of a memory device having a multilayer structure according to an embodiment of the present invention.

FIG. 2A is a circuit diagram of one memory cell array of the plurality of memory cell arrays shown in FIG. 1.

FIG. 2B is a schematic block diagram of one page buffer of the plurality of page buffers shown in FIG. 1.

3 is a cross-sectional view of a semiconductor device having a multilayer structure according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of another example of the memory device having the multilayer structure illustrated in FIG. 3.

FIG. 5 is a schematic block diagram of a memory device having a multilayer structure illustrated in FIGS. 1 to 4.

6 is a flowchart illustrating an operation of the multilayer memory device of FIG. 5.

7 is a flowchart illustrating an operation of a multilayer memory device according to another exemplary embodiment of FIG. 6.

8 is a block diagram illustrating an example of an electronic system including a memory device having a multilayer structure according to an embodiment of the present invention.

9A-9J illustrate various embodiments of electronic systems including a multi-layered memory device in accordance with an embodiment of the present invention.

Claims (10)

A first semiconductor substrate on which a memory cell array including a plurality of memory cells is formed; A second semiconductor substrate stacked on the first semiconductor substrate and formed such that a bit line and a page buffer connected to the bit line correspond to the memory cell array; And And a bit line contact formed between the first semiconductor substrate and the second semiconductor substrate and connecting the page buffer and the memory cell array. The method of claim 1, wherein the bit line contact, A first bit line contact formed in the first semiconductor substrate between the memory cell array and the second semiconductor substrate; A second bit line contact formed in the second semiconductor substrate between the bit line and the page buffer; And And a third bit line contact formed in the second semiconductor substrate between the first bit line contact and the second bit line contact. According to claim 1, The bit line contact may be a via or a plug-in multilayer memory device. A first semiconductor substrate on which a pair of memory cell arrays each including a plurality of memory cells is formed; A second semiconductor substrate stacked on the first semiconductor substrate and having a bit line and a page buffer connected to the bit line corresponding to the pair of memory cell arrays; A sub bit line formed between the first semiconductor substrate and the second semiconductor substrate; And And a bit line contact formed between the first semiconductor substrate and the second semiconductor substrate and connecting the page buffer and the pair of memory cell arrays, respectively. The method of claim 4, wherein the bit line contact, A first bit line contact formed in the first semiconductor substrate between the pair of memory cell arrays and the sub bit line; A second bit line contact formed in the second semiconductor substrate between the bit line and the page buffer; And And a third bit line contact formed in the second semiconductor substrate between the first bit line contact and the sub bit line. The memory device of claim 1, wherein the multilayer memory device includes: And a controller connected to the page buffer of the second semiconductor substrate and outputting a control signal for controlling the operation of the page buffer. A method of operating a memory device having a multilayer structure according to any one of claims 1 to 6, Operating the first page buffer in response to the first control signal output from the controller, and exchanging first data with the first memory cell array; And Operating a second page buffer in response to a second control signal output from the controller, and exchanging second data with a second memory cell array; The second page buffer may operate simultaneously with the first page buffer to exchange the second data with the second memory cell array, or the first page buffer and the first memory cell array may exchange the first data. A method of operating a memory device of a multilayer structure operating during a receiving operation to exchange the second data with the second memory cell array. A method of operating a memory device having a multilayer structure according to any one of claims 1 to 6, Operating the first page buffer in response to the first control signal output from the controller, and exchanging first data with the first memory cell array; While the first page buffer and the first memory cell array exchange the first data, a second page buffer operates in response to a second control signal output from the controller, and a second page buffer. Receiving and storing second data through a bit line; And When the first page buffer and the first memory cell array complete the operation of exchanging the first data, the second page buffer is connected to the second page buffer through the bit line in response to a third control signal output from the controller. And transmitting data to the first page buffer. 2. Card interface; A slot connected to the card interface; And A memory card connectable to said slot, The memory card, A first semiconductor substrate on which a memory cell array including a plurality of memory cells is formed; A second semiconductor substrate stacked on the first semiconductor substrate and formed such that a bit line and a page buffer connected to the bit line correspond to the memory cell array; And And a memory device having a multilayer structure formed between the first semiconductor substrate and the second semiconductor substrate and including a bit line contact connecting the page buffer and the memory cell array. Card interface; A slot connected to the card interface; And A memory card connectable to said slot, The memory card, A first semiconductor substrate having a pair of memory cell arrays provided with a plurality of memory cells; A second semiconductor substrate stacked on the first semiconductor substrate and having a bit line and a page buffer connected to the bit line corresponding to the pair of memory cell arrays; A sub bit line formed between the first semiconductor substrate and the second semiconductor substrate; And And a bit line contact formed between the first semiconductor substrate and the second semiconductor substrate and connecting the page buffer and the pair of memory cell arrays, respectively.

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