CN110688814B - Eye pattern measuring device and eye pattern measuring method - Google Patents
Eye pattern measuring device and eye pattern measuring method Download PDFInfo
- Publication number
- CN110688814B CN110688814B CN201810734744.4A CN201810734744A CN110688814B CN 110688814 B CN110688814 B CN 110688814B CN 201810734744 A CN201810734744 A CN 201810734744A CN 110688814 B CN110688814 B CN 110688814B
- Authority
- CN
- China
- Prior art keywords
- signals
- signal
- eye
- counting
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Dc Digital Transmission (AREA)
Abstract
An eye diagram measuring device and an eye diagram measuring method. The eye diagram measuring device comprises a first mapping circuit system, a counting circuit system, a second mapping circuit system and a memory circuit system. The first mapping circuitry maps one of a plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits. The counting circuitry performs a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits to generate a plurality of counting signals. The second mapping circuitry maps the plurality of count signals to a plurality of eye measurement signals corresponding to a current phase, respectively. The memory circuitry stores the eye measurement signals to provide the eye measurement signals to an external system to generate an eye measurement result of the electronic device. The eye diagram measuring device and the eye diagram measuring method can be used for measuring signals with multiple levels and can also provide a function of counting signal values.
Description
Technical Field
The present invention relates to an eye diagram measuring device, and more particularly, to an eye diagram measuring device and an eye diagram measuring method capable of measuring a signal having multiple levels.
Background
Eye diagram (eye diagram) is a common way to measure signal quality. The larger the eye height (eye height) and/or eye width (eye width) in the eye diagram, the better the measured signal quality.
As data transmission speeds are higher and higher, multi-level signal encoding using Pulse-amplitude modulation (PAM) signals and the like is increasingly used. However, the conventional eye diagram measuring circuit is only suitable for measuring non-return-to-zero (NRZ) encoded signals, and cannot be used for the above applications.
Disclosure of Invention
In order to solve the above-mentioned problems, some aspects of the present invention provide an eye diagram measurement device, which includes a first mapping circuit system, a counting circuit system, a second mapping circuit system and a memory circuit system. The first mapping circuitry is configured to map one of a plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits. The counting circuitry is configured to perform a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits to generate a plurality of counting signals. The second mapping circuitry is configured to map the plurality of count signals to a plurality of eye measurement signals corresponding to a current phase, respectively. The memory circuitry is configured to store the eye measurement signals to provide the eye measurement signals to an external system to generate an eye measurement result of the electronic device.
In some embodiments, the first mapping circuitry includes a plurality of bit conversion circuits and a multiplexer circuit. The plurality of bit conversion circuits are used for generating a plurality of second data signals, wherein the bit number of each of the plurality of second data signals is the same as the preset bit number, and each of the plurality of bit conversion circuits is used for extracting a corresponding one of the plurality of second data signals from a corresponding one of the plurality of internal signals. The multiplexer circuit is used for receiving the plurality of second data signals and outputting one of the plurality of second data signals as the first data signal according to a selection signal.
In some embodiments, the counting circuitry includes a plurality of processing circuits and a plurality of counters. The plurality of processing circuits are used for comparing the first data signal with the plurality of signal values respectively to output a plurality of trigger signals, wherein a first trigger signal in the plurality of trigger signals indicates that the first data signal is identical to a first signal value in the plurality of signal values. The counters are used for determining whether to execute the counting operation according to the trigger signals respectively so as to output the counting signals. When a first counter of the plurality of counters receives the first trigger signal, the first counter performs the counting operation to update a corresponding one of the plurality of counting signals.
In some embodiments, a plurality of second trigger signals of the plurality of trigger signals indicate that the first data signal is different from a remaining signal value of the plurality of signal values, and the remaining counter of the plurality of counters does not perform the counting operation when the remaining counter receives the plurality of second trigger signals.
In some embodiments, the memory circuitry is further configured to store the plurality of count signals to provide the plurality of count signals to the external system to generate a statistical result associated with the current phase.
In some embodiments, the second mapping circuitry comprises a plurality of logic circuits. The logic circuits are used for performing a plurality of logical OR operations according to the counting signals respectively so as to generate the eye pattern measuring signals.
In some embodiments, the eye diagram measurement apparatus further comprises phase control circuitry. The phase control circuitry is configured to provide one of a preset value and a eye-diagram measurement value associated with the electronic device to a clock data recovery circuit in the electronic device according to a control signal to switch a phase of a clock signal of the electronic device from the current phase to one phase at a time.
In some embodiments, the first data signal is a pulse amplitude modulated signal.
Some aspects of the present disclosure provide an eye diagram measurement method, which includes the following operations: mapping one of a plurality of internal signals of an electronic device to a first data signal with a preset bit number; performing a counting operation according to the first data signal and a plurality of signal values associated with the preset bit number to generate a plurality of counting signals; mapping the count signals to eye pattern measurement signals corresponding to a current phase; and storing the eye pattern measurement signals to provide the eye pattern measurement signals to an external system to generate an eye pattern measurement result of the electronic device.
In some embodiments, mapping one of the plurality of internal signals to the first data signal comprises: extracting a plurality of second data signals from the plurality of internal signals respectively; and outputting one of the plurality of second data signals as the first data signal according to a selection signal.
In some embodiments, generating the plurality of count signals includes: comparing the first data signal with the plurality of signal values respectively to output a plurality of trigger signals, wherein a first trigger signal in the plurality of trigger signals indicates that the first data signal is identical to a first signal value in the plurality of signal values; and determining whether to execute the counting operation or not by a plurality of counters according to the plurality of trigger signals respectively so as to output the plurality of counting signals, wherein when a first counter in the plurality of counters receives the first trigger signal, the first counter executes the counting operation so as to update a corresponding one of the plurality of counting signals.
In some embodiments, a plurality of second trigger signals of the plurality of trigger signals indicate that the first data signal is different from a remaining signal value of the plurality of signal values, and the remaining counter of the plurality of counters does not perform the counting operation when the remaining counter receives the plurality of second trigger signals.
In some embodiments, the eye diagram measurement method further comprises: the plurality of count signals are stored to provide the plurality of count signals to the external system to generate a statistical result associated with the current phase.
In some embodiments, mapping the plurality of count signals to the plurality of eye measurement signals, respectively, comprises: and performing a plurality of logical OR operations according to the plurality of counting signals respectively to generate a plurality of eye pattern measurement signals.
In some embodiments, the eye diagram measurement method further comprises: providing one of a preset value and a eye diagram measurement value associated with the electronic device to a clock data recovery circuit in the electronic device according to a control signal so as to switch the phase of a clock signal of the electronic device from the current phase to one phase at a time.
In summary, the eye diagram measuring device and the eye diagram measuring method provided by the present invention can be used for measuring signals with multiple levels and can provide the function of counting signal values.
Drawings
The foregoing and other objects, features, advantages and embodiments of the present disclosure will be apparent from the following description of the drawings in which:
FIG. 1 is a schematic diagram of an eye diagram measurement apparatus according to some embodiments of the present disclosure;
FIG. 2 is a schematic diagram of the mapping circuitry of FIG. 1 according to some embodiments of the present disclosure;
FIG. 3 is a schematic diagram of the counting circuitry of FIG. 1 according to some embodiments of the present disclosure;
FIG. 4 is a schematic diagram of the mapping circuitry of FIG. 1 according to some embodiments of the present disclosure;
FIG. 5 is a schematic diagram of the phase control circuitry of FIG. 1 according to some embodiments of the present disclosure; and
fig. 6 is a flow chart of an eye diagram measurement method according to some embodiments of the present disclosure.
Detailed Description
All terms used herein have their ordinary meaning. The foregoing definitions of words and phrases are provided throughout this specification and in all instances, there is no intention to limit the scope and meaning of the disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.
The terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or blocks. These elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Accordingly, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the spirit of the present disclosure. As used herein, "and/or" includes any and all combinations of one or more of the associated items.
As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or that two or more elements may operate or function with each other.
The term "circuitry" is used herein to refer broadly to a single system comprising one or more circuits (circuits). The term "circuit" generally refers to an article of manufacture that is connected in a manner by one or more transistors and/or one or more active and passive elements to process signals.
Referring to fig. 1, fig. 1 is a schematic diagram of an eye diagram (eye diagram) measurement apparatus 100 according to some embodiments of the present disclosure. In some embodiments, the eye diagram measurement device 100 can be used to measure a plurality of signals in an electronic device (such as the receiver 100A, but not limited thereto). The receiver 100A may include, but is not limited to, an adc A1, a feedforward equalizer A2, a decision maker A3, a clock data recovery circuit A4, a decision feedback circuit A5, and so on.
As shown in fig. 1, the eye diagram measuring apparatus 100 can be used to measure a plurality of internal signals S1-S3 of the receiver 100A, such as an output of an analog-to-digital converter A1, an output of a feed-forward equalizer A2, and an input of a decision maker A3 in the receiver 100A. The above-mentioned internal signals S1 to S3 are only examples, and other signals of the receiver 100A can be measured by the eye measurement device 100.
In some embodiments, eye diagram measurement apparatus 100 includes mapping circuitry 110, counting circuitry 120, mapping circuitry 130, and memory circuitry 140.
The counting circuitry 120 is coupled to the mapping circuitry 110 to receive the data signal D1. In some embodiments, the counting circuitry 120 is configured to perform a counting operation according to the data signal D1 and the plurality of signal values Q1-QM to generate a plurality of counting signals C1-CM. In some embodiments, the plurality of signal values Q1-QM are associated with a predetermined number of bits of the data signal D1. For example, if the predetermined number of bits is 7 bits, the plurality of signal values Q1-QM may be sequentially 0, 1, …, 27-1. When the data signal D1 is identical to one of the plurality of signal values Q1-QM, the counting circuitry 120 performs the counting operation to update a corresponding one of the plurality of counting signals C1-CM. Thus, by observing the plurality of count signals C1 to CM, the corresponding signal value of the data signal D1 measured at each corresponding phase can be confirmed. The operation will be described in the following paragraphs with reference to fig. 3.
By setting the plurality of signal values Q1-QM, the signal values of the data signal D1 at a plurality of different levels can be measured. In other words, the data signal D1 may be a Pulse-amplitude modulation (PAM) signal with multiple levels, but is not limited thereto.
The mapping circuitry 130 is coupled to the counting circuitry 120 for receiving a plurality of counting signals C1-CM. In some embodiments, the mapping circuitry 130 maps the count signals C1-CM to the eye measurement signals E1-EM, respectively, wherein the count signals C1-CM correspond to the eye measurement signals E1-EM, respectively, and the eye measurement signals E1-EM correspond to the current phase of the clock signal CLK outputted by the clock data recovery circuit A4 in the receiver 100A. For example, when the clock signal CLK is in the current phase, the count signal C1 is updated and the remaining count signals C2-CM are not updated, the eye measurement signal E1 has a logic value of 1, and the remaining eye measurement signals E2-EM have a logic value of 0. In other words, in this example, the eye measurement signals E1-EM can confirm that the signal value of the data signal D1 at the current phase is the same as one of the signal values Q1-QM corresponding to the count signal C1.
The memory circuitry 140 is coupled to the counting circuitry 120 to receive the counting signals C1-CM, and coupled to the mapping circuitry 130 to receive the eye measurement signals E1-EM. In some embodiments, the memory circuitry 140 is configured to store a plurality of count signals C1-CM and/or a plurality of eye measurement signals E1-EM. In some embodiments, the memory circuit 140 is coupled to an external system 100B to transmit a plurality of count signals C1-CM and/or a plurality of eye measurement signals E1-EM to the external system 100B. In some embodiments, memory circuitry 140 may be implemented by registers and/or memory circuits.
The external system 100B can generate the eye measurement result R1 by plotting the eye measurement signals E1-EM and generate a statistics result R2 by analyzing the counting signals C1-CM. In some embodiments, the statistic R2 may be a histogram (histogram) for showing the number of times the data signal D1 is identical to the respective signal values Q1-QM in the current phase.
In some embodiments, the external system 100B may include a signal analysis software or design tool implementation executed by a processor. In some embodiments, the external system 100B may be an oscilloscope. The above embodiments regarding the external system 100 are only examples, and the present invention is not limited thereto.
For ease of understanding, fig. 1 shows only one set of mapping circuitry 110, but the disclosure is not limited thereto. In some applications, the eye measurement device 100 may be provided with more sets of mapping circuitry 110, wherein the plurality of mapping circuitry 110 operates in parallel to receive more different internal signals from the receiver 100A. In these embodiments, as shown in FIG. 1, the eye measurement apparatus 100 further comprises buffer circuitry 115 coupled between the mapping circuitry 110 and the counting circuitry 120. Under this condition, the buffer circuit 115 may buffer the data signals D1 outputted from the mapping circuit 110 to synchronize the data signals D1, and sequentially output the data signals D1 as a plurality of data signals D1' to the counting circuit 120. In some embodiments, the buffer circuitry 115 may be implemented as a first-in-first-out (FIFO) circuit, but this is not limiting. In some other embodiments, the mapping circuitry 110 may transmit the data signals D1 to the counting circuitry 120 without providing the buffer circuitry 115.
In some embodiments, as shown in FIG. 1, the eye diagram measurement apparatus 100 further includes phase control circuitry 150. Phase control circuitry 150 is coupled to memory circuitry 140 and receiver 100A. The phase control circuitry 150 is coupled to the feed forward equalizer A2, the decision maker A3 and/or the clock data recovery circuit A4. In some embodiments, after the memory circuit 140 stores the eye measurement signals E1-EM corresponding to the current phase, the phase control circuit 150 is configured to control the circuits (e.g., the feedforward equalizer A2, the decision device A3 and/or the clock data recovery circuit A4) in the receiver 100A according to a control signal SC to switch the phase of the clock signal CLK to the next phase. Thus, the eye measurement device 100 can continuously measure the eye measurement signals E1-EM corresponding to the next phase.
The following paragraphs will illustrate the embodiments of the above-mentioned circuit systems, but the present invention is not limited to the following examples.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating the mapping circuitry 110 of fig. 1 according to some embodiments of the present disclosure. For ease of understanding, like elements in fig. 1 and 2 will be designated with the same reference numerals.
In some embodiments, the mapping circuitry 110 includes a plurality of bit conversion circuits 210-1-210-3 and a multiplexer circuit 220. The plurality of bit conversion circuits 210-1 to 210-3 are coupled to the output of the analog-to-digital converter A1, the output of the feedforward equalizer A2 and the input of the decision maker A3 in FIG. 1, respectively, to receive the plurality of internal signals S1 to S3, respectively.
In some embodiments, the plurality of bit conversion circuits 210-1 to 210-3 generate a plurality of data signals D2 according to the plurality of internal signals S1 to S3, wherein each data signal D2 has the same number of bits as the predetermined number of bits. In some embodiments, each of the bit conversion circuits 210-1 to 210-3 extracts a corresponding data signal D2 according to a corresponding one of the internal signals S1 to S3. Taking the bit conversion circuit 210-1 as an example, the bit conversion circuit 210-1 can extract a portion of bits (e.g., a portion of the least significant bits (Least Significant Bit, LSB) of the internal signal S1) in the internal signal S1 to generate the corresponding data signal D2. Similarly, the bit-conversion circuit 210-2 or 210-3 may also extract a portion of bits in the internal signal S2 or S3 to generate the corresponding data signal D2.
The above-described arrangement of the bit conversion circuits 210-1 to 210-3 is merely exemplary, and other various arrangements for generating the data signal D2 with a fixed bit number are also contemplated.
The multiplexer circuit 220 is coupled to the plurality of bit conversion circuits 210-1 to 210-3 to receive the plurality of data signals D2. The multiplexer circuit 220 is used for outputting one of the plurality of data signals D2 as a data signal D1 according to the selection signal SEL. In some embodiments, the multiplexer circuit 220 may be implemented by multiple sets of switches, but the disclosure is not limited thereto.
In still other embodiments, the mapping circuitry 110 may further include a switching circuit (not shown) for determining whether to output the data signal D1 to the counting circuitry 120 according to an enable signal (not shown). In other words, by the above arrangement, the eye measurement device 100 can determine whether to perform the eye measurement operation according to the enable signal.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating the counting circuitry 120 of fig. 1 according to some embodiments of the present disclosure. For ease of understanding, like elements in fig. 1 and 3 will be designated with the same reference numerals.
In some embodiments, the counting circuitry 120 includes a plurality of processing circuits 310-1-310-M and a plurality of counters 320-1-320-M. The plurality of processing circuits 310-1-310-M are coupled to the mapping circuitry 110 to receive the data signal D1. The number of the plurality of processing circuits 310-1 to 310-M is related to the predetermined number of bits. For example, when the predetermined number of bits is 7, the number of the plurality of processing circuits 310-1 to 310-M is 27.
The plurality of processing circuits 310-1 to 310-M respectively compare the data signal D1 with the plurality of signal values Q1 to QM to generate a plurality of trigger signals TR1 to TRM. When the confirmation data signal D1 is identical to one of the plurality of signal values Q1 to QM, a corresponding one of the plurality of processing circuits 310-1 to 310-M outputs a trigger signal having a first logic value (e.g., logic value 1). Conversely, when the confirmation data signal D1 is different from one of the plurality of signal values Q1-QM, a corresponding one of the plurality of processing circuits 310-1-310-M outputs a trigger signal having a second logic value (e.g., logic value 0).
For example, assume that the predetermined number of bits is 7, and the processing circuit 310-1 is configured to compare the data signal D1 with the signal value Q1 (i.e., 27-1=127). When the data signal D1 is the same as the signal value Q1, the processing circuit 310-1 will output the trigger signal TR1 having a logic value of 1. In addition, under this condition, the data signal D1 is different from the remaining signal values Q2-QM, so the remaining processing circuits 310-2-310-M will output a plurality of trigger signals TR 2-TRM having a logic value of 0. By the above arrangement, it is possible to determine what signal value of the data signal D1 is measured in the current phase based on the trigger signals TR1 to TRM.
In some embodiments, the plurality of processing circuits 310-1-310-M may be implemented by comparators. In some embodiments, the plurality of processing circuits 310-1-310-M may be implemented by logic circuits similar to anti-exclusive OR gates or having the same function. The above embodiments with respect to the processing circuits 310-1-310-M are examples, and other embodiments are also within the scope of the present disclosure.
The counters 320-1-320-M are coupled to the processing circuits 310-1-310-M, respectively, to receive the trigger signals TR 1-TRM. The counters 320-1-320-M perform a counting operation according to the trigger signals TR 1-TRM, respectively, to generate a plurality of counter signals C1-CM when one of the trigger signals TR 1-TRM has a first logic value, and the counter 320-1-320-M performs a counting operation to update a corresponding one of the counter signals C1-CM.
For example, at the beginning, the count signals C1-CM are all 0. When the trigger signal TR1 has a first logic value (i.e., logic 1) and the other trigger signals TR2 to TRM have a second logic value (i.e., logic 0), the trigger signal TR1 has a logic value 1 and the remaining trigger signals TR2 to TRM have a logic value 0. Under this condition, the counter 320-1 performs a counting operation to increase the count signal C1 from 0 to 1 in response to the trigger signal TR1 having a logic value of 1. Likewise, the remaining counters 320-2 to 320-M do not perform a counting operation in response to the trigger signals TR2 to TRM having a logic value of 0. Thus, the remaining count signals C2 to CM are maintained at 0 without being updated.
As previously described, the external system 100B can generate a statistics R2 by analyzing the plurality of count signals C1-CM. For example, by analyzing the number of times the count signal C1 is updated, the number of times the data signal D1 is identical to the signal value Q1 (i.e., 127) can be counted. By analogy, by recording and analyzing all the count signals C1-CM, the number of times the data signal D1 is identical to each of the signal values Q1-QM can be counted to generate the count result R2.
For ease of understanding, FIG. 3 shows only one set of processing circuits 310-1-310-M, but the disclosure is not limited thereto. In some embodiments, the counting circuitry 120 may be configured with more sets of processing circuits 310-1-310-M, wherein the sets of processing circuits 310-1-310-M operate in parallel to increase processing efficiency. In these embodiments, the counting circuitry 120 further includes a plurality of adders and other logic circuits such as registers to sum up the trigger circuits corresponding to each of the plurality of sets of processing circuits 310-1-310-M.
The above arrangements of the counting circuitry 120 are merely examples, and various arrangements capable of achieving the same operation are also contemplated herein.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating the mapping circuitry 130 of fig. 1 according to some embodiments of the present disclosure. For ease of understanding, similar elements in fig. 1 and 4 will be designated with the same reference numerals.
In some embodiments, mapping circuitry 130 includes a plurality of logic circuits 410-1-410-M. The plurality of logic circuits 410-1-410-M are respectively coupled to the plurality of counters 320-1-320-M of FIG. 3 to receive a plurality of count signals C1-CM. Each of the logic circuits 410-1-410-M performs a logical OR operation according to a corresponding one of the count signals C1-CM to generate a corresponding one of the eye measurement signals E1-EM.
For example, the logic circuit 410-1 may perform a logical OR operation according to all the count signals C1 received during a predetermined period to generate the eye measurement signal E1. For example, at the current phase of the clock signal CLK, the signal value of the data signal D1 is 127 (i.e., the signal value Q1), the trigger signal TR1 is continuously 1 while the count signal C1 is continuously updated, such that the count signal C1 is at least 1. Thus, during the period when the clock signal CLK is in the current phase, the logic circuit 410-1 generates the eye measurement signal E1 having a logic value of 1 according to the count signal C1. Equivalently, the eye measurement signal E1 with logic value 1 can be used to represent that the signal value of the data signal D1 is identical to the signal value 127 at the current phase of the clock signal CLK.
Continuing the above example, since the signal value of the data signal D1 is 127 and is different from the other signal values Q2-QM, the trigger signals TR 2-TRM will be continuously 0 without updating the count signals C2-CM, so that the count signals C2-CM are maintained at 0. Thus, the logic circuits 410-2-410-M generate the eye measurement signals E2-EM having a logic value of 0 according to the count signals C2-CM. Equivalently, the eye measurement signals E2-EM having a logic value 0 can be used to represent that the signal value of the data signal D1 is different from the other signal values Q2-QM at the current phase of the clock signal CLK.
The logic circuits 410-1 to 410-M performing the logical OR operation are described above as examples, but the present invention is not limited thereto. Various logic circuits with updated detectable count signals C1-CM may be used to implement logic circuits 410-1-410-M.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating the phase control circuitry 150 of fig. 1 according to some embodiments of the present disclosure. For ease of understanding, similar elements in fig. 1 and 5 will be designated with the same reference numerals.
The phase control circuitry 150 includes a multiplexer circuit 510. The multiplexer circuit 510 outputs one of a preset value PD1 and a measurement reference value REF1 associated with the receiver 100A to the clock data recovery circuit A4 in the receiver 100A according to the control signal SC to switch the phase of the clock signal CLK1 to the next phase. In some embodiments, the predetermined value PD1 may be an internal circuit parameter of the receiver 100A, such as a control parameter of the clock data recovery circuit A4 or a set value of a cyclic shift register, but the disclosure is not limited thereto.
In some embodiments, by outputting the measurement reference value REF1 to the receiver 100A, the eye measurement apparatus 100 can easily determine and control the phase of the clock signal CLK to measure the eye. However, in some cases, if the measured reference value REF1 is used to change the phase of the clock signal CLK, the operation of the receiver 100A may be inaccurate. In these cases, the receiver 100A may be ensured to operate correctly by outputting the preset value PD1 to the receiver 100A. Thus, the eye diagram measuring apparatus 100 can be prevented from measuring an incorrect eye diagram.
Fig. 6 is a flow chart of an eye diagram measurement method 600 according to some embodiments of the present disclosure. For ease of understanding, the eye diagram measurement method 600 will be described with reference to the preceding figures.
In operation S610, one of a preset value PD1 and a measurement reference value REF1 associated with the receiver 100A is output to the receiver 100A according to the control signal SC to switch a phase of the clock signal CLK.
For example, as shown in FIG. 5, the phase control circuitry 150 may output the measurement reference REF1 to the receiver 100A to control the phase of the clock signal CLK. Alternatively, to avoid affecting the operation of the receiver 100A, the phase controller circuitry 150 may output a preset value PD1 to the receiver 100A.
In operation S620, one of the internal signals S1 to S3 is mapped to the data signal D1. For example, as shown in FIG. 2, the mapping circuitry 110 may generate the data signal D1 by extracting a portion of the bits of the plurality of internal signals S1-S3. Equivalently, through operation S620, the plurality of internal signals S1-S3, which may have different numbers of bits, are converted into a data signal (e.g., the data signal D2 of fig. 2) having the same number of bits.
In operation S630, a counting operation is performed according to the data signal D1 and the plurality of signal values Q1-QM to generate a plurality of counting signals C1-CM.
For example, as previously shown in FIG. 3, when the acknowledge data signal D1 is identical to the signal value Q1 (e.g., 127), the processing circuit 310-1 outputs a trigger signal TR1 having a logic value of 1. In this manner, the counter 320-1 performs a counting operation in response to the trigger signal TR1 to update the count signal C1. In this condition, the data signal D1 is different from the plurality of signal values Q2-QM, and the plurality of processing circuits 310-2-310-M output the trigger signals TR 2-TRM having a logic value 0. In this manner, the counters 320-2 to 320-M do not perform a counting operation in response to the trigger signals TR2 to TRM, and do not update the count signals C2 to CM.
In operation S640, a plurality of count signals C1-CM are mapped to a plurality of eye measurement signals E1-EM, respectively. For example, as shown in FIG. 4, the mapping circuitry 130 may perform a logical OR operation on the count signals C1-CM received during a predetermined period, respectively, to generate a plurality of eye measurement signals E1-EM.
In operation S650, a plurality of eye pattern measurement signals E1-EM are stored, and it is determined whether the measurement count reaches a predetermined count. If yes, executing operation S660; if not, operation S610 is performed.
As previously shown in FIG. 1, the memory circuitry 140 may store the count signals C1-CM and/or the eye measurement signals E1-EM to provide the statistics R2 and/or the eye measurement result R1 for analysis by the external system 100B. In some embodiments, the external system 100B may collect a plurality of eye measurement signals E1-EM corresponding to different phases to generate an eye measurement result R1. By determining the predetermined number of times, a certain amount of the plurality of eye measurement signals E1-EM can be collected and provided to the external system 100B. For example, the predetermined number of times may be set to 512. Before the number of measurements does not reach 512, by repeatedly performing operation S610, the phase control circuitry 150 may control the receiver 100A to switch the clock signal CLK to the next phase to collect the plurality of eye measurement signals E1-EM corresponding to the next phase.
In operation S660, the predetermined value PD1 is output to the receiver 100A to end the eye diagram measurement. After a sufficient amount of eye measurement signals E1-EM are collected, the external system 100B can generate an eye measurement result R1 accordingly. Thus, the phase control circuitry 150 may output the predetermined value PD1 to the receiver 100A to restore the original operation of the receiver 100A.
The steps of the eye diagram measurement method 600 described above are merely examples and are not limited to being performed in the order illustrated in this example. The various operations under the eye measurement method 600 may be added, replaced, omitted, or performed in a different order as appropriate without departing from the manner and scope of operation of the various embodiments of the present disclosure.
In summary, the eye diagram measuring device and the eye diagram measuring method provided by the present invention can be used for measuring signals with multiple levels and can provide the function of counting signal values.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be variously modified and modified by those skilled in the art without departing from the spirit and scope of the present invention, and the scope of the present invention is accordingly defined by the appended claims.
Claims (14)
1. An eye diagram measuring apparatus, comprising:
a first mapping circuitry for mapping one of a plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits;
a counting circuitry for performing a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits to generate a plurality of count signals;
a second mapping circuitry for mapping the count signals to eye pattern measurement signals corresponding to a current phase, respectively; and
a memory circuit system for storing the eye pattern measurement signals to provide the eye pattern measurement signals to an external system to generate an eye pattern measurement result of the electronic device,
the second mapping circuitry includes:
the logic circuits are used for executing a plurality of logic OR operations according to the counting signals respectively so as to generate the eye diagram measuring signals.
2. The eye diagram measurement apparatus of claim 1, wherein the first mapping circuitry comprises:
a plurality of bit conversion circuits for generating a plurality of second data signals,
wherein each of the plurality of second data signals has a same number of bits as the predetermined number of bits, and each of the plurality of bit conversion circuits is configured to extract a corresponding one of the plurality of second data signals from a corresponding one of the plurality of internal signals; and
a multiplexer circuit for receiving the plurality of second data signals and outputting one of the plurality of second data signals as the first data signal according to a selection signal.
3. The eye diagram measurement apparatus of claim 1, wherein the counting circuitry comprises:
the plurality of processing circuits are used for respectively comparing the first data signal with the plurality of signal values to output a plurality of trigger signals, wherein a first trigger signal in the plurality of trigger signals indicates that the first data signal is identical to a first signal value in the plurality of signal values; and
a plurality of counters for determining whether to execute the counting operation according to the plurality of trigger signals respectively to output a plurality of counting signals,
when a first counter of the plurality of counters receives the first trigger signal, the first counter performs the counting operation to update a corresponding one of the plurality of counting signals.
4. The eye diagram measurement apparatus according to claim 3, wherein a plurality of second trigger signals of the plurality of trigger signals indicate that the first data signal is different from a remaining signal value of the plurality of signal values, and the remaining counter of the plurality of counters does not perform the counting operation when the remaining counter receives the plurality of second trigger signals.
5. The eye diagram measurement apparatus of claim 1, wherein the memory circuitry is further configured to store the plurality of count signals to provide the plurality of count signals to the external system to generate a statistical result associated with the current phase.
6. The eye diagram measurement apparatus according to claim 1, further comprising:
a phase control circuitry for providing one of an eye measurement value and a predetermined value associated with the electronic device to a clock data recovery circuit in the electronic device according to a control signal to switch a phase of a clock signal of the electronic device from the current phase to one phase at a time.
7. The eye diagram measurement apparatus of any one of claims 1-6, wherein the first data signal is a pulse amplitude modulation signal.
8. An eye diagram measuring method, comprising:
mapping one of a plurality of internal signals of an electronic device to a first data signal with a preset bit number;
performing a counting operation according to the first data signal and a plurality of signal values associated with the preset bit number to generate a plurality of counting signals;
mapping the count signals to eye pattern measurement signals corresponding to a current phase; and
storing the eye pattern measurement signals to provide the eye pattern measurement signals to an external system to generate an eye pattern measurement result of the electronic device,
mapping the plurality of count signals to the plurality of eye measurement signals, respectively, includes:
and performing a plurality of logical OR operations according to the plurality of counting signals respectively to generate a plurality of eye pattern measurement signals.
9. The eye diagram measurement method of claim 8, wherein mapping one of the plurality of internal signals to the first data signal comprises:
extracting a plurality of second data signals from the plurality of internal signals respectively; and
one of the plurality of second data signals is output as the first data signal according to a selection signal.
10. The eye diagram measurement method of claim 8, wherein generating the plurality of count signals comprises:
comparing the first data signal with the plurality of signal values respectively to output a plurality of trigger signals, wherein a first trigger signal in the plurality of trigger signals indicates that the first data signal is identical to a first signal value in the plurality of signal values; and
determining whether to execute the counting operation by a plurality of counters according to the plurality of trigger signals respectively so as to output a plurality of counting signals,
when a first counter of the plurality of counters receives the first trigger signal, the first counter performs the counting operation to update a corresponding one of the plurality of counting signals.
11. The eye diagram measurement method of claim 10, wherein a plurality of second trigger signals of the plurality of trigger signals indicate that the first data signal is different from a remaining signal value of the plurality of signal values, and wherein the remaining counter of the plurality of counters does not perform the counting operation when the remaining counter receives the plurality of second trigger signals.
12. The eye diagram measurement method of claim 11, further comprising:
the plurality of count signals are stored to provide the plurality of count signals to the external system to generate a statistical result associated with the current phase.
13. The eye diagram measurement method of claim 8, further comprising:
providing one of an eye diagram measurement value and a preset value associated with the electronic device to a clock data recovery circuit in the electronic device according to a control signal so as to switch the phase of a clock signal of the electronic device from the current phase to one phase at a time.
14. The method according to any one of claims 9 to 13, wherein the first data signal is a pulse amplitude modulation signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810734744.4A CN110688814B (en) | 2018-07-06 | 2018-07-06 | Eye pattern measuring device and eye pattern measuring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810734744.4A CN110688814B (en) | 2018-07-06 | 2018-07-06 | Eye pattern measuring device and eye pattern measuring method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110688814A CN110688814A (en) | 2020-01-14 |
| CN110688814B true CN110688814B (en) | 2023-04-28 |
Family
ID=69107227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810734744.4A Active CN110688814B (en) | 2018-07-06 | 2018-07-06 | Eye pattern measuring device and eye pattern measuring method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110688814B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106419921A (en) * | 2015-08-04 | 2017-02-22 | 群联电子股份有限公司 | Eye-width detector, memory storage device, eye-width detection method for data signal |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030097226A1 (en) * | 2001-11-21 | 2003-05-22 | Synthesys | Apparatus and method for sampling eye diagrams with window comparators |
| US7606297B2 (en) * | 2002-03-15 | 2009-10-20 | Synthesys Research, Inc. | Method and system for creating an eye diagram using a binary data bit decision mechanism |
| US20100097087A1 (en) * | 2008-10-20 | 2010-04-22 | Stmicroelectronics, Inc. | Eye mapping built-in self test (bist) method and apparatus |
-
2018
- 2018-07-06 CN CN201810734744.4A patent/CN110688814B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106419921A (en) * | 2015-08-04 | 2017-02-22 | 群联电子股份有限公司 | Eye-width detector, memory storage device, eye-width detection method for data signal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110688814A (en) | 2020-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10782344B2 (en) | Technique for determining performance characteristics of electronic devices and systems | |
| US9136952B2 (en) | Pulse amplitude modulation (PAM) bit error test and measurement | |
| US8077063B2 (en) | Method and system for determining bit stream zone statistics | |
| US8542764B2 (en) | Power and area efficient SerDes transmitter | |
| TWI679860B (en) | Eye diagram measurement device and eye diagram measurement method | |
| US8952835B1 (en) | Background calibration of aperture center errors in analog to digital converters | |
| CN110688814B (en) | Eye pattern measuring device and eye pattern measuring method | |
| CN101455023B (en) | Data identification device and error measurement device | |
| KR101541175B1 (en) | Delay line time-to-digital converter | |
| JP2008172657A (en) | Receiver | |
| US8588355B2 (en) | Timing recovery controller and operation method thereof | |
| US20190215094A1 (en) | Digital bus noise suppression | |
| TW202008718A (en) | Signal interface system and data transmission method thereof | |
| CN104956442A (en) | Apparatus and method for storage device reading | |
| EP1646882A1 (en) | Integrated circuit with bit error test capability | |
| CN107241101B (en) | Data serializing circuit | |
| US20230223946A1 (en) | Analog-to-digital converter to identify properties of transmitted signals | |
| SE540997C2 (en) | Method, system and computer program for synchronizing data streams with unknown delay | |
| TWI707544B (en) | Signal detector and signal detection method | |
| CN111239476B (en) | Signal detector and signal detection method | |
| CN109857687B (en) | Measurement system and data transmission interface | |
| KR100667546B1 (en) | Test device and method of serial data link | |
| CN114461473A (en) | Method for detecting time sequence of serializer, detection circuit and electronic device | |
| CN110350911A (en) | The counting circuit of performance monitor unit | |
| JP2009043195A (en) | Data transmitter, data receiver, data transfer device, and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |