CN110688814A

CN110688814A - Eye pattern measuring device and eye pattern measuring method

Info

Publication number: CN110688814A
Application number: CN201810734744.4A
Authority: CN
Inventors: 康文柱; 陈昱竹; 高洵伟
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Priority date: 2018-07-06
Filing date: 2018-07-06
Publication date: 2020-01-14
Anticipated expiration: 2038-07-06
Also published as: CN110688814B

Abstract

An eye pattern measuring device and an eye pattern measuring method. The eye diagram measuring device comprises a first mapping circuit system, a counting circuit system, a second mapping circuit system and a memory circuit system. The first mapping circuit system maps one of a plurality of internal signals of an electronic device to a first data signal with a preset bit number. The counting circuit system executes a counting operation according to the first data signal and a plurality of signal values related to the preset bit number so as to generate a plurality of counting signals. The second mapping circuitry maps the plurality of count signals to a plurality of eye measurement signals corresponding to a current phase, respectively. The memory circuit system stores the plurality of eye pattern measurement signals to provide the plurality of eye pattern measurement signals to an external system to generate an eye pattern measurement result of the electronic device. The eye pattern measuring device and the eye pattern measuring method can be used for measuring signals with multiple levels and can also provide the function of counting signal values.

Description

Eye pattern measuring device and eye pattern measuring method

Technical Field

The present disclosure relates to an eye pattern measuring apparatus, and more particularly, to an eye pattern measuring apparatus and an eye pattern measuring method capable of measuring signals with multiple levels.

Background

Eye diagrams (eye diagrams) are a common way to measure signal quality. The larger the eye height (eye height) and/or eye width (eye width) in the eye diagram, the better the measured signal quality.

As data transmission speeds become higher, multi-level signal coding using Pulse-amplitude modulation (PAM) signals and the like is increasingly applied. However, the conventional eye pattern measuring circuit is only suitable for measuring non-return-to-zero (NRZ) encoded signals and is not suitable for the above applications.

Disclosure of Invention

In order to solve the above problems, some aspects of the present disclosure provide an eye diagram measuring apparatus, which includes a first mapping circuit system, a counting circuit system, a second mapping circuit system, and a memory circuit system. The first mapping circuit system is used for mapping one of a plurality of internal signals of an electronic device to a first data signal with a preset bit number. The counting circuit system is used for executing a counting operation according to the first data signal and a plurality of signal values related to the preset bit number so as to generate a plurality of counting signals. The second mapping circuitry is configured to map the plurality of count signals to a plurality of eye measurement signals corresponding to a current phase, respectively. The memory circuit system is used for storing the plurality of eye pattern measurement signals and providing the plurality of eye pattern measurement signals to an external system to generate an eye pattern measurement result of the electronic device.

In some embodiments, the first mapping circuitry includes a plurality of bit conversion circuits and a multiplexer circuit. The bit conversion circuits are used for generating a plurality of second data signals, wherein the bit number of each of the second data signals is equal to the preset bit number, and each of the bit conversion circuits is used for extracting a corresponding one of the second data signals from a corresponding one of the internal signals. The multiplexer circuit is used for receiving the plurality of second data signals and outputting one of the plurality of second data signals as the first data signal according to a selection signal.

In some embodiments, the counting circuitry includes a plurality of processing circuits and a plurality of counters. The processing circuits are used for respectively comparing the first data signal with the signal values to output a plurality of trigger signals, wherein a first trigger signal in the trigger signals indicates that the first data signal is identical to a first signal value in the signal values. The counters are used for determining whether to execute the counting operation according to the trigger signals respectively so as to output the counting signals. When a first counter of the counters receives the first trigger signal, the first counter performs the counting operation to update a corresponding one of the counting signals.

In some embodiments, a plurality of second trigger signals of the plurality of trigger signals indicate that the first data signal is different from a remaining signal value of the plurality of signal values, and the remaining counters do not perform the counting operation when the remaining counters of the plurality of counters receive the plurality of second trigger signals.

In some embodiments, the memory circuitry is further configured to store the plurality of count signals to provide the plurality of count signals to the external system to generate a statistical result associated with the current phase.

In some embodiments, the second mapping circuitry comprises a plurality of logic circuits. The plurality of logic circuits are used for executing a plurality of logic OR operations according to the plurality of counting signals respectively so as to generate the plurality of eye pattern measuring signals.

In some embodiments, the eye measurement device further comprises phase control circuitry. The phase control circuit system is used for providing one of a preset value and an eye diagram measuring value related to the electronic device to a clock data recovery circuit in the electronic device according to a control signal so as to switch the phase of a clock signal of the electronic device from the current phase to a phase at a time.

In some embodiments, the first data signal is a pulse amplitude modulation signal.

Some embodiments of the present disclosure provide an eye diagram measurement method, which includes the following operations: mapping one of a plurality of internal signals of an electronic device to a first data signal with a preset bit number; performing a counting operation according to the first data signal and a plurality of signal values associated with the preset bit number to generate a plurality of counting signals; mapping the counting signals to a plurality of eye pattern measuring signals corresponding to a current phase respectively; and storing the plurality of eye pattern measurement signals to provide the plurality of eye pattern measurement signals to an external system to generate an eye pattern measurement result of the electronic device.

In some embodiments, mapping one of the plurality of internal signals to the first data signal comprises: extracting a plurality of second data signals from the plurality of internal signals, respectively; and outputting one of the plurality of second data signals as the first data signal according to a selection signal.

In some embodiments, generating the plurality of count signals comprises: comparing the first data signal with the plurality of signal values respectively to output a plurality of trigger signals, wherein a first trigger signal of the plurality of trigger signals indicates that the first data signal is identical to a first signal value of the plurality of signal values; and determining whether to perform the counting operation according to the trigger signals by a plurality of counters respectively so as to output the counting signals, wherein when a first counter of the counters receives the first trigger signal, the first counter performs the counting operation so as to update a corresponding one of the counting signals.

In some embodiments, the eye diagram measuring method further comprises: storing the plurality of count signals to provide the plurality of count signals to the external system to generate a statistical result associated with the current phase.

In some embodiments, mapping the count signals to the eye measurement signals respectively comprises: and executing a plurality of logical OR operations according to the plurality of counting signals respectively to generate the plurality of eye pattern measuring signals.

In some embodiments, the eye diagram measuring method further comprises: providing one of a preset value and an eye diagram measuring value related to the electronic device to a clock data recovery circuit in the electronic device according to a control signal so as to switch the phase of a clock signal of the electronic device from the current phase to a phase at a time.

In summary, the eye pattern measuring apparatus and the eye pattern measuring method provided by the present disclosure can be used for measuring signals with multiple levels and provide the function of counting signal values.

Drawings

The foregoing and other objects, features, advantages and embodiments of the disclosure will be more readily understood from the following description taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic view of an eye measurement device according to some embodiments of the present disclosure;

fig. 2 is a schematic diagram illustrating mapping circuitry as in fig. 1 according to some embodiments of the disclosure;

FIG. 3 is a schematic diagram illustrating the counting circuitry of FIG. 1 according to some embodiments of the disclosure;

FIG. 4 is a schematic diagram illustrating mapping circuitry as in FIG. 1 according to some embodiments of the disclosure;

fig. 5 is a schematic diagram illustrating phase control circuitry as in fig. 1 according to some embodiments of the disclosure; and

fig. 6 is a flowchart illustrating an eye diagram measurement method according to some embodiments of the disclosure.

Detailed Description

All terms used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the words discussed herein in the context of this specification is by way of example only and should not be construed as limiting the scope or meaning of the present disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.

It will be understood that the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections. These elements, components, regions, layers and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. As used herein, "and/or" includes any and all combinations of one or more of the associated items.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to the mutual operation or action of two or more elements.

As used herein, the term "circuit system" generally refers to a single system comprising one or more circuits (circuits). The term "circuit" broadly refers to an object connected in some manner by one or more transistors and/or one or more active and passive components to process a signal.

Referring to fig. 1, fig. 1 is a schematic view illustrating an eye diagram (eye diagram) measurement apparatus 100 according to some embodiments of the present disclosure. In some embodiments, the eye diagram measuring apparatus 100 may be used for measuring a plurality of signals in an electronic device (such as the receiver 100A, but not limited thereto). The receiver 100A may include an analog-to-digital converter a1, a feed-forward equalizer a2, a decision device A3, a clock data recovery circuit a4, a decision feedback circuit a5, and so on, but the disclosure is not limited thereto.

As shown in fig. 1, the eye diagram measuring apparatus 100 may be used for measuring a plurality of internal signals S1-S3 of the receiver 100A, such as the output of the adc a1 in the receiver 100A, the output of the feed-forward equalizer a2, and the input of the decision device A3. The above-mentioned internal signals S1-S3 are only examples, and other signals of the receiver 100A can be measured by the eye diagram measuring apparatus 100.

In some embodiments, the eye measurement device 100 includes mapping circuitry 110, counting circuitry 120, mapping circuitry 130, and memory circuitry 140.

The mapping circuitry 110 is coupled to the internal nodes of the receiver 100A to receive the internal signals S1-S3. The mapping circuitry 110 is used to map one of the internal signals S1-S3 to the data signal D1. In some embodiments, the number of bits of each of the internal signals S1-S3 is different from one another. Through the mapping circuitry 110, a plurality of internal signals S1-S3 with different bit numbers can be mapped to the data signal D1 with a predetermined bit number.

The counting circuitry 120 is coupled to the mapping circuitry 110 to receive the data signal D1. In some embodiments, the counting circuitry 120 is configured to perform a counting operation according to the data signal D1 and the signal values Q1 QM to generate a plurality of counting signals C1 CM. In some embodiments, the signal values Q1-QM are associated with a predetermined number of bits of the data signal D1. For example, if the predetermined number of bits is 7 bits, the signal values Q1-QM can be 0, 1, …, 27-1 in sequence. When the data signal D1 is identical to one of the signal values Q1 QM, the counting circuitry 120 performs the counting operation to update a corresponding one of the count signals C1 CM. Thus, by observing the plurality of count signals C1 to CM, the corresponding signal value of the data signal D1 measured at each corresponding phase can be confirmed. The operation will be described with reference to fig. 3 in the following paragraphs.

By setting a plurality of signal values Q1-QM, the signal values of the data signal D1 at a plurality of different levels can be measured. In other words, the data signal D1 may be a Pulse-amplitude modulation (PAM) signal with multiple levels, but the invention is not limited thereto.

The mapping circuitry 130 is coupled to the counting circuitry 120 to receive a plurality of counting signals C1-CM. In some embodiments, the mapping circuit system 130 maps the counting signals C1-CM to the eye measurement signals E1-EM, wherein the counting signals C1-CM correspond to the eye measurement signals E1-EM, and the eye measurement signals E1-EM correspond to the current phase of the clock signal CLK output by the clock data recovery circuit a4 in the receiver 100A. For example, when the clock signal CLK is at the current phase, the count signal C1 is updated and none of the remaining count signals C2 CM are updated, the eye measurement signal E1 has a logic value of 1 and the remaining eye measurement signals E2 EM have a logic value of 0. In other words, in this example, the eye measurement signals E1-EM confirm that the current phase of the data signal D1 is the same as one of the signal values Q1-QM corresponding to the counter signal C1.

The memory circuitry 140 is coupled to the counting circuitry 120 for receiving the counting signals C1 CM and to the mapping circuitry 130 for receiving the eye measurement signals E1 EM. In some embodiments, the memory circuitry 140 is configured to store a plurality of count signals C1-CM and/or a plurality of eye measurement signals E1-EM. In some embodiments, the memory circuit system 140 is coupled to an external system 100B for transmitting a plurality of counting signals C1-CM and/or a plurality of eye measurement signals E1-EM to the external system 100B. In some embodiments, the memory circuitry 140 may be implemented by registers and/or memory.

The external system 100B may generate the eye measurement result R1 by plotting the plurality of eye measurement signals E1-EM, and may generate a statistical result R2 by analyzing the plurality of count signals C1-CM. In some embodiments, the statistical result R2 may be a histogram (histogram) showing the times that the data signal D1 is identical to the respective signal values Q1 QM at the current phase.

In some embodiments, the external system 100B may include a signal analysis software or design tool implemented via a processor. In some embodiments, the external system 100B may be an oscilloscope. The above embodiments of the external system 100 are only examples, and the disclosure is not limited thereto.

For ease of understanding, fig. 1 only shows one set of mapping circuitry 110, but the disclosure is not limited thereto. In some applications, the eye measurement apparatus 100 may be provided with more sets of mapping circuitry 110, wherein the plurality of mapping circuitry 110 operate in parallel to receive more different internal signals from the receiver 100A. In these embodiments, as shown in fig. 1, the eye diagram measuring apparatus 100 further includes a buffer circuit system 115 coupled between the mapping circuit system 110 and the counting circuit system 120. Under this condition, the buffer circuitry 115 may buffer the data signals D1 output from the mapping circuitry 110 to synchronize the data signals D1, and output the data signals D1 as data signals D1' to the counting circuitry 120 sequentially. In some embodiments, the buffer circuitry 115 may be implemented by a first-in-first-out (FIFO) circuit, but the present disclosure is not limited thereto. In some other embodiments, the mapping circuitry 110 may transmit the data signals D1 to the counting circuitry 120 without the buffer circuitry 115.

In some embodiments, as shown in fig. 1, the eye diagram measuring apparatus 100 further includes a phase control circuit system 150. Phase control circuitry 150 is coupled to memory circuitry 140 and to receiver 100A. The phase control circuitry 150 is coupled to the feed forward equalizer a2, the decision device A3, and/or the clock data recovery circuit a 4. In some embodiments, after the memory circuitry 140 stores the eye measurement signals E1-EM corresponding to the current phase, the phase control circuitry 150 is configured to control circuitry (e.g., feed-forward equalizer A2, decision device A3, and/or clock data recovery circuit A4) in the receiver 100A to switch the phase of the clock signal CLK to the next phase according to a control signal SC. Thus, the eye measurement apparatus 100 can continuously measure a plurality of eye measurement signals E1-EM corresponding to the next phase.

The following paragraphs will describe the implementation of the above-mentioned multiple circuit systems, but the present disclosure is not limited to the following embodiments.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating the mapping circuitry 110 of fig. 1 according to some embodiments of the disclosure. For ease of understanding, like elements in fig. 1 and 2 will be designated with the same reference numerals.

In some embodiments, the mapping circuitry 110 includes a plurality of bit conversion circuits 210-1-210-3 and a multiplexer circuit 220. The bit conversion circuits 210-1 to 210-3 are respectively coupled to the output of the analog-to-digital converter A1, the output of the feed-forward equalizer A2 and the input of the decision device A3 in FIG. 1 to respectively receive the internal signals S1 to S3.

In some embodiments, the bit conversion circuits 210-1-210-3 generate the data signals D2 according to the internal signals S1-S3, wherein each data signal D2 has a same number of bits as the predetermined number of bits. In some embodiments, each of the bit conversion circuits 210-1-210-3 extracts a corresponding data signal D2 according to a corresponding one of the internal signals S1-S3. Taking the Bit conversion circuit 210-1 as an example, the Bit conversion circuit 210-1 can extract a part of bits (e.g., part of Least Significant Bits (LSBs) of the internal signal S1) in the internal signal S1 to generate the corresponding data signal D2. Similarly, the bit conversion circuit 210-2 or 210-3 can also extract a portion of the bits in the internal signal S2 or S3 to generate the corresponding data signal D2.

The above-mentioned arrangement of the bit conversion circuits 210-1 to 210-3 is merely an example, and other ways of generating the data signal D2 with a fixed number of bits are also within the scope of the present disclosure.

The multiplexer circuit 220 is coupled to the bit conversion circuits 210-1 to 210-3 for receiving the data signals D2. The multiplexer circuit 220 is used for outputting one of the data signals D2 as the data signal D1 according to the selection signal SEL. In some embodiments, the multiplexer circuit 220 may be implemented by a plurality of sets of switches, but the disclosure is not limited thereto.

In some embodiments, the mapping circuitry 110 may further include a switching circuit (not shown) for determining whether to output the data signal D1 to the counting circuitry 120 according to an enable signal (not shown). In other words, with the above arrangement, the eye diagram measuring apparatus 100 can determine whether to perform the eye diagram measuring operation according to the enable signal.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating the counting circuitry 120 of fig. 1 according to some embodiments of the disclosure. For ease of understanding, like elements in fig. 1 and 3 will be designated with the same reference numerals.

In some embodiments, the counting circuitry 120 includes a plurality of processing circuits 310-1-310-M and a plurality of counters 320-1-320-M. The plurality of processing circuits 310-1-310-M are coupled to the mapping circuitry 110 for receiving the data signal D1. The number of the processing circuits 310-1 to 310-M is related to the predetermined number of bits. For example, when the predetermined number of bits is 7, the number of the processing circuits 310-1 to 310-M is 27.

The processing circuits 310-1 to 310-M respectively compare the data signal D1 with the signal values Q1 to QM to generate trigger signals TR1 to TRM. Wherein, when the data signal D1 is identical to one of the signal values Q1 QM, a corresponding one of the processing circuits 310-1-310-M outputs a trigger signal having a first logic value (e.g., logic value 1). Conversely, when the confirmation data signal D1 is different from one of the signal values Q1 QM, a corresponding one of the processing circuits 310-1-310-M outputs a trigger signal having a second logic value (e.g., logic value 0).

For example, assume that the predetermined number of bits is 7, and the processing circuit 310-1 is configured to compare the data signal D1 with the signal value Q1 (i.e., 27-1 equals 127). When the data signal D1 is the same as the signal value Q1, the processing circuit 310-1 will output the trigger signal TR1 with logic value 1. In addition, under this condition, the data signal D1 is different from the remaining signal values Q2 QM, so the remaining processing circuits 310-2 through 310-M will output a plurality of trigger signals TR2 through TRM with logic value 0. With the above arrangement, it is possible to determine what the signal value of the data signal D1 measured at the current phase is based on the trigger signals TR1 to TRM.

In some embodiments, the plurality of processing circuits 310-1-310-M may be implemented by comparators. In some embodiments, the plurality of processing circuits 310-1-310-M may be implemented by logic circuits similar to or having the same function as an anti-exclusive OR gate. The above embodiments of the processing circuits 310-1 to 310-M are exemplary, and other embodiments are also within the scope of the present disclosure.

The counters 320-1 to 320-M are respectively coupled to the processing circuits 310-1 to 310-M to receive the trigger signals TR1 to TRM. The counters 320-1-320-M perform a counting operation according to the trigger signals TR 1-TRM, respectively, to generate a plurality of count signals when one of the trigger signals TR 1-TRM has a first logic value, and a corresponding one of the counters 320-1-320-M performs a counting operation to update a corresponding one of the count signals C1-CM.

For example, initially, the count signals C1 CM are all 0. When the trigger signal TR1 has a first logic value (i.e., logic 1) and the other trigger signals TR2 TRM have a second logic value (i.e., logic 0), the trigger signal TR1 has a logic value of 1 and the remaining trigger signals TR2 TRM have a logic value of 0. In this condition, the counter 320-1 performs a counting operation to increase the count signal C1 from 0 to 1 in response to the trigger signal TR1 having a logic value of 1. Likewise, the remaining counters 320-2 to 320-M do not perform a counting operation in response to the trigger signals TR2 to TRM having a logic value of 0. Thus, the remaining count signals C2 to CM are not updated and remain at 0.

As described above, the external system 100B can generate a statistical result R2 by analyzing the plurality of counting signals C1-CM. For example, by analyzing the number of times the count signal C1 is updated, the number of times the data signal D1 is the same as the signal value Q1 (i.e., 127) can be counted. By analogy, the number of times that the data signal D1 is identical to each of the signal values Q1 QM can be counted by recording and analyzing all the count signals C1-CM to generate the statistical result R2.

For ease of understanding, FIG. 3 only shows one set of processing circuits 310-1 to 310-M, but the disclosure is not limited thereto. In some embodiments, the counting circuitry 120 may be configured with more processing circuits 310-1-310-M, wherein the processing circuits 310-1-310-M operate in parallel to increase processing efficiency. In these embodiments, the counting circuitry 120 further includes a plurality of adders and other logic circuits such as registers to sum up the flip-flops corresponding to each of the plurality of processing circuits 310-1 to 310-M.

The above arrangement of the counting circuit 120 is merely an example, and various arrangements for achieving the same operation are also covered by the present disclosure.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating the mapping circuitry 130 of fig. 1 according to some embodiments of the disclosure. For ease of understanding, like elements in fig. 1 and 4 will be designated with the same reference numerals.

In some embodiments, the mapping circuitry 130 includes a plurality of logic circuits 410-1-410-M. The plurality of logic circuits 410-1 to 410-M are respectively coupled to the plurality of counters 320-1 to 320-M of FIG. 3 for receiving the plurality of count signals C1 to CM. Each of the logic circuits 410-1-410-M is configured to perform an OR operation according to a corresponding one of the count signals C1-CM to generate a corresponding one of the eye measurement signals E1-EM.

For example, the logic circuit 410-1 may perform a logical OR operation according to all the count signals C1 received during a predetermined period to generate the eye measurement signal E1. For example, at the current phase of the clock signal CLK, the data signal D1 has a signal value of 127 (i.e., the signal value Q1), and the trigger signal TR1 will continue to be 1 while continuously updating the count signal C1 such that the count signal C1 is at least 1. Thus, during the period when the clock signal CLK is at the current phase, the logic circuit 410-1 generates the eye measurement signal E1 with a logic value of 1 according to the count signal C1. Equivalently, the eye measurement signal E1 with a logic value of 1 may be used to indicate that the signal value of the data signal D1 is the same as the signal value 127 at the current phase of the clock signal CLK.

Continuing with the above example, since the data signal D1 has a signal value of 127 and is different from the other signal values Q2 QM, the trigger signals TR2 TRM will continue to be 0 without updating the count signals C2 CM, so that the count signals C2 CM are maintained at 0. Thus, the logic circuits 410-2-410-M generate the eye measurement signals E2-EM with logic value 0 according to the count signals C2-CM. Equivalently, the eye measurement signals E2-EM with logic value 0 may indicate that the signal value of the data signal D1 was different from the other signal values Q2-QM at the current phase of the clock signal CLK.

The logic circuits 410-1 to 410-M for performing logic OR operations are described above as an example, but the disclosure is not limited thereto. Various logic circuits that have been updated to detect the count signals C1-CM can be used to implement the logic circuits 410-1-410-M.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating the phase control circuitry 150 of fig. 1 according to some embodiments of the disclosure. For ease of understanding, like elements in fig. 1 and 5 will be designated with the same reference numerals.

The phase control circuitry 150 includes a multiplexer circuit 510. The multiplexer circuit 510 is used for outputting one of a default PD1 and a measurement reference REF1 associated with the receiver 100A to the clock data recovery circuit a4 in the receiver 100A according to the control signal SC to switch the phase of the clock signal CLK1 to the next phase. In some embodiments, the default PD1 may be an internal circuit parameter of the receiver 100A, such as a control parameter of the clock data recovery circuit a4 or a setting value of a cyclic shift register, but not limited thereto.

In some embodiments, by outputting the measurement reference REF1 to the receiver 100A, the eye diagram measurement apparatus 100 can easily identify and control the phase of the clock signal CLK to measure the eye diagram. However, in some cases, if the phase of the clock signal CLK is changed by using the REF1, the receiver 100A may operate inaccurately. In these cases, the receiver 100A can be ensured to operate correctly by outputting the preset value PD1 to the receiver 100A. Thus, the eye pattern measuring apparatus 100 can be prevented from measuring an incorrect eye pattern.

Fig. 6 is a flowchart illustrating an eye diagram measurement method 600 according to some embodiments of the disclosure. For ease of understanding, the eye measurement method 600 will be described with reference to the foregoing figures.

In operation S610, one of a default PD1 and a measurement reference REF1 associated with the receiver 100A is output to the receiver 100A according to the control signal SC to switch a phase of the clock signal CLK.

For example, as shown in fig. 5, the phase control circuitry 150 may output a measurement reference REF1 to the receiver 100A to control the phase of the clock signal CLK. Alternatively, to avoid affecting the operation of the receiver 100A, the phase controller circuitry 150 may output the preset value PD1 to the receiver 100A.

In operation S620, one of the internal signals S1-S3 is mapped to the data signal D1. For example, as shown in FIG. 2, the mapping circuitry 110 may generate the data signal D1 by retrieving a portion of the bits of the internal signals S1-S3. Equivalently, a plurality of internal signals S1-S3 with possibly different bit numbers are converted into data signals with the same bit number (e.g., the data signal D2 of FIG. 2) by operation S620.

In operation S630, a counting operation is performed according to the data signal D1 and the signal values Q1 QM to generate a plurality of counting signals C1 CM.

For example, as shown in FIG. 3, when the data signal D1 is identical to the signal value Q1 (e.g., 127), the processing circuit 310-1 outputs the trigger signal TR1 with logic value 1. Thus, the counter 320-1 performs a counting operation in response to the trigger signal TR1 to update the count signal C1. Under this condition, the data signal D1 is different from the plurality of signal values Q2 QM, and the plurality of processing circuits 310-2 through 310-M output the trigger signals TR2 through TRM having a logic value 0. Thus, the counters 320-2 to 320-M do not perform the counting operation in response to the trigger signals TR2 to TRM without updating the count signals C2 to CM.

In operation S640, the plurality of count signals C1 CM to the plurality of eye diagram measurement signals E1 EM are mapped, respectively. For example, as shown in FIG. 4, the mapping circuitry 130 may perform a logical OR operation on the count signals C1 CM received within a predetermined period to generate a plurality of eye measurement signals E1 EM, respectively.

In operation S650, the eye pattern measurement signals E1-EM are stored, and it is determined whether the measurement count reaches a predetermined count. If yes, perform operation S660; if not, operation S610 is performed.

As shown in FIG. 1, the memory circuit system 140 may store the count signals C1-CM and/or the eye measurement signals E1-EM for the external system 100B to analyze to generate the statistical result R2 and/or the eye measurement result R1. In some embodiments, the external system 100B may collect a plurality of eye measurement signals E1-EM corresponding to different phases to generate an eye measurement result R1. By determining the predetermined number of times, a certain amount of the plurality of eye measurement signals E1-EM may be collected and provided to the external system 100B. For example, the predetermined number of times may be set to 512. Before the number of measurements reaches 512, the phase control circuitry 150 may control the receiver 100A to switch the clock signal CLK to the next phase by repeating operation S610 to collect a plurality of eye measurement signals E1-EM corresponding to the next phase.

In operation S660, the default PD1 is output to the receiver 100A to end the eye diagram measurement. When a sufficient amount of eye measurement signals E1-EM are collected, the external system 100B may generate an eye measurement result R1 accordingly. Therefore, the phase control circuitry 150 can output the default PD1 to the receiver 100A to restore the receiver 100A to its original operation.

The steps of the eye diagram measuring method 600 are merely exemplary, and need not be performed in the order shown in this example. The various operations performed under the eye diagram measurement method 600 may be suitably augmented, replaced, omitted, or performed in a different order without departing from the manner and scope of operation of various embodiments of the present disclosure.

Although the present disclosure has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure is to be determined by the appended claims.

Claims

1. An eye diagram measuring apparatus, comprising:

a first mapping circuitry for mapping one of a plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits;

a counting circuit system for performing a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits to generate a plurality of counting signals;

second mapping circuitry for mapping the plurality of count signals to a plurality of eye measurement signals corresponding to a current phase, respectively; and

the memory circuit system is used for storing the plurality of eye pattern measuring signals so as to provide the plurality of eye pattern measuring signals to an external system to generate an eye pattern measuring result of the electronic device.

2. The eye diagram measurement device of claim 1, wherein the first mapping circuitry comprises:

a plurality of bit conversion circuits for generating a plurality of second data signals,

wherein the bit number of each of the plurality of second data signals is equal to the predetermined bit number, and each of the plurality of bit conversion circuits is configured to extract a corresponding one of the plurality of second data signals from a corresponding one of the plurality of internal signals; and

a multiplexer circuit for receiving the plurality of second data signals and outputting one of the plurality of second data signals as the first data signal according to a selection signal.

3. The eye diagram measurement device according to claim 1, wherein the counting circuitry comprises:

a plurality of processing circuits for comparing the first data signal with the plurality of signal values respectively to output a plurality of trigger signals, wherein a first trigger signal of the plurality of trigger signals indicates that the first data signal is the same as a first signal value of the plurality of signal values; and

a plurality of counters for determining whether to execute the counting operation according to the trigger signals respectively to output the counting signals,

when a first counter of the counters receives the first trigger signal, the first counter performs the counting operation to update a corresponding one of the counting signals.

4. The eye diagram measuring device according to claim 3, wherein a plurality of second trigger signals of the plurality of trigger signals indicate that the first data signal is different from a remaining signal value of the plurality of signal values, and the remaining counters do not perform the counting operation when receiving the plurality of second trigger signals.

5. The eye measurement device of claim 1, wherein the memory circuitry is further configured to store the plurality of count signals to provide the plurality of count signals to the external system to generate a statistical result associated with the current phase.

6. The eye diagram measurement device of claim 1, wherein the second mapping circuitry comprises:

the logic circuits are used for executing a plurality of logic OR operations according to the counting signals respectively so as to generate a plurality of eye pattern measuring signals.

7. The eye diagram measuring device according to claim 1, further comprising:

a phase control circuit system for providing one of an eye diagram measurement value and a preset value related to the electronic device to a clock data recovery circuit in the electronic device according to a control signal so as to switch the phase of a clock signal of the electronic device from the current phase to a phase at a time.

8. The eye diagram measuring device according to any one of claims 1 to 7, wherein the first data signal is a pulse amplitude modulation signal.

9. An eye diagram measuring method, comprising:

mapping one of a plurality of internal signals of an electronic device to a first data signal with a preset bit number;

performing a counting operation according to the first data signal and a plurality of signal values associated with the preset bit number to generate a plurality of counting signals;

mapping the counting signals to a plurality of eye pattern measuring signals corresponding to a current phase respectively; and

the plurality of eye pattern measurement signals are stored to provide the plurality of eye pattern measurement signals to an external system to generate an eye pattern measurement result of the electronic device.

10. The eye measurement method of claim 9, wherein mapping one of the plurality of internal signals to the first data signal comprises:

extracting a plurality of second data signals from the plurality of internal signals, respectively; and

one of the plurality of second data signals is output as the first data signal according to a selection signal.

11. The eye diagram measuring method of claim 9, wherein generating the plurality of count signals comprises:

comparing the first data signal with the plurality of signal values respectively to output a plurality of trigger signals, wherein a first trigger signal of the plurality of trigger signals indicates that the first data signal is identical to a first signal value of the plurality of signal values; and

determining whether to execute the counting operation according to the trigger signals by a plurality of counters respectively so as to output a plurality of counting signals,

12. The eye diagram measuring method of claim 11, wherein a plurality of second trigger signals of the plurality of trigger signals indicate that the first data signal is different from a remaining signal value of the plurality of signal values, and the remaining counter does not perform the counting operation when the remaining counter of the plurality of counters receives the plurality of second trigger signals.

13. The eye diagram measuring method of claim 12, further comprising:

storing the plurality of count signals to provide the plurality of count signals to the external system to generate a statistical result associated with the current phase.

14. The eye measurement method of claim 9, wherein mapping the plurality of count signals to the plurality of eye measurement signals respectively comprises:

and executing a plurality of logical OR operations according to the plurality of counting signals respectively to generate the plurality of eye pattern measuring signals.

15. The eye diagram measuring method of claim 9, further comprising:

providing one of an eye diagram measurement value and a preset value related to the electronic device to a clock data recovery circuit in the electronic device according to a control signal so as to switch the phase of a clock signal of the electronic device from the current phase to a phase at a time.

16. The eye diagram measuring method of any one of claims 9 to 15, wherein the first data signal is a pulse amplitude modulation signal.